Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame^] | 1 | /* Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | #ifndef __KGSL_HFI_H |
| 14 | #define __KGSL_HFI_H |
| 15 | |
| 16 | #include <linux/types.h> |
| 17 | |
| 18 | #define HFI_QUEUE_SIZE SZ_4K /* bytes */ |
| 19 | #define MAX_RSP_PAYLOAD_SIZE 16 /* dwords */ |
| 20 | #define HFI_MAX_MSG_SIZE (SZ_1K>>2) /* dwords */ |
| 21 | |
| 22 | /* Below section is for all structures related to HFI queues */ |
| 23 | enum hfi_queue_type { |
| 24 | HFI_CMD_QUEUE = 0, |
| 25 | HFI_MSG_QUEUE, |
| 26 | HFI_DBG_QUEUE, |
| 27 | HFI_QUEUE_MAX |
| 28 | }; |
| 29 | |
| 30 | /* Add 16B guard band between HFI queues */ |
| 31 | #define HFI_QUEUE_OFFSET(i) \ |
| 32 | ((sizeof(struct hfi_queue_table)) + \ |
| 33 | ((i) * (HFI_QUEUE_SIZE + 16))) |
| 34 | |
| 35 | #define HOST_QUEUE_START_ADDR(hfi_mem, i) \ |
| 36 | ((hfi_mem)->hostptr + HFI_QUEUE_OFFSET(i)) |
| 37 | |
| 38 | #define GMU_QUEUE_START_ADDR(hfi_mem, i) \ |
| 39 | ((hfi_mem)->gmuaddr + HFI_QUEUE_OFFSET(i)) |
| 40 | |
| 41 | #define HFI_IRQ_MSGQ_MASK 0x1 |
| 42 | #define HFI_IRQ_DBGQ_MASK 0x2 |
| 43 | #define HFI_IRQ_BLOCKED_MSG_MASK 0x4 |
| 44 | #define HFI_IRQ_GMU_ERR_MASK 0xFF0000 |
| 45 | #define HFI_IRQ_OOB_MASK 0xFF000000 |
| 46 | #define HFI_IRQ_MASK (HFI_IRQ_MSGQ_MASK |\ |
| 47 | HFI_IRQ_DBGQ_MASK |\ |
| 48 | HFI_IRQ_BLOCKED_MSG_MASK |\ |
| 49 | HFI_IRQ_GMU_ERR_MASK |\ |
| 50 | HFI_IRQ_OOB_MASK) |
| 51 | /** |
| 52 | * struct hfi_queue_table_header - HFI queue table structure |
| 53 | * @version: HFI protocol version |
| 54 | * @size: queue table size in dwords |
| 55 | * @qhdr0_offset: first queue header offset (dwords) in this table |
| 56 | * @qhdr_size: queue header size |
| 57 | * @num_q: number of queues defined in this table |
| 58 | * @num_active_q: number of active queues |
| 59 | */ |
| 60 | struct hfi_queue_table_header { |
| 61 | uint32_t version; |
| 62 | uint32_t size; |
| 63 | uint32_t qhdr0_offset; |
| 64 | uint32_t qhdr_size; |
| 65 | uint32_t num_q; |
| 66 | uint32_t num_active_q; |
| 67 | }; |
| 68 | |
| 69 | /** |
| 70 | * struct hfi_queue_header - HFI queue header structure |
| 71 | * @status: active: 1; inactive: 0 |
| 72 | * @start_addr: starting address of the queue in GMU VA space |
| 73 | * @type: queue type encoded the priority, ID and send/recevie types |
| 74 | * @queue_size: size of the queue |
| 75 | * @msg_size: size of the message if each message has fixed size. |
| 76 | * Otherwise, 0 means variable size of message in the queue. |
| 77 | * @drop_cnt: count of dropped messages |
| 78 | * @rx_wm: receiver watermark |
| 79 | * @tx_wm: sender watermark |
| 80 | * @rx_req: receiver request |
| 81 | * @tx_req: sender request |
| 82 | * @read_index: read index of the queue |
| 83 | * @write_index: write index of the queue |
| 84 | */ |
| 85 | struct hfi_queue_header { |
| 86 | uint32_t status; |
| 87 | uint32_t start_addr; |
| 88 | uint32_t type; |
| 89 | uint32_t queue_size; |
| 90 | uint32_t msg_size; |
| 91 | uint32_t drop_cnt; |
| 92 | uint32_t rx_wm; |
| 93 | uint32_t tx_wm; |
| 94 | uint32_t rx_req; |
| 95 | uint32_t tx_req; |
| 96 | uint32_t read_index; |
| 97 | uint32_t write_index; |
| 98 | }; |
| 99 | |
| 100 | struct hfi_queue_table { |
| 101 | struct hfi_queue_table_header qtbl_hdr; |
| 102 | struct hfi_queue_header qhdr[HFI_QUEUE_MAX]; |
| 103 | }; |
| 104 | |
| 105 | /* HTOF queue priority, 1 is highest priority */ |
| 106 | enum hfi_h2f_qpri { |
| 107 | HFI_H2F_QPRI_CMD = 10, |
| 108 | HFI_H2F_QPRI_DISPATCH_P0 = 20, |
| 109 | HFI_H2F_QPRI_DISPATCH_P1 = 21, |
| 110 | HFI_H2F_QPRI_DISPATCH_P2 = 22, |
| 111 | }; |
| 112 | |
| 113 | /* FTOH queue priority, 1 is highest priority */ |
| 114 | enum hfi_f2h_qpri { |
| 115 | HFI_F2H_QPRI_MSG = 10, |
| 116 | HFI_F2H_QPRI_DEBUG = 40, |
| 117 | }; |
| 118 | |
| 119 | #define HFI_RSP_TIMEOUT 50 /* msec */ |
| 120 | #define HFI_H2F_CMD_IRQ_MASK BIT(0) |
| 121 | |
| 122 | enum hfi_msg_type { |
| 123 | HFI_MSG_CMD = 0, |
| 124 | HFI_MSG_POST = 1, |
| 125 | HFI_MSG_ACK = 2, |
| 126 | HFI_MSG_INVALID = 3 |
| 127 | }; |
| 128 | |
| 129 | enum hfi_msg_id { |
| 130 | H2F_MSG_INIT = 0, |
| 131 | H2F_MSG_FW_VER = 1, |
| 132 | H2F_MSG_LM_CFG = 2, |
| 133 | H2F_MSG_BW_VOTE_TBL = 3, |
| 134 | H2F_MSG_PERF_TBL = 4, |
| 135 | H2F_MSG_TEST = 5, |
| 136 | H2F_MSG_DCVS_VOTE = 30, |
| 137 | H2F_MSG_FW_HALT = 31, |
| 138 | H2F_MSG_PREPARE_SLUMBER = 33, |
| 139 | F2H_MSG_ERR = 100, |
| 140 | F2H_MSG_GMU_CNTR_REGISTER = 101, |
| 141 | F2H_MSG_ACK = 126, |
| 142 | H2F_MSG_ACK = 127, |
| 143 | H2F_MSG_REGISTER_CONTEXT = 128, |
| 144 | H2F_MSG_UNREGISTER_CONTEXT = 129, |
| 145 | H2F_MSG_ISSUE_IB = 130, |
| 146 | H2F_MSG_REGISTER_QUEUE = 131, |
| 147 | H2F_MSG_UNREGISTER_QUEUE = 132, |
| 148 | H2F_MSG_CLOSE = 133, |
| 149 | H2F_REGISTER_CONTEXT_DONE = 134, |
| 150 | H2F_UNREG_CONTEXT_DONE = 135, |
| 151 | H2F_ISSUE_IB_DONE = 136, |
| 152 | H2F_REGISTER_QUEUE_DONE = 137, |
| 153 | }; |
| 154 | |
| 155 | #define MAX_GX_LEVELS 16 |
| 156 | #define MAX_CX_LEVELS 4 |
| 157 | #define MAX_CNOC_LEVELS 2 |
| 158 | #define MAX_CNOC_CMDS 6 |
| 159 | #define MAX_BW_CMDS 8 |
| 160 | #define INVALID_DCVS_IDX 0xFF |
| 161 | |
| 162 | #if MAX_CNOC_LEVELS > MAX_GX_LEVELS |
| 163 | #error "CNOC levels cannot exceed GX levels" |
| 164 | #endif |
| 165 | |
| 166 | /** |
| 167 | * For detail usage of structures defined below, |
| 168 | * please look up HFI spec. |
| 169 | */ |
| 170 | |
| 171 | struct hfi_msg_hdr { |
| 172 | uint32_t id: 8; /* 0~127 power, 128~255 ecp */ |
| 173 | uint32_t size: 8; /* unit in dword */ |
| 174 | uint32_t type: 4; |
| 175 | uint32_t seqnum: 12; |
| 176 | }; |
| 177 | |
| 178 | struct hfi_msg_rsp { |
| 179 | struct hfi_msg_hdr hdr; |
| 180 | struct hfi_msg_hdr ret_hdr; |
| 181 | uint32_t error; |
| 182 | uint32_t payload[MAX_RSP_PAYLOAD_SIZE]; |
| 183 | }; |
| 184 | |
| 185 | struct hfi_gmu_init_cmd { |
| 186 | struct hfi_msg_hdr hdr; |
| 187 | uint32_t seg_id; |
| 188 | uint32_t dbg_buffer_addr; |
| 189 | uint32_t dbg_buffer_size; |
| 190 | uint32_t boot_state; |
| 191 | }; |
| 192 | |
| 193 | struct hfi_fw_version_cmd { |
| 194 | struct hfi_msg_hdr hdr; |
| 195 | uint32_t supported_ver; |
| 196 | }; |
| 197 | |
| 198 | struct limits_config { |
| 199 | uint32_t lm_type: 4; |
| 200 | uint32_t lm_sensor_type: 4; |
| 201 | uint32_t throttle_config: 4; |
| 202 | uint32_t idle_throttle_en: 4; |
| 203 | uint32_t acd_en: 4; |
| 204 | uint32_t reserved: 12; |
| 205 | }; |
| 206 | |
| 207 | struct bcl_config { |
| 208 | uint32_t bcl: 8; |
| 209 | uint32_t reserved: 24; |
| 210 | }; |
| 211 | |
| 212 | struct hfi_lmconfig_cmd { |
| 213 | struct hfi_msg_hdr hdr; |
| 214 | struct limits_config limit_conf; |
| 215 | struct bcl_config bcl_conf; |
| 216 | uint32_t lm_enable_bitmask; |
| 217 | }; |
| 218 | |
| 219 | struct hfi_bwtable_cmd { |
| 220 | struct hfi_msg_hdr hdr; |
| 221 | uint32_t bw_level_num; |
| 222 | uint32_t cnoc_cmds_num; |
| 223 | uint32_t ddr_cmds_num; |
| 224 | uint32_t cnoc_wait_bitmask; |
| 225 | uint32_t ddr_wait_bitmask; |
| 226 | uint32_t cnoc_cmd_addrs[MAX_CNOC_CMDS]; |
| 227 | uint32_t cnoc_cmd_data[MAX_CNOC_LEVELS][MAX_CNOC_CMDS]; |
| 228 | uint32_t ddr_cmd_addrs[MAX_BW_CMDS]; |
| 229 | uint32_t ddr_cmd_data[MAX_GX_LEVELS][MAX_BW_CMDS]; |
| 230 | }; |
| 231 | |
| 232 | struct arc_vote_desc { |
| 233 | /* In case of GPU freq vote, primary is GX, secondary is MX |
| 234 | * in case of GMU freq vote, primary is CX, secondary is MX |
| 235 | */ |
| 236 | uint32_t pri_idx: 8; |
| 237 | uint32_t sec_idx : 8; |
| 238 | uint32_t vlvl: 16; |
| 239 | }; |
| 240 | |
| 241 | struct opp_desc { |
| 242 | struct arc_vote_desc vote; |
| 243 | uint32_t freq; |
| 244 | }; |
| 245 | |
| 246 | struct hfi_dcvstable_cmd { |
| 247 | struct hfi_msg_hdr hdr; |
| 248 | uint32_t gpu_level_num; |
| 249 | uint32_t gmu_level_num; |
| 250 | struct opp_desc gx_votes[MAX_GX_LEVELS]; |
| 251 | struct opp_desc cx_votes[MAX_CX_LEVELS]; |
| 252 | }; |
| 253 | |
| 254 | enum fw_clkset_options { |
| 255 | OPTION_DEFAULT = 0, |
| 256 | OPTION_CLOSEST = 1, |
| 257 | OPTION_AT_MOST = 2, |
| 258 | OPTION_AT_LEAST = 3, |
| 259 | OPTION_INVALID = 4 |
| 260 | }; |
| 261 | |
| 262 | enum rpm_ack_type { |
| 263 | ACK_NONBLOCK = 0, |
| 264 | ACK_BLOCK = 1, |
| 265 | ACK_INVALID = 2, |
| 266 | }; |
| 267 | |
| 268 | struct gpu_dcvs_vote { |
| 269 | uint32_t perf_idx : 8; |
| 270 | uint32_t reserved : 20; |
| 271 | uint32_t clkset_opt : 4; |
| 272 | }; |
| 273 | |
| 274 | struct gpu_bw_vote { |
| 275 | uint32_t bw_idx : 8; |
| 276 | /* to support split AB and IB vote */ |
| 277 | uint32_t reserved : 24; |
| 278 | }; |
| 279 | |
| 280 | union gpu_perf_vote { |
| 281 | struct gpu_dcvs_vote fvote; |
| 282 | struct gpu_bw_vote bvote; |
| 283 | uint32_t raw; |
| 284 | }; |
| 285 | |
| 286 | struct hfi_dcvs_cmd { |
| 287 | struct hfi_msg_hdr hdr; |
| 288 | uint32_t ack_type; |
| 289 | struct gpu_dcvs_vote freq; |
| 290 | struct gpu_bw_vote bw; |
| 291 | }; |
| 292 | |
| 293 | struct hfi_prep_slumber_cmd { |
| 294 | struct hfi_msg_hdr hdr; |
| 295 | uint32_t init_bw_idx; |
| 296 | uint32_t init_perf_idx; |
| 297 | }; |
| 298 | |
| 299 | struct hfi_fw_err_msg { |
| 300 | struct hfi_msg_hdr hdr; |
| 301 | uint32_t error_code; |
| 302 | uint32_t data_1; |
| 303 | uint32_t data_2; |
| 304 | }; |
| 305 | |
| 306 | /** |
| 307 | * struct pending_msg - data structure to track outstanding HFI |
| 308 | * command messages |
| 309 | * @msg_complete: a blocking mechanism for sender to wait for ACK |
| 310 | * @node: a node in pending message queue |
| 311 | * @msg_id: the ID of the command message pending for ACK |
| 312 | * @seqnum: the seqnum of the command message pending for ACK. |
| 313 | * together with msg_id, are used to correlate a receiving ACK |
| 314 | * to a pending cmd message |
| 315 | * @results: the payload of received return message (ACK) |
| 316 | */ |
| 317 | struct pending_msg { |
| 318 | struct completion msg_complete; |
| 319 | struct list_head node; |
| 320 | uint32_t msg_id; |
| 321 | uint32_t seqnum; |
| 322 | struct hfi_msg_rsp results; |
| 323 | }; |
| 324 | |
| 325 | /** |
| 326 | * struct kgsl_hfi - HFI control structure |
| 327 | * @hfi_interrupt_num: number of GMU asserted HFI interrupt |
| 328 | * @msglock: spinlock to protect access to outstanding command message list |
| 329 | * @cmdq_mutex: mutex to protect command queue access from multiple senders |
| 330 | * @msglist: outstanding command message list. Each message in the list |
| 331 | * is waiting for ACK from GMU |
| 332 | * @tasklet: the thread handling received messages from GMU |
| 333 | * @fw_version: FW version number provided by GMU |
| 334 | * @seqnum: atomic counter that is incremented for each message sent. The |
| 335 | * value of the counter is used as sequence number for HFI message |
| 336 | */ |
| 337 | struct kgsl_hfi { |
| 338 | int hfi_interrupt_num; |
| 339 | spinlock_t msglock; |
| 340 | struct mutex cmdq_mutex; |
| 341 | struct list_head msglist; |
| 342 | struct tasklet_struct tasklet; |
| 343 | uint32_t fw_version; |
| 344 | atomic_t seqnum; |
| 345 | bool gmu_init_done; |
| 346 | }; |
| 347 | |
| 348 | struct gmu_device; |
| 349 | struct gmu_memdesc; |
| 350 | |
| 351 | int hfi_start(struct gmu_device *gmu, uint32_t boot_state); |
| 352 | void hfi_stop(struct gmu_device *gmu); |
| 353 | void hfi_receiver(unsigned long data); |
| 354 | void hfi_init(struct kgsl_hfi *hfi, struct gmu_memdesc *mem_addr, |
| 355 | uint32_t queue_sz_bytes); |
| 356 | int hfi_send_dcvs_vote(struct gmu_device *gmu, uint32_t perf_idx, |
| 357 | uint32_t bw_idx, enum rpm_ack_type ack_type); |
| 358 | int hfi_notify_slumber(struct gmu_device *gmu, uint32_t init_perf_idx, |
| 359 | uint32_t init_bw_idx); |
| 360 | #endif /* __KGSL_HFI_H */ |