Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 1 | /* |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 2 | * Synopsys Designware PCIe host controller driver |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. |
| 5 | * http://www.samsung.com |
| 6 | * |
| 7 | * Author: Jingoo Han <jg1.han@samsung.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | */ |
| 13 | |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 14 | #include <linux/irq.h> |
| 15 | #include <linux/irqdomain.h> |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 16 | #include <linux/kernel.h> |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 17 | #include <linux/module.h> |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 18 | #include <linux/msi.h> |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 19 | #include <linux/of_address.h> |
Lucas Stach | 804f57b | 2014-03-05 14:25:51 +0100 | [diff] [blame] | 20 | #include <linux/of_pci.h> |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 21 | #include <linux/pci.h> |
| 22 | #include <linux/pci_regs.h> |
Kishon Vijay Abraham I | 4dd964d | 2014-07-17 14:30:40 +0530 | [diff] [blame] | 23 | #include <linux/platform_device.h> |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 24 | #include <linux/types.h> |
| 25 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 26 | #include "pcie-designware.h" |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 27 | |
| 28 | /* Synopsis specific PCIE configuration registers */ |
| 29 | #define PCIE_PORT_LINK_CONTROL 0x710 |
| 30 | #define PORT_LINK_MODE_MASK (0x3f << 16) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 31 | #define PORT_LINK_MODE_1_LANES (0x1 << 16) |
| 32 | #define PORT_LINK_MODE_2_LANES (0x3 << 16) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 33 | #define PORT_LINK_MODE_4_LANES (0x7 << 16) |
| 34 | |
| 35 | #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C |
| 36 | #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) |
| 37 | #define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 38 | #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) |
| 39 | #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) |
| 40 | #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 41 | |
| 42 | #define PCIE_MSI_ADDR_LO 0x820 |
| 43 | #define PCIE_MSI_ADDR_HI 0x824 |
| 44 | #define PCIE_MSI_INTR0_ENABLE 0x828 |
| 45 | #define PCIE_MSI_INTR0_MASK 0x82C |
| 46 | #define PCIE_MSI_INTR0_STATUS 0x830 |
| 47 | |
| 48 | #define PCIE_ATU_VIEWPORT 0x900 |
| 49 | #define PCIE_ATU_REGION_INBOUND (0x1 << 31) |
| 50 | #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) |
| 51 | #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) |
| 52 | #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) |
| 53 | #define PCIE_ATU_CR1 0x904 |
| 54 | #define PCIE_ATU_TYPE_MEM (0x0 << 0) |
| 55 | #define PCIE_ATU_TYPE_IO (0x2 << 0) |
| 56 | #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) |
| 57 | #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) |
| 58 | #define PCIE_ATU_CR2 0x908 |
| 59 | #define PCIE_ATU_ENABLE (0x1 << 31) |
| 60 | #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) |
| 61 | #define PCIE_ATU_LOWER_BASE 0x90C |
| 62 | #define PCIE_ATU_UPPER_BASE 0x910 |
| 63 | #define PCIE_ATU_LIMIT 0x914 |
| 64 | #define PCIE_ATU_LOWER_TARGET 0x918 |
| 65 | #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) |
| 66 | #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) |
| 67 | #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) |
| 68 | #define PCIE_ATU_UPPER_TARGET 0x91C |
| 69 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 70 | static struct hw_pci dw_pci; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 71 | |
Bjorn Helgaas | 73e4085 | 2013-10-09 09:12:37 -0600 | [diff] [blame] | 72 | static unsigned long global_io_offset; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 73 | |
| 74 | static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys) |
| 75 | { |
| 76 | return sys->private_data; |
| 77 | } |
| 78 | |
Pratyush Anand | a01ef59 | 2013-12-11 15:08:32 +0530 | [diff] [blame] | 79 | int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 80 | { |
| 81 | *val = readl(addr); |
| 82 | |
| 83 | if (size == 1) |
| 84 | *val = (*val >> (8 * (where & 3))) & 0xff; |
| 85 | else if (size == 2) |
| 86 | *val = (*val >> (8 * (where & 3))) & 0xffff; |
| 87 | else if (size != 4) |
| 88 | return PCIBIOS_BAD_REGISTER_NUMBER; |
| 89 | |
| 90 | return PCIBIOS_SUCCESSFUL; |
| 91 | } |
| 92 | |
Pratyush Anand | a01ef59 | 2013-12-11 15:08:32 +0530 | [diff] [blame] | 93 | int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 94 | { |
| 95 | if (size == 4) |
| 96 | writel(val, addr); |
| 97 | else if (size == 2) |
| 98 | writew(val, addr + (where & 2)); |
| 99 | else if (size == 1) |
| 100 | writeb(val, addr + (where & 3)); |
| 101 | else |
| 102 | return PCIBIOS_BAD_REGISTER_NUMBER; |
| 103 | |
| 104 | return PCIBIOS_SUCCESSFUL; |
| 105 | } |
| 106 | |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 107 | static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 108 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 109 | if (pp->ops->readl_rc) |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 110 | pp->ops->readl_rc(pp, pp->dbi_base + reg, val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 111 | else |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 112 | *val = readl(pp->dbi_base + reg); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 113 | } |
| 114 | |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 115 | static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 116 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 117 | if (pp->ops->writel_rc) |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 118 | pp->ops->writel_rc(pp, val, pp->dbi_base + reg); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 119 | else |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 120 | writel(val, pp->dbi_base + reg); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 121 | } |
| 122 | |
Bjorn Helgaas | 73e4085 | 2013-10-09 09:12:37 -0600 | [diff] [blame] | 123 | static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, |
| 124 | u32 *val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 125 | { |
| 126 | int ret; |
| 127 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 128 | if (pp->ops->rd_own_conf) |
| 129 | ret = pp->ops->rd_own_conf(pp, where, size, val); |
| 130 | else |
Pratyush Anand | a01ef59 | 2013-12-11 15:08:32 +0530 | [diff] [blame] | 131 | ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, |
| 132 | size, val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 133 | |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 134 | return ret; |
| 135 | } |
| 136 | |
Bjorn Helgaas | 73e4085 | 2013-10-09 09:12:37 -0600 | [diff] [blame] | 137 | static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, |
| 138 | u32 val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 139 | { |
| 140 | int ret; |
| 141 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 142 | if (pp->ops->wr_own_conf) |
| 143 | ret = pp->ops->wr_own_conf(pp, where, size, val); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 144 | else |
Pratyush Anand | a01ef59 | 2013-12-11 15:08:32 +0530 | [diff] [blame] | 145 | ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where, |
| 146 | size, val); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 147 | |
| 148 | return ret; |
| 149 | } |
| 150 | |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 151 | static struct irq_chip dw_msi_irq_chip = { |
| 152 | .name = "PCI-MSI", |
| 153 | .irq_enable = unmask_msi_irq, |
| 154 | .irq_disable = mask_msi_irq, |
| 155 | .irq_mask = mask_msi_irq, |
| 156 | .irq_unmask = unmask_msi_irq, |
| 157 | }; |
| 158 | |
| 159 | /* MSI int handler */ |
Lucas Stach | 7f4f16e | 2014-03-28 17:52:58 +0100 | [diff] [blame] | 160 | irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 161 | { |
| 162 | unsigned long val; |
Pratyush Anand | 904d0e7 | 2013-10-09 21:32:12 +0900 | [diff] [blame] | 163 | int i, pos, irq; |
Lucas Stach | 7f4f16e | 2014-03-28 17:52:58 +0100 | [diff] [blame] | 164 | irqreturn_t ret = IRQ_NONE; |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 165 | |
| 166 | for (i = 0; i < MAX_MSI_CTRLS; i++) { |
| 167 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, |
| 168 | (u32 *)&val); |
| 169 | if (val) { |
Lucas Stach | 7f4f16e | 2014-03-28 17:52:58 +0100 | [diff] [blame] | 170 | ret = IRQ_HANDLED; |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 171 | pos = 0; |
| 172 | while ((pos = find_next_bit(&val, 32, pos)) != 32) { |
Pratyush Anand | 904d0e7 | 2013-10-09 21:32:12 +0900 | [diff] [blame] | 173 | irq = irq_find_mapping(pp->irq_domain, |
| 174 | i * 32 + pos); |
Harro Haan | ca16589 | 2013-12-12 19:29:03 +0100 | [diff] [blame] | 175 | dw_pcie_wr_own_conf(pp, |
| 176 | PCIE_MSI_INTR0_STATUS + i * 12, |
| 177 | 4, 1 << pos); |
Pratyush Anand | 904d0e7 | 2013-10-09 21:32:12 +0900 | [diff] [blame] | 178 | generic_handle_irq(irq); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 179 | pos++; |
| 180 | } |
| 181 | } |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 182 | } |
Lucas Stach | 7f4f16e | 2014-03-28 17:52:58 +0100 | [diff] [blame] | 183 | |
| 184 | return ret; |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 185 | } |
| 186 | |
| 187 | void dw_pcie_msi_init(struct pcie_port *pp) |
| 188 | { |
| 189 | pp->msi_data = __get_free_pages(GFP_KERNEL, 0); |
| 190 | |
| 191 | /* program the msi_data */ |
| 192 | dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, |
| 193 | virt_to_phys((void *)pp->msi_data)); |
| 194 | dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); |
| 195 | } |
| 196 | |
| 197 | static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0) |
| 198 | { |
| 199 | int flag = 1; |
| 200 | |
| 201 | do { |
| 202 | pos = find_next_zero_bit(pp->msi_irq_in_use, |
| 203 | MAX_MSI_IRQS, pos); |
| 204 | /*if you have reached to the end then get out from here.*/ |
| 205 | if (pos == MAX_MSI_IRQS) |
| 206 | return -ENOSPC; |
| 207 | /* |
| 208 | * Check if this position is at correct offset.nvec is always a |
Bjorn Helgaas | f762598 | 2013-11-14 11:28:18 -0700 | [diff] [blame] | 209 | * power of two. pos0 must be nvec bit aligned. |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 210 | */ |
| 211 | if (pos % msgvec) |
| 212 | pos += msgvec - (pos % msgvec); |
| 213 | else |
| 214 | flag = 0; |
| 215 | } while (flag); |
| 216 | |
| 217 | *pos0 = pos; |
| 218 | return 0; |
| 219 | } |
| 220 | |
Murali Karicheri | 2f37c5a | 2014-07-21 12:58:42 -0400 | [diff] [blame] | 221 | static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq) |
| 222 | { |
| 223 | unsigned int res, bit, val; |
| 224 | |
| 225 | res = (irq / 32) * 12; |
| 226 | bit = irq % 32; |
| 227 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); |
| 228 | val &= ~(1 << bit); |
| 229 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); |
| 230 | } |
| 231 | |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 232 | static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base, |
Jingoo Han | 58275f2f | 2013-12-27 09:30:25 +0900 | [diff] [blame] | 233 | unsigned int nvec, unsigned int pos) |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 234 | { |
Murali Karicheri | 2f37c5a | 2014-07-21 12:58:42 -0400 | [diff] [blame] | 235 | unsigned int i; |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 236 | |
Bjorn Helgaas | 0b8cfb6 | 2013-12-09 15:11:25 -0700 | [diff] [blame] | 237 | for (i = 0; i < nvec; i++) { |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 238 | irq_set_msi_desc_off(irq_base, i, NULL); |
| 239 | clear_bit(pos + i, pp->msi_irq_in_use); |
Jingoo Han | 58275f2f | 2013-12-27 09:30:25 +0900 | [diff] [blame] | 240 | /* Disable corresponding interrupt on MSI controller */ |
Murali Karicheri | 2f37c5a | 2014-07-21 12:58:42 -0400 | [diff] [blame] | 241 | if (pp->ops->msi_clear_irq) |
| 242 | pp->ops->msi_clear_irq(pp, pos + i); |
| 243 | else |
| 244 | dw_pcie_msi_clear_irq(pp, pos + i); |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 245 | } |
| 246 | } |
| 247 | |
Murali Karicheri | 2f37c5a | 2014-07-21 12:58:42 -0400 | [diff] [blame] | 248 | static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) |
| 249 | { |
| 250 | unsigned int res, bit, val; |
| 251 | |
| 252 | res = (irq / 32) * 12; |
| 253 | bit = irq % 32; |
| 254 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); |
| 255 | val |= 1 << bit; |
| 256 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); |
| 257 | } |
| 258 | |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 259 | static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos) |
| 260 | { |
Murali Karicheri | 2f37c5a | 2014-07-21 12:58:42 -0400 | [diff] [blame] | 261 | int irq, pos0, pos1, i; |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 262 | struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata); |
| 263 | |
| 264 | if (!pp) { |
| 265 | BUG(); |
| 266 | return -EINVAL; |
| 267 | } |
| 268 | |
| 269 | pos0 = find_first_zero_bit(pp->msi_irq_in_use, |
| 270 | MAX_MSI_IRQS); |
| 271 | if (pos0 % no_irqs) { |
| 272 | if (find_valid_pos0(pp, no_irqs, pos0, &pos0)) |
| 273 | goto no_valid_irq; |
| 274 | } |
| 275 | if (no_irqs > 1) { |
| 276 | pos1 = find_next_bit(pp->msi_irq_in_use, |
| 277 | MAX_MSI_IRQS, pos0); |
| 278 | /* there must be nvec number of consecutive free bits */ |
| 279 | while ((pos1 - pos0) < no_irqs) { |
| 280 | if (find_valid_pos0(pp, no_irqs, pos1, &pos0)) |
| 281 | goto no_valid_irq; |
| 282 | pos1 = find_next_bit(pp->msi_irq_in_use, |
| 283 | MAX_MSI_IRQS, pos0); |
| 284 | } |
| 285 | } |
| 286 | |
Pratyush Anand | 904d0e7 | 2013-10-09 21:32:12 +0900 | [diff] [blame] | 287 | irq = irq_find_mapping(pp->irq_domain, pos0); |
| 288 | if (!irq) |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 289 | goto no_valid_irq; |
| 290 | |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 291 | /* |
| 292 | * irq_create_mapping (called from dw_pcie_host_init) pre-allocates |
| 293 | * descs so there is no need to allocate descs here. We can therefore |
| 294 | * assume that if irq_find_mapping above returns non-zero, then the |
| 295 | * descs are also successfully allocated. |
| 296 | */ |
| 297 | |
Bjorn Helgaas | 0b8cfb6 | 2013-12-09 15:11:25 -0700 | [diff] [blame] | 298 | for (i = 0; i < no_irqs; i++) { |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 299 | if (irq_set_msi_desc_off(irq, i, desc) != 0) { |
| 300 | clear_irq_range(pp, irq, i, pos0); |
| 301 | goto no_valid_irq; |
| 302 | } |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 303 | set_bit(pos0 + i, pp->msi_irq_in_use); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 304 | /*Enable corresponding interrupt in MSI interrupt controller */ |
Murali Karicheri | 2f37c5a | 2014-07-21 12:58:42 -0400 | [diff] [blame] | 305 | if (pp->ops->msi_set_irq) |
| 306 | pp->ops->msi_set_irq(pp, pos0 + i); |
| 307 | else |
| 308 | dw_pcie_msi_set_irq(pp, pos0 + i); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 309 | } |
| 310 | |
| 311 | *pos = pos0; |
| 312 | return irq; |
| 313 | |
| 314 | no_valid_irq: |
| 315 | *pos = pos0; |
| 316 | return -ENOSPC; |
| 317 | } |
| 318 | |
| 319 | static void clear_irq(unsigned int irq) |
| 320 | { |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 321 | unsigned int pos, nvec; |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 322 | struct msi_desc *msi; |
| 323 | struct pcie_port *pp; |
Pratyush Anand | 904d0e7 | 2013-10-09 21:32:12 +0900 | [diff] [blame] | 324 | struct irq_data *data = irq_get_irq_data(irq); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 325 | |
| 326 | /* get the port structure */ |
Thomas Gleixner | f7bfca6 | 2014-02-23 21:40:11 +0000 | [diff] [blame] | 327 | msi = irq_data_get_msi(data); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 328 | pp = sys_to_pcie(msi->dev->bus->sysdata); |
| 329 | if (!pp) { |
| 330 | BUG(); |
| 331 | return; |
| 332 | } |
| 333 | |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 334 | /* undo what was done in assign_irq */ |
Pratyush Anand | 904d0e7 | 2013-10-09 21:32:12 +0900 | [diff] [blame] | 335 | pos = data->hwirq; |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 336 | nvec = 1 << msi->msi_attrib.multiple; |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 337 | |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 338 | clear_irq_range(pp, irq, nvec, pos); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 339 | |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 340 | /* all irqs cleared; reset attributes */ |
| 341 | msi->irq = 0; |
| 342 | msi->msi_attrib.multiple = 0; |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 343 | } |
| 344 | |
| 345 | static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev, |
| 346 | struct msi_desc *desc) |
| 347 | { |
| 348 | int irq, pos, msgvec; |
| 349 | u16 msg_ctr; |
| 350 | struct msi_msg msg; |
| 351 | struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata); |
| 352 | |
| 353 | if (!pp) { |
| 354 | BUG(); |
| 355 | return -EINVAL; |
| 356 | } |
| 357 | |
| 358 | pci_read_config_word(pdev, desc->msi_attrib.pos+PCI_MSI_FLAGS, |
| 359 | &msg_ctr); |
| 360 | msgvec = (msg_ctr&PCI_MSI_FLAGS_QSIZE) >> 4; |
| 361 | if (msgvec == 0) |
| 362 | msgvec = (msg_ctr & PCI_MSI_FLAGS_QMASK) >> 1; |
| 363 | if (msgvec > 5) |
| 364 | msgvec = 0; |
| 365 | |
| 366 | irq = assign_irq((1 << msgvec), desc, &pos); |
| 367 | if (irq < 0) |
| 368 | return irq; |
| 369 | |
Bjørn Erik Nilsen | 64989e7 | 2013-11-29 14:35:25 +0100 | [diff] [blame] | 370 | /* |
| 371 | * write_msi_msg() will update PCI_MSI_FLAGS so there is |
| 372 | * no need to explicitly call pci_write_config_word(). |
| 373 | */ |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 374 | desc->msi_attrib.multiple = msgvec; |
| 375 | |
Murali Karicheri | 2f37c5a | 2014-07-21 12:58:42 -0400 | [diff] [blame] | 376 | if (pp->ops->get_msi_data) |
| 377 | msg.address_lo = pp->ops->get_msi_data(pp); |
| 378 | else |
| 379 | msg.address_lo = virt_to_phys((void *)pp->msi_data); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 380 | msg.address_hi = 0x0; |
| 381 | msg.data = pos; |
| 382 | write_msi_msg(irq, &msg); |
| 383 | |
| 384 | return 0; |
| 385 | } |
| 386 | |
| 387 | static void dw_msi_teardown_irq(struct msi_chip *chip, unsigned int irq) |
| 388 | { |
| 389 | clear_irq(irq); |
| 390 | } |
| 391 | |
| 392 | static struct msi_chip dw_pcie_msi_chip = { |
| 393 | .setup_irq = dw_msi_setup_irq, |
| 394 | .teardown_irq = dw_msi_teardown_irq, |
| 395 | }; |
| 396 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 397 | int dw_pcie_link_up(struct pcie_port *pp) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 398 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 399 | if (pp->ops->link_up) |
| 400 | return pp->ops->link_up(pp); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 401 | else |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 402 | return 0; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 403 | } |
| 404 | |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 405 | static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq, |
| 406 | irq_hw_number_t hwirq) |
| 407 | { |
| 408 | irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq); |
| 409 | irq_set_chip_data(irq, domain->host_data); |
| 410 | set_irq_flags(irq, IRQF_VALID); |
| 411 | |
| 412 | return 0; |
| 413 | } |
| 414 | |
| 415 | static const struct irq_domain_ops msi_domain_ops = { |
| 416 | .map = dw_pcie_msi_map, |
| 417 | }; |
| 418 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 419 | int __init dw_pcie_host_init(struct pcie_port *pp) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 420 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 421 | struct device_node *np = pp->dev->of_node; |
Kishon Vijay Abraham I | 4dd964d | 2014-07-17 14:30:40 +0530 | [diff] [blame] | 422 | struct platform_device *pdev = to_platform_device(pp->dev); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 423 | struct of_pci_range range; |
| 424 | struct of_pci_range_parser parser; |
Kishon Vijay Abraham I | 4dd964d | 2014-07-17 14:30:40 +0530 | [diff] [blame] | 425 | struct resource *cfg_res; |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 426 | u32 val, na, ns; |
| 427 | const __be32 *addrp; |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame^] | 428 | int i, index, ret; |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 429 | |
| 430 | /* Find the address cell size and the number of cells in order to get |
| 431 | * the untranslated address. |
| 432 | */ |
| 433 | of_property_read_u32(np, "#address-cells", &na); |
| 434 | ns = of_n_size_cells(np); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 435 | |
Kishon Vijay Abraham I | 4dd964d | 2014-07-17 14:30:40 +0530 | [diff] [blame] | 436 | cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); |
| 437 | if (cfg_res) { |
| 438 | pp->config.cfg0_size = resource_size(cfg_res)/2; |
| 439 | pp->config.cfg1_size = resource_size(cfg_res)/2; |
| 440 | pp->cfg0_base = cfg_res->start; |
| 441 | pp->cfg1_base = cfg_res->start + pp->config.cfg0_size; |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 442 | |
| 443 | /* Find the untranslated configuration space address */ |
| 444 | index = of_property_match_string(np, "reg-names", "config"); |
| 445 | addrp = of_get_address(np, index, false, false); |
| 446 | pp->cfg0_mod_base = of_read_number(addrp, ns); |
| 447 | pp->cfg1_mod_base = pp->cfg0_mod_base + pp->config.cfg0_size; |
Kishon Vijay Abraham I | 4dd964d | 2014-07-17 14:30:40 +0530 | [diff] [blame] | 448 | } else { |
| 449 | dev_err(pp->dev, "missing *config* reg space\n"); |
| 450 | } |
| 451 | |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 452 | if (of_pci_range_parser_init(&parser, np)) { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 453 | dev_err(pp->dev, "missing ranges property\n"); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 454 | return -EINVAL; |
| 455 | } |
| 456 | |
| 457 | /* Get the I/O and memory ranges from DT */ |
| 458 | for_each_of_pci_range(&parser, &range) { |
| 459 | unsigned long restype = range.flags & IORESOURCE_TYPE_BITS; |
| 460 | if (restype == IORESOURCE_IO) { |
| 461 | of_pci_range_to_resource(&range, np, &pp->io); |
| 462 | pp->io.name = "I/O"; |
| 463 | pp->io.start = max_t(resource_size_t, |
| 464 | PCIBIOS_MIN_IO, |
| 465 | range.pci_addr + global_io_offset); |
| 466 | pp->io.end = min_t(resource_size_t, |
| 467 | IO_SPACE_LIMIT, |
| 468 | range.pci_addr + range.size |
| 469 | + global_io_offset); |
| 470 | pp->config.io_size = resource_size(&pp->io); |
| 471 | pp->config.io_bus_addr = range.pci_addr; |
Pratyush Anand | fce8591 | 2013-12-11 15:08:33 +0530 | [diff] [blame] | 472 | pp->io_base = range.cpu_addr; |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 473 | |
| 474 | /* Find the untranslated IO space address */ |
| 475 | pp->io_mod_base = of_read_number(parser.range - |
| 476 | parser.np + na, ns); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 477 | } |
| 478 | if (restype == IORESOURCE_MEM) { |
| 479 | of_pci_range_to_resource(&range, np, &pp->mem); |
| 480 | pp->mem.name = "MEM"; |
| 481 | pp->config.mem_size = resource_size(&pp->mem); |
| 482 | pp->config.mem_bus_addr = range.pci_addr; |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 483 | |
| 484 | /* Find the untranslated MEM space address */ |
| 485 | pp->mem_mod_base = of_read_number(parser.range - |
| 486 | parser.np + na, ns); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 487 | } |
| 488 | if (restype == 0) { |
| 489 | of_pci_range_to_resource(&range, np, &pp->cfg); |
| 490 | pp->config.cfg0_size = resource_size(&pp->cfg)/2; |
| 491 | pp->config.cfg1_size = resource_size(&pp->cfg)/2; |
Kishon Vijay Abraham I | 4dd964d | 2014-07-17 14:30:40 +0530 | [diff] [blame] | 492 | pp->cfg0_base = pp->cfg.start; |
| 493 | pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size; |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 494 | |
| 495 | /* Find the untranslated configuration space address */ |
| 496 | pp->cfg0_mod_base = of_read_number(parser.range - |
| 497 | parser.np + na, ns); |
| 498 | pp->cfg1_mod_base = pp->cfg0_mod_base + |
| 499 | pp->config.cfg0_size; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 500 | } |
| 501 | } |
| 502 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 503 | if (!pp->dbi_base) { |
| 504 | pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start, |
| 505 | resource_size(&pp->cfg)); |
| 506 | if (!pp->dbi_base) { |
| 507 | dev_err(pp->dev, "error with ioremap\n"); |
| 508 | return -ENOMEM; |
| 509 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 510 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 511 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 512 | pp->mem_base = pp->mem.start; |
| 513 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 514 | if (!pp->va_cfg0_base) { |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame^] | 515 | pp->cfg0_base = pp->cfg.start; |
| 516 | pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base, |
| 517 | pp->config.cfg0_size); |
| 518 | if (!pp->va_cfg0_base) { |
| 519 | dev_err(pp->dev, "error with ioremap in function\n"); |
| 520 | return -ENOMEM; |
| 521 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 522 | } |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame^] | 523 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 524 | if (!pp->va_cfg1_base) { |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame^] | 525 | pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size; |
| 526 | pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base, |
| 527 | pp->config.cfg1_size); |
| 528 | if (!pp->va_cfg1_base) { |
| 529 | dev_err(pp->dev, "error with ioremap\n"); |
| 530 | return -ENOMEM; |
| 531 | } |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 532 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 533 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 534 | if (of_property_read_u32(np, "num-lanes", &pp->lanes)) { |
| 535 | dev_err(pp->dev, "Failed to parse the number of lanes\n"); |
| 536 | return -EINVAL; |
| 537 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 538 | |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 539 | if (IS_ENABLED(CONFIG_PCI_MSI)) { |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame^] | 540 | if (!pp->ops->msi_host_init) { |
| 541 | pp->irq_domain = irq_domain_add_linear(pp->dev->of_node, |
| 542 | MAX_MSI_IRQS, &msi_domain_ops, |
| 543 | &dw_pcie_msi_chip); |
| 544 | if (!pp->irq_domain) { |
| 545 | dev_err(pp->dev, "irq domain init failed\n"); |
| 546 | return -ENXIO; |
| 547 | } |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 548 | |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame^] | 549 | for (i = 0; i < MAX_MSI_IRQS; i++) |
| 550 | irq_create_mapping(pp->irq_domain, i); |
| 551 | } else { |
| 552 | ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip); |
| 553 | if (ret < 0) |
| 554 | return ret; |
| 555 | } |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 556 | } |
| 557 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 558 | if (pp->ops->host_init) |
| 559 | pp->ops->host_init(pp); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 560 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 561 | dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); |
| 562 | |
| 563 | /* program correct class for RC */ |
| 564 | dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); |
| 565 | |
| 566 | dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); |
| 567 | val |= PORT_LOGIC_SPEED_CHANGE; |
| 568 | dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); |
| 569 | |
| 570 | dw_pci.nr_controllers = 1; |
| 571 | dw_pci.private_data = (void **)&pp; |
| 572 | |
Lucas Stach | 804f57b | 2014-03-05 14:25:51 +0100 | [diff] [blame] | 573 | pci_common_init_dev(pp->dev, &dw_pci); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 574 | pci_assign_unassigned_resources(); |
| 575 | #ifdef CONFIG_PCI_DOMAINS |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 576 | dw_pci.domain++; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 577 | #endif |
| 578 | |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 579 | return 0; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 580 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 581 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 582 | static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev) |
| 583 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 584 | /* Program viewport 0 : OUTBOUND : CFG0 */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 585 | dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, |
| 586 | PCIE_ATU_VIEWPORT); |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 587 | dw_pcie_writel_rc(pp, pp->cfg0_mod_base, PCIE_ATU_LOWER_BASE); |
| 588 | dw_pcie_writel_rc(pp, (pp->cfg0_mod_base >> 32), PCIE_ATU_UPPER_BASE); |
| 589 | dw_pcie_writel_rc(pp, pp->cfg0_mod_base + pp->config.cfg0_size - 1, |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 590 | PCIE_ATU_LIMIT); |
| 591 | dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET); |
| 592 | dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET); |
| 593 | dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1); |
| 594 | dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 595 | } |
| 596 | |
| 597 | static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev) |
| 598 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 599 | /* Program viewport 1 : OUTBOUND : CFG1 */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 600 | dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, |
| 601 | PCIE_ATU_VIEWPORT); |
| 602 | dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1); |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 603 | dw_pcie_writel_rc(pp, pp->cfg1_mod_base, PCIE_ATU_LOWER_BASE); |
| 604 | dw_pcie_writel_rc(pp, (pp->cfg1_mod_base >> 32), PCIE_ATU_UPPER_BASE); |
| 605 | dw_pcie_writel_rc(pp, pp->cfg1_mod_base + pp->config.cfg1_size - 1, |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 606 | PCIE_ATU_LIMIT); |
| 607 | dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET); |
| 608 | dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET); |
Mohit Kumar | a19f88b | 2014-04-14 14:22:55 -0600 | [diff] [blame] | 609 | dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 610 | } |
| 611 | |
| 612 | static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp) |
| 613 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 614 | /* Program viewport 0 : OUTBOUND : MEM */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 615 | dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, |
| 616 | PCIE_ATU_VIEWPORT); |
| 617 | dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1); |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 618 | dw_pcie_writel_rc(pp, pp->mem_mod_base, PCIE_ATU_LOWER_BASE); |
| 619 | dw_pcie_writel_rc(pp, (pp->mem_mod_base >> 32), PCIE_ATU_UPPER_BASE); |
| 620 | dw_pcie_writel_rc(pp, pp->mem_mod_base + pp->config.mem_size - 1, |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 621 | PCIE_ATU_LIMIT); |
| 622 | dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 623 | dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr), |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 624 | PCIE_ATU_UPPER_TARGET); |
Mohit Kumar | a19f88b | 2014-04-14 14:22:55 -0600 | [diff] [blame] | 625 | dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 626 | } |
| 627 | |
| 628 | static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp) |
| 629 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 630 | /* Program viewport 1 : OUTBOUND : IO */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 631 | dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, |
| 632 | PCIE_ATU_VIEWPORT); |
| 633 | dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1); |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 634 | dw_pcie_writel_rc(pp, pp->io_mod_base, PCIE_ATU_LOWER_BASE); |
| 635 | dw_pcie_writel_rc(pp, (pp->io_mod_base >> 32), PCIE_ATU_UPPER_BASE); |
| 636 | dw_pcie_writel_rc(pp, pp->io_mod_base + pp->config.io_size - 1, |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 637 | PCIE_ATU_LIMIT); |
| 638 | dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 639 | dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr), |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 640 | PCIE_ATU_UPPER_TARGET); |
Mohit Kumar | a19f88b | 2014-04-14 14:22:55 -0600 | [diff] [blame] | 641 | dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 642 | } |
| 643 | |
| 644 | static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, |
| 645 | u32 devfn, int where, int size, u32 *val) |
| 646 | { |
| 647 | int ret = PCIBIOS_SUCCESSFUL; |
| 648 | u32 address, busdev; |
| 649 | |
| 650 | busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | |
| 651 | PCIE_ATU_FUNC(PCI_FUNC(devfn)); |
| 652 | address = where & ~0x3; |
| 653 | |
| 654 | if (bus->parent->number == pp->root_bus_nr) { |
| 655 | dw_pcie_prog_viewport_cfg0(pp, busdev); |
Pratyush Anand | a01ef59 | 2013-12-11 15:08:32 +0530 | [diff] [blame] | 656 | ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size, |
| 657 | val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 658 | dw_pcie_prog_viewport_mem_outbound(pp); |
| 659 | } else { |
| 660 | dw_pcie_prog_viewport_cfg1(pp, busdev); |
Pratyush Anand | a01ef59 | 2013-12-11 15:08:32 +0530 | [diff] [blame] | 661 | ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size, |
| 662 | val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 663 | dw_pcie_prog_viewport_io_outbound(pp); |
| 664 | } |
| 665 | |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 666 | return ret; |
| 667 | } |
| 668 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 669 | static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, |
| 670 | u32 devfn, int where, int size, u32 val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 671 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 672 | int ret = PCIBIOS_SUCCESSFUL; |
| 673 | u32 address, busdev; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 674 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 675 | busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | |
| 676 | PCIE_ATU_FUNC(PCI_FUNC(devfn)); |
| 677 | address = where & ~0x3; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 678 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 679 | if (bus->parent->number == pp->root_bus_nr) { |
| 680 | dw_pcie_prog_viewport_cfg0(pp, busdev); |
Pratyush Anand | a01ef59 | 2013-12-11 15:08:32 +0530 | [diff] [blame] | 681 | ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size, |
| 682 | val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 683 | dw_pcie_prog_viewport_mem_outbound(pp); |
| 684 | } else { |
| 685 | dw_pcie_prog_viewport_cfg1(pp, busdev); |
Pratyush Anand | a01ef59 | 2013-12-11 15:08:32 +0530 | [diff] [blame] | 686 | ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size, |
| 687 | val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 688 | dw_pcie_prog_viewport_io_outbound(pp); |
| 689 | } |
| 690 | |
| 691 | return ret; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 692 | } |
| 693 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 694 | static int dw_pcie_valid_config(struct pcie_port *pp, |
| 695 | struct pci_bus *bus, int dev) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 696 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 697 | /* If there is no link, then there is no device */ |
| 698 | if (bus->number != pp->root_bus_nr) { |
| 699 | if (!dw_pcie_link_up(pp)) |
| 700 | return 0; |
| 701 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 702 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 703 | /* access only one slot on each root port */ |
| 704 | if (bus->number == pp->root_bus_nr && dev > 0) |
| 705 | return 0; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 706 | |
| 707 | /* |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 708 | * do not read more than one device on the bus directly attached |
| 709 | * to RC's (Virtual Bridge's) DS side. |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 710 | */ |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 711 | if (bus->primary == pp->root_bus_nr && dev > 0) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 712 | return 0; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 713 | |
| 714 | return 1; |
| 715 | } |
| 716 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 717 | static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, |
| 718 | int size, u32 *val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 719 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 720 | struct pcie_port *pp = sys_to_pcie(bus->sysdata); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 721 | int ret; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 722 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 723 | if (!pp) { |
| 724 | BUG(); |
| 725 | return -EINVAL; |
| 726 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 727 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 728 | if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { |
| 729 | *val = 0xffffffff; |
| 730 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 731 | } |
| 732 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 733 | if (bus->number != pp->root_bus_nr) |
Murali Karicheri | a1c0ae9 | 2014-07-21 12:58:41 -0400 | [diff] [blame] | 734 | if (pp->ops->rd_other_conf) |
| 735 | ret = pp->ops->rd_other_conf(pp, bus, devfn, |
| 736 | where, size, val); |
| 737 | else |
| 738 | ret = dw_pcie_rd_other_conf(pp, bus, devfn, |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 739 | where, size, val); |
| 740 | else |
| 741 | ret = dw_pcie_rd_own_conf(pp, where, size, val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 742 | |
| 743 | return ret; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 744 | } |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 745 | |
| 746 | static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, |
| 747 | int where, int size, u32 val) |
| 748 | { |
| 749 | struct pcie_port *pp = sys_to_pcie(bus->sysdata); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 750 | int ret; |
| 751 | |
| 752 | if (!pp) { |
| 753 | BUG(); |
| 754 | return -EINVAL; |
| 755 | } |
| 756 | |
| 757 | if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) |
| 758 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 759 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 760 | if (bus->number != pp->root_bus_nr) |
Murali Karicheri | a1c0ae9 | 2014-07-21 12:58:41 -0400 | [diff] [blame] | 761 | if (pp->ops->wr_other_conf) |
| 762 | ret = pp->ops->wr_other_conf(pp, bus, devfn, |
| 763 | where, size, val); |
| 764 | else |
| 765 | ret = dw_pcie_wr_other_conf(pp, bus, devfn, |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 766 | where, size, val); |
| 767 | else |
| 768 | ret = dw_pcie_wr_own_conf(pp, where, size, val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 769 | |
| 770 | return ret; |
| 771 | } |
| 772 | |
| 773 | static struct pci_ops dw_pcie_ops = { |
| 774 | .read = dw_pcie_rd_conf, |
| 775 | .write = dw_pcie_wr_conf, |
| 776 | }; |
| 777 | |
Bjorn Helgaas | 73e4085 | 2013-10-09 09:12:37 -0600 | [diff] [blame] | 778 | static int dw_pcie_setup(int nr, struct pci_sys_data *sys) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 779 | { |
| 780 | struct pcie_port *pp; |
| 781 | |
| 782 | pp = sys_to_pcie(sys); |
| 783 | |
| 784 | if (!pp) |
| 785 | return 0; |
| 786 | |
| 787 | if (global_io_offset < SZ_1M && pp->config.io_size > 0) { |
| 788 | sys->io_offset = global_io_offset - pp->config.io_bus_addr; |
Pratyush Anand | fce8591 | 2013-12-11 15:08:33 +0530 | [diff] [blame] | 789 | pci_ioremap_io(global_io_offset, pp->io_base); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 790 | global_io_offset += SZ_64K; |
| 791 | pci_add_resource_offset(&sys->resources, &pp->io, |
| 792 | sys->io_offset); |
| 793 | } |
| 794 | |
| 795 | sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr; |
| 796 | pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset); |
| 797 | |
| 798 | return 1; |
| 799 | } |
| 800 | |
Bjorn Helgaas | 73e4085 | 2013-10-09 09:12:37 -0600 | [diff] [blame] | 801 | static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 802 | { |
| 803 | struct pci_bus *bus; |
| 804 | struct pcie_port *pp = sys_to_pcie(sys); |
| 805 | |
| 806 | if (pp) { |
| 807 | pp->root_bus_nr = sys->busnr; |
Lucas Stach | 804f57b | 2014-03-05 14:25:51 +0100 | [diff] [blame] | 808 | bus = pci_scan_root_bus(pp->dev, sys->busnr, &dw_pcie_ops, |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 809 | sys, &sys->resources); |
| 810 | } else { |
| 811 | bus = NULL; |
| 812 | BUG(); |
| 813 | } |
| 814 | |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame^] | 815 | if (bus && pp->ops->scan_bus) |
| 816 | pp->ops->scan_bus(pp); |
| 817 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 818 | return bus; |
| 819 | } |
| 820 | |
Bjorn Helgaas | 73e4085 | 2013-10-09 09:12:37 -0600 | [diff] [blame] | 821 | static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 822 | { |
| 823 | struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); |
Lucas Stach | 804f57b | 2014-03-05 14:25:51 +0100 | [diff] [blame] | 824 | int irq; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 825 | |
Lucas Stach | 804f57b | 2014-03-05 14:25:51 +0100 | [diff] [blame] | 826 | irq = of_irq_parse_and_map_pci(dev, slot, pin); |
| 827 | if (!irq) |
| 828 | irq = pp->irq; |
| 829 | |
| 830 | return irq; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 831 | } |
| 832 | |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 833 | static void dw_pcie_add_bus(struct pci_bus *bus) |
| 834 | { |
| 835 | if (IS_ENABLED(CONFIG_PCI_MSI)) { |
| 836 | struct pcie_port *pp = sys_to_pcie(bus->sysdata); |
| 837 | |
| 838 | dw_pcie_msi_chip.dev = pp->dev; |
| 839 | bus->msi = &dw_pcie_msi_chip; |
| 840 | } |
| 841 | } |
| 842 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 843 | static struct hw_pci dw_pci = { |
| 844 | .setup = dw_pcie_setup, |
| 845 | .scan = dw_pcie_scan_bus, |
| 846 | .map_irq = dw_pcie_map_irq, |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 847 | .add_bus = dw_pcie_add_bus, |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 848 | }; |
| 849 | |
| 850 | void dw_pcie_setup_rc(struct pcie_port *pp) |
| 851 | { |
| 852 | struct pcie_port_info *config = &pp->config; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 853 | u32 val; |
| 854 | u32 membase; |
| 855 | u32 memlimit; |
| 856 | |
Mohit Kumar | 66c5c34 | 2014-04-14 14:22:54 -0600 | [diff] [blame] | 857 | /* set the number of lanes */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 858 | dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 859 | val &= ~PORT_LINK_MODE_MASK; |
| 860 | switch (pp->lanes) { |
| 861 | case 1: |
| 862 | val |= PORT_LINK_MODE_1_LANES; |
| 863 | break; |
| 864 | case 2: |
| 865 | val |= PORT_LINK_MODE_2_LANES; |
| 866 | break; |
| 867 | case 4: |
| 868 | val |= PORT_LINK_MODE_4_LANES; |
| 869 | break; |
| 870 | } |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 871 | dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 872 | |
| 873 | /* set link width speed control register */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 874 | dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 875 | val &= ~PORT_LOGIC_LINK_WIDTH_MASK; |
| 876 | switch (pp->lanes) { |
| 877 | case 1: |
| 878 | val |= PORT_LOGIC_LINK_WIDTH_1_LANES; |
| 879 | break; |
| 880 | case 2: |
| 881 | val |= PORT_LOGIC_LINK_WIDTH_2_LANES; |
| 882 | break; |
| 883 | case 4: |
| 884 | val |= PORT_LOGIC_LINK_WIDTH_4_LANES; |
| 885 | break; |
| 886 | } |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 887 | dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 888 | |
| 889 | /* setup RC BARs */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 890 | dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0); |
Mohit Kumar | dbffdd6 | 2014-02-19 17:34:35 +0530 | [diff] [blame] | 891 | dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 892 | |
| 893 | /* setup interrupt pins */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 894 | dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 895 | val &= 0xffff00ff; |
| 896 | val |= 0x00000100; |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 897 | dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 898 | |
| 899 | /* setup bus numbers */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 900 | dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 901 | val &= 0xff000000; |
| 902 | val |= 0x00010100; |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 903 | dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 904 | |
| 905 | /* setup memory base, memory limit */ |
| 906 | membase = ((u32)pp->mem_base & 0xfff00000) >> 16; |
| 907 | memlimit = (config->mem_size + (u32)pp->mem_base) & 0xfff00000; |
| 908 | val = memlimit | membase; |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 909 | dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 910 | |
| 911 | /* setup command register */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 912 | dw_pcie_readl_rc(pp, PCI_COMMAND, &val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 913 | val &= 0xffff0000; |
| 914 | val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
| 915 | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 916 | dw_pcie_writel_rc(pp, val, PCI_COMMAND); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 917 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 918 | |
| 919 | MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>"); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 920 | MODULE_DESCRIPTION("Designware PCIe host controller driver"); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 921 | MODULE_LICENSE("GPL v2"); |