Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | #include <linux/hdmi.h> |
| 24 | #include <drm/drmP.h> |
| 25 | #include "radeon.h" |
| 26 | #include "sid.h" |
| 27 | |
| 28 | static u32 dce6_endpoint_rreg(struct radeon_device *rdev, |
| 29 | u32 block_offset, u32 reg) |
| 30 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 31 | unsigned long flags; |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 32 | u32 r; |
| 33 | |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 34 | spin_lock_irqsave(&rdev->end_idx_lock, flags); |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 35 | WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); |
| 36 | r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 37 | spin_unlock_irqrestore(&rdev->end_idx_lock, flags); |
| 38 | |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 39 | return r; |
| 40 | } |
| 41 | |
| 42 | static void dce6_endpoint_wreg(struct radeon_device *rdev, |
| 43 | u32 block_offset, u32 reg, u32 v) |
| 44 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 45 | unsigned long flags; |
| 46 | |
| 47 | spin_lock_irqsave(&rdev->end_idx_lock, flags); |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 48 | if (ASIC_IS_DCE8(rdev)) |
| 49 | WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); |
| 50 | else |
| 51 | WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, |
| 52 | AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg)); |
| 53 | WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 54 | spin_unlock_irqrestore(&rdev->end_idx_lock, flags); |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 55 | } |
| 56 | |
| 57 | #define RREG32_ENDPOINT(block, reg) dce6_endpoint_rreg(rdev, (block), (reg)) |
| 58 | #define WREG32_ENDPOINT(block, reg, v) dce6_endpoint_wreg(rdev, (block), (reg), (v)) |
| 59 | |
| 60 | |
| 61 | static void dce6_afmt_get_connected_pins(struct radeon_device *rdev) |
| 62 | { |
| 63 | int i; |
| 64 | u32 offset, tmp; |
| 65 | |
| 66 | for (i = 0; i < rdev->audio.num_pins; i++) { |
| 67 | offset = rdev->audio.pin[i].offset; |
| 68 | tmp = RREG32_ENDPOINT(offset, |
| 69 | AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); |
| 70 | if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1) |
| 71 | rdev->audio.pin[i].connected = false; |
| 72 | else |
| 73 | rdev->audio.pin[i].connected = true; |
| 74 | } |
| 75 | } |
| 76 | |
| 77 | struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev) |
| 78 | { |
| 79 | int i; |
| 80 | |
| 81 | dce6_afmt_get_connected_pins(rdev); |
| 82 | |
| 83 | for (i = 0; i < rdev->audio.num_pins; i++) { |
| 84 | if (rdev->audio.pin[i].connected) |
| 85 | return &rdev->audio.pin[i]; |
| 86 | } |
| 87 | DRM_ERROR("No connected audio pins found!\n"); |
| 88 | return NULL; |
| 89 | } |
| 90 | |
| 91 | void dce6_afmt_select_pin(struct drm_encoder *encoder) |
| 92 | { |
| 93 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 94 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 95 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 96 | u32 offset = dig->afmt->offset; |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 97 | |
| 98 | if (!dig->afmt->pin) |
| 99 | return; |
| 100 | |
Alex Deucher | 7cc0a3d | 2013-09-03 14:03:21 -0400 | [diff] [blame] | 101 | WREG32(AFMT_AUDIO_SRC_CONTROL + offset, |
| 102 | AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id)); |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 103 | } |
| 104 | |
Alex Deucher | b188025 | 2013-10-10 18:03:06 -0400 | [diff] [blame^] | 105 | void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, |
| 106 | struct drm_display_mode *mode) |
| 107 | { |
| 108 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 109 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 110 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 111 | struct drm_connector *connector; |
| 112 | struct radeon_connector *radeon_connector = NULL; |
| 113 | u32 tmp = 0, offset; |
| 114 | |
| 115 | if (!dig->afmt->pin) |
| 116 | return; |
| 117 | |
| 118 | offset = dig->afmt->pin->offset; |
| 119 | |
| 120 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
| 121 | if (connector->encoder == encoder) { |
| 122 | radeon_connector = to_radeon_connector(connector); |
| 123 | break; |
| 124 | } |
| 125 | } |
| 126 | |
| 127 | if (!radeon_connector) { |
| 128 | DRM_ERROR("Couldn't find encoder's connector\n"); |
| 129 | return; |
| 130 | } |
| 131 | |
| 132 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
| 133 | if (connector->latency_present[1]) |
| 134 | tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | |
| 135 | AUDIO_LIPSYNC(connector->audio_latency[1]); |
| 136 | else |
| 137 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); |
| 138 | } else { |
| 139 | if (connector->latency_present[0]) |
| 140 | tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | |
| 141 | AUDIO_LIPSYNC(connector->audio_latency[0]); |
| 142 | else |
| 143 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); |
| 144 | } |
| 145 | WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); |
| 146 | } |
| 147 | |
Rafał Miłecki | 6159b65 | 2013-08-15 11:16:30 +0200 | [diff] [blame] | 148 | void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder) |
| 149 | { |
| 150 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 151 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 152 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 153 | struct drm_connector *connector; |
| 154 | struct radeon_connector *radeon_connector = NULL; |
| 155 | u32 offset, tmp; |
| 156 | u8 *sadb; |
| 157 | int sad_count; |
| 158 | |
| 159 | if (!dig->afmt->pin) |
| 160 | return; |
| 161 | |
| 162 | offset = dig->afmt->pin->offset; |
| 163 | |
| 164 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
| 165 | if (connector->encoder == encoder) |
| 166 | radeon_connector = to_radeon_connector(connector); |
| 167 | } |
| 168 | |
| 169 | if (!radeon_connector) { |
| 170 | DRM_ERROR("Couldn't find encoder's connector\n"); |
| 171 | return; |
| 172 | } |
| 173 | |
| 174 | sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb); |
| 175 | if (sad_count < 0) { |
| 176 | DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); |
| 177 | return; |
| 178 | } |
| 179 | |
| 180 | /* program the speaker allocation */ |
| 181 | tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); |
| 182 | tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); |
| 183 | /* set HDMI mode */ |
| 184 | tmp |= HDMI_CONNECTION; |
| 185 | if (sad_count) |
| 186 | tmp |= SPEAKER_ALLOCATION(sadb[0]); |
| 187 | else |
| 188 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ |
| 189 | WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); |
| 190 | |
| 191 | kfree(sadb); |
| 192 | } |
| 193 | |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 194 | void dce6_afmt_write_sad_regs(struct drm_encoder *encoder) |
| 195 | { |
| 196 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 197 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 198 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Rafał Miłecki | 6159b65 | 2013-08-15 11:16:30 +0200 | [diff] [blame] | 199 | u32 offset; |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 200 | struct drm_connector *connector; |
| 201 | struct radeon_connector *radeon_connector = NULL; |
| 202 | struct cea_sad *sads; |
Rafał Miłecki | 6159b65 | 2013-08-15 11:16:30 +0200 | [diff] [blame] | 203 | int i, sad_count; |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 204 | |
| 205 | static const u16 eld_reg_to_type[][2] = { |
| 206 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, |
| 207 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, |
| 208 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, |
| 209 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, |
| 210 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, |
| 211 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, |
| 212 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, |
| 213 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, |
| 214 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, |
| 215 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, |
| 216 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, |
| 217 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, |
| 218 | }; |
| 219 | |
| 220 | if (!dig->afmt->pin) |
| 221 | return; |
| 222 | |
| 223 | offset = dig->afmt->pin->offset; |
| 224 | |
| 225 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
| 226 | if (connector->encoder == encoder) |
| 227 | radeon_connector = to_radeon_connector(connector); |
| 228 | } |
| 229 | |
| 230 | if (!radeon_connector) { |
| 231 | DRM_ERROR("Couldn't find encoder's connector\n"); |
| 232 | return; |
| 233 | } |
| 234 | |
| 235 | sad_count = drm_edid_to_sad(radeon_connector->edid, &sads); |
| 236 | if (sad_count < 0) { |
| 237 | DRM_ERROR("Couldn't read SADs: %d\n", sad_count); |
| 238 | return; |
| 239 | } |
| 240 | BUG_ON(!sads); |
| 241 | |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 242 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { |
| 243 | u32 value = 0; |
| 244 | int j; |
| 245 | |
| 246 | for (j = 0; j < sad_count; j++) { |
| 247 | struct cea_sad *sad = &sads[j]; |
| 248 | |
| 249 | if (sad->format == eld_reg_to_type[i][1]) { |
| 250 | value = MAX_CHANNELS(sad->channels) | |
| 251 | DESCRIPTOR_BYTE_2(sad->byte2) | |
| 252 | SUPPORTED_FREQUENCIES(sad->freq); |
| 253 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) |
| 254 | value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq); |
| 255 | break; |
| 256 | } |
| 257 | } |
| 258 | WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value); |
| 259 | } |
| 260 | |
| 261 | kfree(sads); |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 262 | } |
| 263 | |
| 264 | static int dce6_audio_chipset_supported(struct radeon_device *rdev) |
| 265 | { |
| 266 | return !ASIC_IS_NODCE(rdev); |
| 267 | } |
| 268 | |
| 269 | static void dce6_audio_enable(struct radeon_device *rdev, |
| 270 | struct r600_audio_pin *pin, |
| 271 | bool enable) |
| 272 | { |
| 273 | WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL, |
| 274 | AUDIO_ENABLED); |
| 275 | DRM_INFO("%s audio %d support\n", enable ? "Enabling" : "Disabling", pin->id); |
| 276 | } |
| 277 | |
| 278 | static const u32 pin_offsets[7] = |
| 279 | { |
| 280 | (0x5e00 - 0x5e00), |
| 281 | (0x5e18 - 0x5e00), |
| 282 | (0x5e30 - 0x5e00), |
| 283 | (0x5e48 - 0x5e00), |
| 284 | (0x5e60 - 0x5e00), |
| 285 | (0x5e78 - 0x5e00), |
| 286 | (0x5e90 - 0x5e00), |
| 287 | }; |
| 288 | |
| 289 | int dce6_audio_init(struct radeon_device *rdev) |
| 290 | { |
| 291 | int i; |
| 292 | |
| 293 | if (!radeon_audio || !dce6_audio_chipset_supported(rdev)) |
| 294 | return 0; |
| 295 | |
| 296 | rdev->audio.enabled = true; |
| 297 | |
| 298 | if (ASIC_IS_DCE8(rdev)) |
| 299 | rdev->audio.num_pins = 7; |
| 300 | else |
| 301 | rdev->audio.num_pins = 6; |
| 302 | |
| 303 | for (i = 0; i < rdev->audio.num_pins; i++) { |
| 304 | rdev->audio.pin[i].channels = -1; |
| 305 | rdev->audio.pin[i].rate = -1; |
| 306 | rdev->audio.pin[i].bits_per_sample = -1; |
| 307 | rdev->audio.pin[i].status_bits = 0; |
| 308 | rdev->audio.pin[i].category_code = 0; |
| 309 | rdev->audio.pin[i].connected = false; |
| 310 | rdev->audio.pin[i].offset = pin_offsets[i]; |
| 311 | rdev->audio.pin[i].id = i; |
| 312 | dce6_audio_enable(rdev, &rdev->audio.pin[i], true); |
| 313 | } |
| 314 | |
| 315 | return 0; |
| 316 | } |
| 317 | |
| 318 | void dce6_audio_fini(struct radeon_device *rdev) |
| 319 | { |
| 320 | int i; |
| 321 | |
| 322 | if (!rdev->audio.enabled) |
| 323 | return; |
| 324 | |
| 325 | for (i = 0; i < rdev->audio.num_pins; i++) |
| 326 | dce6_audio_enable(rdev, &rdev->audio.pin[i], false); |
| 327 | |
| 328 | rdev->audio.enabled = false; |
| 329 | } |