Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This program is free software; you can redistribute it and/or modify |
| 3 | * it under the terms of the GNU General Public License, version 2, as |
| 4 | * published by the Free Software Foundation. |
| 5 | * |
| 6 | * This program is distributed in the hope that it will be useful, |
| 7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 9 | * GNU General Public License for more details. |
| 10 | * |
| 11 | * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com> |
| 12 | * |
| 13 | * Derived from book3s_rmhandlers.S and other files, which are: |
| 14 | * |
| 15 | * Copyright SUSE Linux Products GmbH 2009 |
| 16 | * |
| 17 | * Authors: Alexander Graf <agraf@suse.de> |
| 18 | */ |
| 19 | |
| 20 | #include <asm/ppc_asm.h> |
| 21 | #include <asm/kvm_asm.h> |
| 22 | #include <asm/reg.h> |
Paul Mackerras | 177339d | 2011-07-23 17:41:11 +1000 | [diff] [blame] | 23 | #include <asm/mmu.h> |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 24 | #include <asm/page.h> |
Paul Mackerras | 177339d | 2011-07-23 17:41:11 +1000 | [diff] [blame] | 25 | #include <asm/ptrace.h> |
| 26 | #include <asm/hvcall.h> |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 27 | #include <asm/asm-offsets.h> |
| 28 | #include <asm/exception-64s.h> |
Paul Mackerras | f0888f7 | 2012-02-03 00:54:17 +0000 | [diff] [blame] | 29 | #include <asm/kvm_book3s_asm.h> |
Paul Mackerras | b4072df | 2012-11-23 22:37:50 +0000 | [diff] [blame] | 30 | #include <asm/mmu-hash64.h> |
Michael Neuling | e4e3812 | 2014-03-25 10:47:02 +1100 | [diff] [blame] | 31 | #include <asm/tm.h> |
| 32 | |
| 33 | #define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 34 | |
Anton Blanchard | 7ffcf8e | 2013-08-07 02:01:46 +1000 | [diff] [blame] | 35 | #ifdef __LITTLE_ENDIAN__ |
| 36 | #error Need to fix lppaca and SLB shadow accesses in little endian mode |
| 37 | #endif |
| 38 | |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 39 | /* Values in HSTATE_NAPPING(r13) */ |
| 40 | #define NAPPING_CEDE 1 |
| 41 | #define NAPPING_NOVCPU 2 |
| 42 | |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 43 | /* |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 44 | * Call kvmppc_hv_entry in real mode. |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 45 | * Must be called with interrupts hard-disabled. |
| 46 | * |
| 47 | * Input Registers: |
| 48 | * |
| 49 | * LR = return address to continue at after eventually re-enabling MMU |
| 50 | */ |
| 51 | _GLOBAL(kvmppc_hv_entry_trampoline) |
Paul Mackerras | 218309b | 2013-09-06 13:23:44 +1000 | [diff] [blame] | 52 | mflr r0 |
| 53 | std r0, PPC_LR_STKOFF(r1) |
| 54 | stdu r1, -112(r1) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 55 | mfmsr r10 |
Paul Mackerras | 218309b | 2013-09-06 13:23:44 +1000 | [diff] [blame] | 56 | LOAD_REG_ADDR(r5, kvmppc_call_hv_entry) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 57 | li r0,MSR_RI |
| 58 | andc r0,r10,r0 |
| 59 | li r6,MSR_IR | MSR_DR |
| 60 | andc r6,r10,r6 |
| 61 | mtmsrd r0,1 /* clear RI in MSR */ |
| 62 | mtsrr0 r5 |
| 63 | mtsrr1 r6 |
| 64 | RFI |
| 65 | |
Paul Mackerras | 218309b | 2013-09-06 13:23:44 +1000 | [diff] [blame] | 66 | kvmppc_call_hv_entry: |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 67 | ld r4, HSTATE_KVM_VCPU(r13) |
Paul Mackerras | 218309b | 2013-09-06 13:23:44 +1000 | [diff] [blame] | 68 | bl kvmppc_hv_entry |
| 69 | |
| 70 | /* Back from guest - restore host state and return to caller */ |
| 71 | |
Michael Neuling | eee7ff9 | 2014-01-08 21:25:19 +1100 | [diff] [blame] | 72 | BEGIN_FTR_SECTION |
Paul Mackerras | 218309b | 2013-09-06 13:23:44 +1000 | [diff] [blame] | 73 | /* Restore host DABR and DABRX */ |
| 74 | ld r5,HSTATE_DABR(r13) |
| 75 | li r6,7 |
| 76 | mtspr SPRN_DABR,r5 |
| 77 | mtspr SPRN_DABRX,r6 |
Michael Neuling | eee7ff9 | 2014-01-08 21:25:19 +1100 | [diff] [blame] | 78 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) |
Paul Mackerras | 218309b | 2013-09-06 13:23:44 +1000 | [diff] [blame] | 79 | |
| 80 | /* Restore SPRG3 */ |
Scott Wood | 9d378df | 2014-03-10 17:29:38 -0500 | [diff] [blame] | 81 | ld r3,PACA_SPRG_VDSO(r13) |
| 82 | mtspr SPRN_SPRG_VDSO_WRITE,r3 |
Paul Mackerras | 218309b | 2013-09-06 13:23:44 +1000 | [diff] [blame] | 83 | |
Paul Mackerras | 218309b | 2013-09-06 13:23:44 +1000 | [diff] [blame] | 84 | /* Reload the host's PMU registers */ |
| 85 | ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */ |
| 86 | lbz r4, LPPACA_PMCINUSE(r3) |
| 87 | cmpwi r4, 0 |
| 88 | beq 23f /* skip if not */ |
| 89 | lwz r3, HSTATE_PMC(r13) |
| 90 | lwz r4, HSTATE_PMC + 4(r13) |
| 91 | lwz r5, HSTATE_PMC + 8(r13) |
| 92 | lwz r6, HSTATE_PMC + 12(r13) |
| 93 | lwz r8, HSTATE_PMC + 16(r13) |
| 94 | lwz r9, HSTATE_PMC + 20(r13) |
| 95 | BEGIN_FTR_SECTION |
| 96 | lwz r10, HSTATE_PMC + 24(r13) |
| 97 | lwz r11, HSTATE_PMC + 28(r13) |
| 98 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) |
| 99 | mtspr SPRN_PMC1, r3 |
| 100 | mtspr SPRN_PMC2, r4 |
| 101 | mtspr SPRN_PMC3, r5 |
| 102 | mtspr SPRN_PMC4, r6 |
| 103 | mtspr SPRN_PMC5, r8 |
| 104 | mtspr SPRN_PMC6, r9 |
| 105 | BEGIN_FTR_SECTION |
| 106 | mtspr SPRN_PMC7, r10 |
| 107 | mtspr SPRN_PMC8, r11 |
| 108 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) |
| 109 | ld r3, HSTATE_MMCR(r13) |
| 110 | ld r4, HSTATE_MMCR + 8(r13) |
| 111 | ld r5, HSTATE_MMCR + 16(r13) |
Paul Mackerras | 72cde5a | 2014-03-25 10:47:08 +1100 | [diff] [blame] | 112 | ld r6, HSTATE_MMCR + 24(r13) |
| 113 | ld r7, HSTATE_MMCR + 32(r13) |
Paul Mackerras | 218309b | 2013-09-06 13:23:44 +1000 | [diff] [blame] | 114 | mtspr SPRN_MMCR1, r4 |
| 115 | mtspr SPRN_MMCRA, r5 |
Paul Mackerras | 72cde5a | 2014-03-25 10:47:08 +1100 | [diff] [blame] | 116 | mtspr SPRN_SIAR, r6 |
| 117 | mtspr SPRN_SDAR, r7 |
| 118 | BEGIN_FTR_SECTION |
| 119 | ld r8, HSTATE_MMCR + 40(r13) |
| 120 | ld r9, HSTATE_MMCR + 48(r13) |
| 121 | mtspr SPRN_MMCR2, r8 |
| 122 | mtspr SPRN_SIER, r9 |
| 123 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
Paul Mackerras | 218309b | 2013-09-06 13:23:44 +1000 | [diff] [blame] | 124 | mtspr SPRN_MMCR0, r3 |
| 125 | isync |
| 126 | 23: |
| 127 | |
| 128 | /* |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 129 | * Reload DEC. HDEC interrupts were disabled when |
| 130 | * we reloaded the host's LPCR value. |
| 131 | */ |
| 132 | ld r3, HSTATE_DECEXP(r13) |
| 133 | mftb r4 |
| 134 | subf r4, r4, r3 |
| 135 | mtspr SPRN_DEC, r4 |
| 136 | |
| 137 | /* |
Paul Mackerras | 218309b | 2013-09-06 13:23:44 +1000 | [diff] [blame] | 138 | * For external and machine check interrupts, we need |
| 139 | * to call the Linux handler to process the interrupt. |
| 140 | * We do that by jumping to absolute address 0x500 for |
| 141 | * external interrupts, or the machine_check_fwnmi label |
| 142 | * for machine checks (since firmware might have patched |
| 143 | * the vector area at 0x200). The [h]rfid at the end of the |
| 144 | * handler will return to the book3s_hv_interrupts.S code. |
| 145 | * For other interrupts we do the rfid to get back |
| 146 | * to the book3s_hv_interrupts.S code here. |
| 147 | */ |
| 148 | ld r8, 112+PPC_LR_STKOFF(r1) |
| 149 | addi r1, r1, 112 |
| 150 | ld r7, HSTATE_HOST_MSR(r13) |
| 151 | |
| 152 | cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK |
| 153 | cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL |
| 154 | BEGIN_FTR_SECTION |
| 155 | beq 11f |
| 156 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
| 157 | |
| 158 | /* RFI into the highmem handler, or branch to interrupt handler */ |
| 159 | mfmsr r6 |
| 160 | li r0, MSR_RI |
| 161 | andc r6, r6, r0 |
| 162 | mtmsrd r6, 1 /* Clear RI in MSR */ |
| 163 | mtsrr0 r8 |
| 164 | mtsrr1 r7 |
| 165 | beqa 0x500 /* external interrupt (PPC970) */ |
| 166 | beq cr1, 13f /* machine check */ |
| 167 | RFI |
| 168 | |
| 169 | /* On POWER7, we have external interrupts set to use HSRR0/1 */ |
| 170 | 11: mtspr SPRN_HSRR0, r8 |
| 171 | mtspr SPRN_HSRR1, r7 |
| 172 | ba 0x500 |
| 173 | |
| 174 | 13: b machine_check_fwnmi |
| 175 | |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 176 | kvmppc_primary_no_guest: |
| 177 | /* We handle this much like a ceded vcpu */ |
| 178 | /* set our bit in napping_threads */ |
| 179 | ld r5, HSTATE_KVM_VCORE(r13) |
| 180 | lbz r7, HSTATE_PTID(r13) |
| 181 | li r0, 1 |
| 182 | sld r0, r0, r7 |
| 183 | addi r6, r5, VCORE_NAPPING_THREADS |
| 184 | 1: lwarx r3, 0, r6 |
| 185 | or r3, r3, r0 |
| 186 | stwcx. r3, 0, r6 |
| 187 | bne 1b |
| 188 | /* order napping_threads update vs testing entry_exit_count */ |
| 189 | isync |
| 190 | li r12, 0 |
| 191 | lwz r7, VCORE_ENTRY_EXIT(r5) |
| 192 | cmpwi r7, 0x100 |
| 193 | bge kvm_novcpu_exit /* another thread already exiting */ |
| 194 | li r3, NAPPING_NOVCPU |
| 195 | stb r3, HSTATE_NAPPING(r13) |
| 196 | li r3, 1 |
| 197 | stb r3, HSTATE_HWTHREAD_REQ(r13) |
| 198 | |
| 199 | b kvm_do_nap |
| 200 | |
| 201 | kvm_novcpu_wakeup: |
| 202 | ld r1, HSTATE_HOST_R1(r13) |
| 203 | ld r5, HSTATE_KVM_VCORE(r13) |
| 204 | li r0, 0 |
| 205 | stb r0, HSTATE_NAPPING(r13) |
| 206 | stb r0, HSTATE_HWTHREAD_REQ(r13) |
| 207 | |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 208 | /* check the wake reason */ |
| 209 | bl kvmppc_check_wake_reason |
| 210 | |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 211 | /* see if any other thread is already exiting */ |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 212 | lwz r0, VCORE_ENTRY_EXIT(r5) |
| 213 | cmpwi r0, 0x100 |
| 214 | bge kvm_novcpu_exit |
| 215 | |
| 216 | /* clear our bit in napping_threads */ |
| 217 | lbz r7, HSTATE_PTID(r13) |
| 218 | li r0, 1 |
| 219 | sld r0, r0, r7 |
| 220 | addi r6, r5, VCORE_NAPPING_THREADS |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 221 | 4: lwarx r7, 0, r6 |
| 222 | andc r7, r7, r0 |
| 223 | stwcx. r7, 0, r6 |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 224 | bne 4b |
| 225 | |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 226 | /* See if the wake reason means we need to exit */ |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 227 | cmpdi r3, 0 |
| 228 | bge kvm_novcpu_exit |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 229 | |
| 230 | /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */ |
| 231 | ld r4, HSTATE_KVM_VCPU(r13) |
| 232 | cmpdi r4, 0 |
| 233 | bne kvmppc_got_guest |
| 234 | |
| 235 | kvm_novcpu_exit: |
| 236 | b hdec_soon |
| 237 | |
Paul Mackerras | 371fefd | 2011-06-29 00:23:08 +0000 | [diff] [blame] | 238 | /* |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 239 | * We come in here when wakened from nap mode. |
Paul Mackerras | 371fefd | 2011-06-29 00:23:08 +0000 | [diff] [blame] | 240 | * Relocation is off and most register values are lost. |
| 241 | * r13 points to the PACA. |
| 242 | */ |
| 243 | .globl kvm_start_guest |
| 244 | kvm_start_guest: |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 245 | ld r2,PACATOC(r13) |
| 246 | |
Paul Mackerras | f0888f7 | 2012-02-03 00:54:17 +0000 | [diff] [blame] | 247 | li r0,KVM_HWTHREAD_IN_KVM |
| 248 | stb r0,HSTATE_HWTHREAD_STATE(r13) |
| 249 | |
| 250 | /* NV GPR values from power7_idle() will no longer be valid */ |
| 251 | li r0,1 |
| 252 | stb r0,PACA_NAPSTATELOST(r13) |
| 253 | |
Paul Mackerras | 4619ac8 | 2013-04-17 20:31:41 +0000 | [diff] [blame] | 254 | /* were we napping due to cede? */ |
| 255 | lbz r0,HSTATE_NAPPING(r13) |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 256 | cmpwi r0,NAPPING_CEDE |
| 257 | beq kvm_end_cede |
| 258 | cmpwi r0,NAPPING_NOVCPU |
| 259 | beq kvm_novcpu_wakeup |
| 260 | |
| 261 | ld r1,PACAEMERGSP(r13) |
| 262 | subi r1,r1,STACK_FRAME_OVERHEAD |
Paul Mackerras | 4619ac8 | 2013-04-17 20:31:41 +0000 | [diff] [blame] | 263 | |
| 264 | /* |
| 265 | * We weren't napping due to cede, so this must be a secondary |
| 266 | * thread being woken up to run a guest, or being woken up due |
| 267 | * to a stray IPI. (Or due to some machine check or hypervisor |
| 268 | * maintenance interrupt while the core is in KVM.) |
| 269 | */ |
Paul Mackerras | f0888f7 | 2012-02-03 00:54:17 +0000 | [diff] [blame] | 270 | |
| 271 | /* Check the wake reason in SRR1 to see why we got here */ |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 272 | bl kvmppc_check_wake_reason |
| 273 | cmpdi r3, 0 |
| 274 | bge kvm_no_guest |
Paul Mackerras | f0888f7 | 2012-02-03 00:54:17 +0000 | [diff] [blame] | 275 | |
Paul Mackerras | 4619ac8 | 2013-04-17 20:31:41 +0000 | [diff] [blame] | 276 | /* get vcpu pointer, NULL if we have no vcpu to run */ |
Paul Mackerras | 7b444c6 | 2012-10-15 01:16:14 +0000 | [diff] [blame] | 277 | ld r4,HSTATE_KVM_VCPU(r13) |
| 278 | cmpdi r4,0 |
Paul Mackerras | f0888f7 | 2012-02-03 00:54:17 +0000 | [diff] [blame] | 279 | /* if we have no vcpu to run, go back to sleep */ |
Paul Mackerras | 7b444c6 | 2012-10-15 01:16:14 +0000 | [diff] [blame] | 280 | beq kvm_no_guest |
Paul Mackerras | f0888f7 | 2012-02-03 00:54:17 +0000 | [diff] [blame] | 281 | |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 282 | /* Set HSTATE_DSCR(r13) to something sensible */ |
| 283 | LOAD_REG_ADDR(r6, dscr_default) |
| 284 | ld r6, 0(r6) |
| 285 | std r6, HSTATE_DSCR(r13) |
Paul Mackerras | 371fefd | 2011-06-29 00:23:08 +0000 | [diff] [blame] | 286 | |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 287 | bl kvmppc_hv_entry |
Paul Mackerras | 218309b | 2013-09-06 13:23:44 +1000 | [diff] [blame] | 288 | |
| 289 | /* Back from the guest, go back to nap */ |
| 290 | /* Clear our vcpu pointer so we don't come back in early */ |
| 291 | li r0, 0 |
| 292 | std r0, HSTATE_KVM_VCPU(r13) |
Paul Mackerras | f019b7a | 2013-11-16 17:46:03 +1100 | [diff] [blame] | 293 | /* |
| 294 | * Make sure we clear HSTATE_KVM_VCPU(r13) before incrementing |
| 295 | * the nap_count, because once the increment to nap_count is |
| 296 | * visible we could be given another vcpu. |
| 297 | */ |
Paul Mackerras | 218309b | 2013-09-06 13:23:44 +1000 | [diff] [blame] | 298 | lwsync |
Paul Mackerras | 218309b | 2013-09-06 13:23:44 +1000 | [diff] [blame] | 299 | |
| 300 | /* increment the nap count and then go to nap mode */ |
| 301 | ld r4, HSTATE_KVM_VCORE(r13) |
| 302 | addi r4, r4, VCORE_NAP_COUNT |
Paul Mackerras | 218309b | 2013-09-06 13:23:44 +1000 | [diff] [blame] | 303 | 51: lwarx r3, 0, r4 |
| 304 | addi r3, r3, 1 |
| 305 | stwcx. r3, 0, r4 |
| 306 | bne 51b |
| 307 | |
| 308 | kvm_no_guest: |
| 309 | li r0, KVM_HWTHREAD_IN_NAP |
| 310 | stb r0, HSTATE_HWTHREAD_STATE(r13) |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 311 | kvm_do_nap: |
Paul Mackerras | 218309b | 2013-09-06 13:23:44 +1000 | [diff] [blame] | 312 | li r3, LPCR_PECE0 |
| 313 | mfspr r4, SPRN_LPCR |
| 314 | rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1 |
| 315 | mtspr SPRN_LPCR, r4 |
| 316 | isync |
| 317 | std r0, HSTATE_SCRATCH0(r13) |
| 318 | ptesync |
| 319 | ld r0, HSTATE_SCRATCH0(r13) |
| 320 | 1: cmpd r0, r0 |
| 321 | bne 1b |
| 322 | nap |
| 323 | b . |
| 324 | |
| 325 | /****************************************************************************** |
| 326 | * * |
| 327 | * Entry code * |
| 328 | * * |
| 329 | *****************************************************************************/ |
| 330 | |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 331 | .global kvmppc_hv_entry |
| 332 | kvmppc_hv_entry: |
| 333 | |
| 334 | /* Required state: |
| 335 | * |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 336 | * R4 = vcpu pointer (or NULL) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 337 | * MSR = ~IR|DR |
| 338 | * R13 = PACA |
| 339 | * R1 = host R1 |
| 340 | * all other volatile GPRS = free |
| 341 | */ |
| 342 | mflr r0 |
Paul Mackerras | 218309b | 2013-09-06 13:23:44 +1000 | [diff] [blame] | 343 | std r0, PPC_LR_STKOFF(r1) |
| 344 | stdu r1, -112(r1) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 345 | |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 346 | /* Save R1 in the PACA */ |
| 347 | std r1, HSTATE_HOST_R1(r13) |
| 348 | |
Paul Mackerras | 44a3add | 2013-10-04 21:45:04 +1000 | [diff] [blame] | 349 | li r6, KVM_GUEST_MODE_HOST_HV |
| 350 | stb r6, HSTATE_IN_GUEST(r13) |
| 351 | |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 352 | /* Clear out SLB */ |
| 353 | li r6,0 |
| 354 | slbmte r6,r6 |
| 355 | slbia |
| 356 | ptesync |
| 357 | |
Paul Mackerras | 9e368f2 | 2011-06-29 00:40:08 +0000 | [diff] [blame] | 358 | BEGIN_FTR_SECTION |
| 359 | b 30f |
| 360 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) |
| 361 | /* |
| 362 | * POWER7 host -> guest partition switch code. |
| 363 | * We don't have to lock against concurrent tlbies, |
| 364 | * but we do have to coordinate across hardware threads. |
| 365 | */ |
Paul Mackerras | 371fefd | 2011-06-29 00:23:08 +0000 | [diff] [blame] | 366 | /* Increment entry count iff exit count is zero. */ |
| 367 | ld r5,HSTATE_KVM_VCORE(r13) |
| 368 | addi r9,r5,VCORE_ENTRY_EXIT |
| 369 | 21: lwarx r3,0,r9 |
| 370 | cmpwi r3,0x100 /* any threads starting to exit? */ |
| 371 | bge secondary_too_late /* if so we're too late to the party */ |
| 372 | addi r3,r3,1 |
| 373 | stwcx. r3,0,r9 |
| 374 | bne 21b |
| 375 | |
| 376 | /* Primary thread switches to guest partition. */ |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 377 | ld r9,VCORE_KVM(r5) /* pointer to struct kvm */ |
| 378 | lbz r6,HSTATE_PTID(r13) |
Paul Mackerras | 371fefd | 2011-06-29 00:23:08 +0000 | [diff] [blame] | 379 | cmpwi r6,0 |
| 380 | bne 20f |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 381 | ld r6,KVM_SDR1(r9) |
| 382 | lwz r7,KVM_LPID(r9) |
| 383 | li r0,LPID_RSVD /* switch to reserved LPID */ |
| 384 | mtspr SPRN_LPID,r0 |
| 385 | ptesync |
| 386 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ |
| 387 | mtspr SPRN_LPID,r7 |
| 388 | isync |
Paul Mackerras | 1b400ba | 2012-11-21 23:28:08 +0000 | [diff] [blame] | 389 | |
| 390 | /* See if we need to flush the TLB */ |
| 391 | lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */ |
| 392 | clrldi r7,r6,64-6 /* extract bit number (6 bits) */ |
| 393 | srdi r6,r6,6 /* doubleword number */ |
| 394 | sldi r6,r6,3 /* address offset */ |
| 395 | add r6,r6,r9 |
| 396 | addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */ |
Paul Mackerras | 371fefd | 2011-06-29 00:23:08 +0000 | [diff] [blame] | 397 | li r0,1 |
Paul Mackerras | 1b400ba | 2012-11-21 23:28:08 +0000 | [diff] [blame] | 398 | sld r0,r0,r7 |
| 399 | ld r7,0(r6) |
| 400 | and. r7,r7,r0 |
| 401 | beq 22f |
| 402 | 23: ldarx r7,0,r6 /* if set, clear the bit */ |
| 403 | andc r7,r7,r0 |
| 404 | stdcx. r7,0,r6 |
| 405 | bne 23b |
Paul Mackerras | ca25205 | 2014-01-08 21:25:22 +1100 | [diff] [blame] | 406 | /* Flush the TLB of any entries for this LPID */ |
| 407 | /* use arch 2.07S as a proxy for POWER8 */ |
| 408 | BEGIN_FTR_SECTION |
| 409 | li r6,512 /* POWER8 has 512 sets */ |
| 410 | FTR_SECTION_ELSE |
| 411 | li r6,128 /* POWER7 has 128 sets */ |
| 412 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S) |
Paul Mackerras | 1b400ba | 2012-11-21 23:28:08 +0000 | [diff] [blame] | 413 | mtctr r6 |
| 414 | li r7,0x800 /* IS field = 0b10 */ |
| 415 | ptesync |
| 416 | 28: tlbiel r7 |
| 417 | addi r7,r7,0x1000 |
| 418 | bdnz 28b |
| 419 | ptesync |
| 420 | |
Paul Mackerras | 93b0f4d | 2013-09-06 13:17:46 +1000 | [diff] [blame] | 421 | /* Add timebase offset onto timebase */ |
| 422 | 22: ld r8,VCORE_TB_OFFSET(r5) |
| 423 | cmpdi r8,0 |
| 424 | beq 37f |
| 425 | mftb r6 /* current host timebase */ |
| 426 | add r8,r8,r6 |
| 427 | mtspr SPRN_TBU40,r8 /* update upper 40 bits */ |
| 428 | mftb r7 /* check if lower 24 bits overflowed */ |
| 429 | clrldi r6,r6,40 |
| 430 | clrldi r7,r7,40 |
| 431 | cmpld r7,r6 |
| 432 | bge 37f |
| 433 | addis r8,r8,0x100 /* if so, increment upper 40 bits */ |
| 434 | mtspr SPRN_TBU40,r8 |
| 435 | |
Paul Mackerras | 388cc6e | 2013-09-21 14:35:02 +1000 | [diff] [blame] | 436 | /* Load guest PCR value to select appropriate compat mode */ |
| 437 | 37: ld r7, VCORE_PCR(r5) |
| 438 | cmpdi r7, 0 |
| 439 | beq 38f |
| 440 | mtspr SPRN_PCR, r7 |
| 441 | 38: |
Michael Neuling | b005255e | 2014-01-08 21:25:21 +1100 | [diff] [blame] | 442 | |
| 443 | BEGIN_FTR_SECTION |
| 444 | /* DPDES is shared between threads */ |
| 445 | ld r8, VCORE_DPDES(r5) |
| 446 | mtspr SPRN_DPDES, r8 |
| 447 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
| 448 | |
Paul Mackerras | 388cc6e | 2013-09-21 14:35:02 +1000 | [diff] [blame] | 449 | li r0,1 |
Paul Mackerras | 371fefd | 2011-06-29 00:23:08 +0000 | [diff] [blame] | 450 | stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */ |
| 451 | b 10f |
| 452 | |
| 453 | /* Secondary threads wait for primary to have done partition switch */ |
| 454 | 20: lbz r0,VCORE_IN_GUEST(r5) |
| 455 | cmpwi r0,0 |
| 456 | beq 20b |
Paul Mackerras | aa04b4c | 2011-06-29 00:25:44 +0000 | [diff] [blame] | 457 | |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 458 | /* Set LPCR and RMOR. */ |
Paul Mackerras | a0144e2 | 2013-09-20 14:52:38 +1000 | [diff] [blame] | 459 | 10: ld r8,VCORE_LPCR(r5) |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 460 | mtspr SPRN_LPCR,r8 |
Paul Mackerras | aa04b4c | 2011-06-29 00:25:44 +0000 | [diff] [blame] | 461 | ld r8,KVM_RMOR(r9) |
| 462 | mtspr SPRN_RMOR,r8 |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 463 | isync |
| 464 | |
| 465 | /* Check if HDEC expires soon */ |
| 466 | mfspr r3,SPRN_HDEC |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 467 | cmpwi r3,512 /* 1 microsecond */ |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 468 | li r12,BOOK3S_INTERRUPT_HV_DECREMENTER |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 469 | blt hdec_soon |
Paul Mackerras | 9e368f2 | 2011-06-29 00:40:08 +0000 | [diff] [blame] | 470 | b 31f |
| 471 | |
| 472 | /* |
| 473 | * PPC970 host -> guest partition switch code. |
| 474 | * We have to lock against concurrent tlbies, |
| 475 | * using native_tlbie_lock to lock against host tlbies |
| 476 | * and kvm->arch.tlbie_lock to lock against guest tlbies. |
| 477 | * We also have to invalidate the TLB since its |
| 478 | * entries aren't tagged with the LPID. |
| 479 | */ |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 480 | 30: ld r5,HSTATE_KVM_VCORE(r13) |
| 481 | ld r9,VCORE_KVM(r5) /* pointer to struct kvm */ |
Paul Mackerras | 9e368f2 | 2011-06-29 00:40:08 +0000 | [diff] [blame] | 482 | |
| 483 | /* first take native_tlbie_lock */ |
| 484 | .section ".toc","aw" |
| 485 | toc_tlbie_lock: |
| 486 | .tc native_tlbie_lock[TC],native_tlbie_lock |
| 487 | .previous |
| 488 | ld r3,toc_tlbie_lock@toc(2) |
Anton Blanchard | 54bb7f4 | 2013-08-07 02:01:51 +1000 | [diff] [blame] | 489 | #ifdef __BIG_ENDIAN__ |
Paul Mackerras | 9e368f2 | 2011-06-29 00:40:08 +0000 | [diff] [blame] | 490 | lwz r8,PACA_LOCK_TOKEN(r13) |
Anton Blanchard | 54bb7f4 | 2013-08-07 02:01:51 +1000 | [diff] [blame] | 491 | #else |
| 492 | lwz r8,PACAPACAINDEX(r13) |
| 493 | #endif |
Paul Mackerras | 9e368f2 | 2011-06-29 00:40:08 +0000 | [diff] [blame] | 494 | 24: lwarx r0,0,r3 |
| 495 | cmpwi r0,0 |
| 496 | bne 24b |
| 497 | stwcx. r8,0,r3 |
| 498 | bne 24b |
| 499 | isync |
| 500 | |
Paul Mackerras | a0144e2 | 2013-09-20 14:52:38 +1000 | [diff] [blame] | 501 | ld r5,HSTATE_KVM_VCORE(r13) |
| 502 | ld r7,VCORE_LPCR(r5) /* use vcore->lpcr to store HID4 */ |
Paul Mackerras | 9e368f2 | 2011-06-29 00:40:08 +0000 | [diff] [blame] | 503 | li r0,0x18f |
| 504 | rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */ |
| 505 | or r0,r7,r0 |
| 506 | ptesync |
| 507 | sync |
| 508 | mtspr SPRN_HID4,r0 /* switch to reserved LPID */ |
| 509 | isync |
| 510 | li r0,0 |
| 511 | stw r0,0(r3) /* drop native_tlbie_lock */ |
| 512 | |
| 513 | /* invalidate the whole TLB */ |
| 514 | li r0,256 |
| 515 | mtctr r0 |
| 516 | li r6,0 |
| 517 | 25: tlbiel r6 |
| 518 | addi r6,r6,0x1000 |
| 519 | bdnz 25b |
| 520 | ptesync |
| 521 | |
| 522 | /* Take the guest's tlbie_lock */ |
| 523 | addi r3,r9,KVM_TLBIE_LOCK |
| 524 | 24: lwarx r0,0,r3 |
| 525 | cmpwi r0,0 |
| 526 | bne 24b |
| 527 | stwcx. r8,0,r3 |
| 528 | bne 24b |
| 529 | isync |
| 530 | ld r6,KVM_SDR1(r9) |
| 531 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ |
| 532 | |
| 533 | /* Set up HID4 with the guest's LPID etc. */ |
| 534 | sync |
| 535 | mtspr SPRN_HID4,r7 |
| 536 | isync |
| 537 | |
| 538 | /* drop the guest's tlbie_lock */ |
| 539 | li r0,0 |
| 540 | stw r0,0(r3) |
| 541 | |
| 542 | /* Check if HDEC expires soon */ |
| 543 | mfspr r3,SPRN_HDEC |
| 544 | cmpwi r3,10 |
| 545 | li r12,BOOK3S_INTERRUPT_HV_DECREMENTER |
Paul Mackerras | 9e368f2 | 2011-06-29 00:40:08 +0000 | [diff] [blame] | 546 | blt hdec_soon |
| 547 | |
| 548 | /* Enable HDEC interrupts */ |
| 549 | mfspr r0,SPRN_HID0 |
| 550 | li r3,1 |
| 551 | rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1 |
| 552 | sync |
| 553 | mtspr SPRN_HID0,r0 |
| 554 | mfspr r0,SPRN_HID0 |
| 555 | mfspr r0,SPRN_HID0 |
| 556 | mfspr r0,SPRN_HID0 |
| 557 | mfspr r0,SPRN_HID0 |
| 558 | mfspr r0,SPRN_HID0 |
| 559 | mfspr r0,SPRN_HID0 |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 560 | 31: |
| 561 | /* Do we have a guest vcpu to run? */ |
| 562 | cmpdi r4, 0 |
| 563 | beq kvmppc_primary_no_guest |
| 564 | kvmppc_got_guest: |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 565 | |
| 566 | /* Load up guest SLB entries */ |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 567 | lwz r5,VCPU_SLB_MAX(r4) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 568 | cmpwi r5,0 |
| 569 | beq 9f |
| 570 | mtctr r5 |
| 571 | addi r6,r4,VCPU_SLB |
| 572 | 1: ld r8,VCPU_SLB_E(r6) |
| 573 | ld r9,VCPU_SLB_V(r6) |
| 574 | slbmte r9,r8 |
| 575 | addi r6,r6,VCPU_SLB_SIZE |
| 576 | bdnz 1b |
| 577 | 9: |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 578 | /* Increment yield count if they have a VPA */ |
| 579 | ld r3, VCPU_VPA(r4) |
| 580 | cmpdi r3, 0 |
| 581 | beq 25f |
| 582 | lwz r5, LPPACA_YIELDCOUNT(r3) |
| 583 | addi r5, r5, 1 |
| 584 | stw r5, LPPACA_YIELDCOUNT(r3) |
| 585 | li r6, 1 |
| 586 | stb r6, VCPU_VPA_DIRTY(r4) |
| 587 | 25: |
| 588 | |
| 589 | BEGIN_FTR_SECTION |
| 590 | /* Save purr/spurr */ |
| 591 | mfspr r5,SPRN_PURR |
| 592 | mfspr r6,SPRN_SPURR |
| 593 | std r5,HSTATE_PURR(r13) |
| 594 | std r6,HSTATE_SPURR(r13) |
| 595 | ld r7,VCPU_PURR(r4) |
| 596 | ld r8,VCPU_SPURR(r4) |
| 597 | mtspr SPRN_PURR,r7 |
| 598 | mtspr SPRN_SPURR,r8 |
| 599 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
| 600 | |
Michael Neuling | eee7ff9 | 2014-01-08 21:25:19 +1100 | [diff] [blame] | 601 | BEGIN_FTR_SECTION |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 602 | /* Set partition DABR */ |
| 603 | /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */ |
Paul Mackerras | 8563bf5 | 2014-01-08 21:25:29 +1100 | [diff] [blame] | 604 | lwz r5,VCPU_DABRX(r4) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 605 | ld r6,VCPU_DABR(r4) |
| 606 | mtspr SPRN_DABRX,r5 |
| 607 | mtspr SPRN_DABR,r6 |
Michael Neuling | eee7ff9 | 2014-01-08 21:25:19 +1100 | [diff] [blame] | 608 | BEGIN_FTR_SECTION_NESTED(89) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 609 | isync |
Michael Neuling | eee7ff9 | 2014-01-08 21:25:19 +1100 | [diff] [blame] | 610 | END_FTR_SECTION_NESTED(CPU_FTR_ARCH_206, CPU_FTR_ARCH_206, 89) |
| 611 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 612 | |
Michael Neuling | e4e3812 | 2014-03-25 10:47:02 +1100 | [diff] [blame] | 613 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
| 614 | BEGIN_FTR_SECTION |
| 615 | b skip_tm |
| 616 | END_FTR_SECTION_IFCLR(CPU_FTR_TM) |
| 617 | |
| 618 | /* Turn on TM/FP/VSX/VMX so we can restore them. */ |
| 619 | mfmsr r5 |
| 620 | li r6, MSR_TM >> 32 |
| 621 | sldi r6, r6, 32 |
| 622 | or r5, r5, r6 |
| 623 | ori r5, r5, MSR_FP |
| 624 | oris r5, r5, (MSR_VEC | MSR_VSX)@h |
| 625 | mtmsrd r5 |
| 626 | |
| 627 | /* |
| 628 | * The user may change these outside of a transaction, so they must |
| 629 | * always be context switched. |
| 630 | */ |
| 631 | ld r5, VCPU_TFHAR(r4) |
| 632 | ld r6, VCPU_TFIAR(r4) |
| 633 | ld r7, VCPU_TEXASR(r4) |
| 634 | mtspr SPRN_TFHAR, r5 |
| 635 | mtspr SPRN_TFIAR, r6 |
| 636 | mtspr SPRN_TEXASR, r7 |
| 637 | |
| 638 | ld r5, VCPU_MSR(r4) |
| 639 | rldicl. r5, r5, 64 - MSR_TS_S_LG, 62 |
| 640 | beq skip_tm /* TM not active in guest */ |
| 641 | |
| 642 | /* Make sure the failure summary is set, otherwise we'll program check |
| 643 | * when we trechkpt. It's possible that this might have been not set |
| 644 | * on a kvmppc_set_one_reg() call but we shouldn't let this crash the |
| 645 | * host. |
| 646 | */ |
| 647 | oris r7, r7, (TEXASR_FS)@h |
| 648 | mtspr SPRN_TEXASR, r7 |
| 649 | |
| 650 | /* |
| 651 | * We need to load up the checkpointed state for the guest. |
| 652 | * We need to do this early as it will blow away any GPRs, VSRs and |
| 653 | * some SPRs. |
| 654 | */ |
| 655 | |
| 656 | mr r31, r4 |
| 657 | addi r3, r31, VCPU_FPRS_TM |
| 658 | bl .load_fp_state |
| 659 | addi r3, r31, VCPU_VRS_TM |
| 660 | bl .load_vr_state |
| 661 | mr r4, r31 |
| 662 | lwz r7, VCPU_VRSAVE_TM(r4) |
| 663 | mtspr SPRN_VRSAVE, r7 |
| 664 | |
| 665 | ld r5, VCPU_LR_TM(r4) |
| 666 | lwz r6, VCPU_CR_TM(r4) |
| 667 | ld r7, VCPU_CTR_TM(r4) |
| 668 | ld r8, VCPU_AMR_TM(r4) |
| 669 | ld r9, VCPU_TAR_TM(r4) |
| 670 | mtlr r5 |
| 671 | mtcr r6 |
| 672 | mtctr r7 |
| 673 | mtspr SPRN_AMR, r8 |
| 674 | mtspr SPRN_TAR, r9 |
| 675 | |
| 676 | /* |
| 677 | * Load up PPR and DSCR values but don't put them in the actual SPRs |
| 678 | * till the last moment to avoid running with userspace PPR and DSCR for |
| 679 | * too long. |
| 680 | */ |
| 681 | ld r29, VCPU_DSCR_TM(r4) |
| 682 | ld r30, VCPU_PPR_TM(r4) |
| 683 | |
| 684 | std r2, PACATMSCRATCH(r13) /* Save TOC */ |
| 685 | |
| 686 | /* Clear the MSR RI since r1, r13 are all going to be foobar. */ |
| 687 | li r5, 0 |
| 688 | mtmsrd r5, 1 |
| 689 | |
| 690 | /* Load GPRs r0-r28 */ |
| 691 | reg = 0 |
| 692 | .rept 29 |
| 693 | ld reg, VCPU_GPRS_TM(reg)(r31) |
| 694 | reg = reg + 1 |
| 695 | .endr |
| 696 | |
| 697 | mtspr SPRN_DSCR, r29 |
| 698 | mtspr SPRN_PPR, r30 |
| 699 | |
| 700 | /* Load final GPRs */ |
| 701 | ld 29, VCPU_GPRS_TM(29)(r31) |
| 702 | ld 30, VCPU_GPRS_TM(30)(r31) |
| 703 | ld 31, VCPU_GPRS_TM(31)(r31) |
| 704 | |
| 705 | /* TM checkpointed state is now setup. All GPRs are now volatile. */ |
| 706 | TRECHKPT |
| 707 | |
| 708 | /* Now let's get back the state we need. */ |
| 709 | HMT_MEDIUM |
| 710 | GET_PACA(r13) |
| 711 | ld r29, HSTATE_DSCR(r13) |
| 712 | mtspr SPRN_DSCR, r29 |
| 713 | ld r4, HSTATE_KVM_VCPU(r13) |
| 714 | ld r1, HSTATE_HOST_R1(r13) |
| 715 | ld r2, PACATMSCRATCH(r13) |
| 716 | |
| 717 | /* Set the MSR RI since we have our registers back. */ |
| 718 | li r5, MSR_RI |
| 719 | mtmsrd r5, 1 |
| 720 | skip_tm: |
| 721 | #endif |
| 722 | |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 723 | /* Load guest PMU registers */ |
| 724 | /* R4 is live here (vcpu pointer) */ |
| 725 | li r3, 1 |
| 726 | sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */ |
| 727 | mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */ |
| 728 | isync |
| 729 | lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */ |
| 730 | lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */ |
| 731 | lwz r6, VCPU_PMC + 8(r4) |
| 732 | lwz r7, VCPU_PMC + 12(r4) |
| 733 | lwz r8, VCPU_PMC + 16(r4) |
| 734 | lwz r9, VCPU_PMC + 20(r4) |
| 735 | BEGIN_FTR_SECTION |
| 736 | lwz r10, VCPU_PMC + 24(r4) |
| 737 | lwz r11, VCPU_PMC + 28(r4) |
| 738 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) |
| 739 | mtspr SPRN_PMC1, r3 |
| 740 | mtspr SPRN_PMC2, r5 |
| 741 | mtspr SPRN_PMC3, r6 |
| 742 | mtspr SPRN_PMC4, r7 |
| 743 | mtspr SPRN_PMC5, r8 |
| 744 | mtspr SPRN_PMC6, r9 |
| 745 | BEGIN_FTR_SECTION |
| 746 | mtspr SPRN_PMC7, r10 |
| 747 | mtspr SPRN_PMC8, r11 |
| 748 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) |
| 749 | ld r3, VCPU_MMCR(r4) |
| 750 | ld r5, VCPU_MMCR + 8(r4) |
| 751 | ld r6, VCPU_MMCR + 16(r4) |
| 752 | ld r7, VCPU_SIAR(r4) |
| 753 | ld r8, VCPU_SDAR(r4) |
| 754 | mtspr SPRN_MMCR1, r5 |
| 755 | mtspr SPRN_MMCRA, r6 |
| 756 | mtspr SPRN_SIAR, r7 |
| 757 | mtspr SPRN_SDAR, r8 |
Michael Neuling | b005255e | 2014-01-08 21:25:21 +1100 | [diff] [blame] | 758 | BEGIN_FTR_SECTION |
| 759 | ld r5, VCPU_MMCR + 24(r4) |
| 760 | ld r6, VCPU_SIER(r4) |
| 761 | lwz r7, VCPU_PMC + 24(r4) |
| 762 | lwz r8, VCPU_PMC + 28(r4) |
| 763 | ld r9, VCPU_MMCR + 32(r4) |
| 764 | mtspr SPRN_MMCR2, r5 |
| 765 | mtspr SPRN_SIER, r6 |
| 766 | mtspr SPRN_SPMC1, r7 |
| 767 | mtspr SPRN_SPMC2, r8 |
| 768 | mtspr SPRN_MMCRS, r9 |
| 769 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 770 | mtspr SPRN_MMCR0, r3 |
| 771 | isync |
| 772 | |
| 773 | /* Load up FP, VMX and VSX registers */ |
| 774 | bl kvmppc_load_fp |
| 775 | |
| 776 | ld r14, VCPU_GPR(R14)(r4) |
| 777 | ld r15, VCPU_GPR(R15)(r4) |
| 778 | ld r16, VCPU_GPR(R16)(r4) |
| 779 | ld r17, VCPU_GPR(R17)(r4) |
| 780 | ld r18, VCPU_GPR(R18)(r4) |
| 781 | ld r19, VCPU_GPR(R19)(r4) |
| 782 | ld r20, VCPU_GPR(R20)(r4) |
| 783 | ld r21, VCPU_GPR(R21)(r4) |
| 784 | ld r22, VCPU_GPR(R22)(r4) |
| 785 | ld r23, VCPU_GPR(R23)(r4) |
| 786 | ld r24, VCPU_GPR(R24)(r4) |
| 787 | ld r25, VCPU_GPR(R25)(r4) |
| 788 | ld r26, VCPU_GPR(R26)(r4) |
| 789 | ld r27, VCPU_GPR(R27)(r4) |
| 790 | ld r28, VCPU_GPR(R28)(r4) |
| 791 | ld r29, VCPU_GPR(R29)(r4) |
| 792 | ld r30, VCPU_GPR(R30)(r4) |
| 793 | ld r31, VCPU_GPR(R31)(r4) |
| 794 | |
| 795 | BEGIN_FTR_SECTION |
| 796 | /* Switch DSCR to guest value */ |
| 797 | ld r5, VCPU_DSCR(r4) |
| 798 | mtspr SPRN_DSCR, r5 |
| 799 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
| 800 | |
Michael Neuling | b005255e | 2014-01-08 21:25:21 +1100 | [diff] [blame] | 801 | BEGIN_FTR_SECTION |
| 802 | /* Skip next section on POWER7 or PPC970 */ |
| 803 | b 8f |
| 804 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) |
| 805 | /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */ |
| 806 | mfmsr r8 |
| 807 | li r0, 1 |
| 808 | rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG |
| 809 | mtmsrd r8 |
| 810 | |
| 811 | /* Load up POWER8-specific registers */ |
| 812 | ld r5, VCPU_IAMR(r4) |
| 813 | lwz r6, VCPU_PSPB(r4) |
| 814 | ld r7, VCPU_FSCR(r4) |
| 815 | mtspr SPRN_IAMR, r5 |
| 816 | mtspr SPRN_PSPB, r6 |
| 817 | mtspr SPRN_FSCR, r7 |
| 818 | ld r5, VCPU_DAWR(r4) |
| 819 | ld r6, VCPU_DAWRX(r4) |
| 820 | ld r7, VCPU_CIABR(r4) |
| 821 | ld r8, VCPU_TAR(r4) |
| 822 | mtspr SPRN_DAWR, r5 |
| 823 | mtspr SPRN_DAWRX, r6 |
| 824 | mtspr SPRN_CIABR, r7 |
| 825 | mtspr SPRN_TAR, r8 |
| 826 | ld r5, VCPU_IC(r4) |
| 827 | ld r6, VCPU_VTB(r4) |
| 828 | mtspr SPRN_IC, r5 |
| 829 | mtspr SPRN_VTB, r6 |
Michael Neuling | 7b49041 | 2014-01-08 21:25:32 +1100 | [diff] [blame] | 830 | ld r8, VCPU_EBBHR(r4) |
Michael Neuling | b005255e | 2014-01-08 21:25:21 +1100 | [diff] [blame] | 831 | mtspr SPRN_EBBHR, r8 |
| 832 | ld r5, VCPU_EBBRR(r4) |
| 833 | ld r6, VCPU_BESCR(r4) |
| 834 | ld r7, VCPU_CSIGR(r4) |
| 835 | ld r8, VCPU_TACR(r4) |
| 836 | mtspr SPRN_EBBRR, r5 |
| 837 | mtspr SPRN_BESCR, r6 |
| 838 | mtspr SPRN_CSIGR, r7 |
| 839 | mtspr SPRN_TACR, r8 |
| 840 | ld r5, VCPU_TCSCR(r4) |
| 841 | ld r6, VCPU_ACOP(r4) |
| 842 | lwz r7, VCPU_GUEST_PID(r4) |
| 843 | ld r8, VCPU_WORT(r4) |
| 844 | mtspr SPRN_TCSCR, r5 |
| 845 | mtspr SPRN_ACOP, r6 |
| 846 | mtspr SPRN_PID, r7 |
| 847 | mtspr SPRN_WORT, r8 |
| 848 | 8: |
| 849 | |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 850 | /* |
| 851 | * Set the decrementer to the guest decrementer. |
| 852 | */ |
| 853 | ld r8,VCPU_DEC_EXPIRES(r4) |
Paul Mackerras | c5fb80d | 2014-03-25 10:47:07 +1100 | [diff] [blame] | 854 | /* r8 is a host timebase value here, convert to guest TB */ |
| 855 | ld r5,HSTATE_KVM_VCORE(r13) |
| 856 | ld r6,VCORE_TB_OFFSET(r5) |
| 857 | add r8,r8,r6 |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 858 | mftb r7 |
| 859 | subf r3,r7,r8 |
| 860 | mtspr SPRN_DEC,r3 |
| 861 | stw r3,VCPU_DEC(r4) |
| 862 | |
| 863 | ld r5, VCPU_SPRG0(r4) |
| 864 | ld r6, VCPU_SPRG1(r4) |
| 865 | ld r7, VCPU_SPRG2(r4) |
| 866 | ld r8, VCPU_SPRG3(r4) |
| 867 | mtspr SPRN_SPRG0, r5 |
| 868 | mtspr SPRN_SPRG1, r6 |
| 869 | mtspr SPRN_SPRG2, r7 |
| 870 | mtspr SPRN_SPRG3, r8 |
| 871 | |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 872 | /* Load up DAR and DSISR */ |
| 873 | ld r5, VCPU_DAR(r4) |
| 874 | lwz r6, VCPU_DSISR(r4) |
| 875 | mtspr SPRN_DAR, r5 |
| 876 | mtspr SPRN_DSISR, r6 |
| 877 | |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 878 | BEGIN_FTR_SECTION |
| 879 | /* Restore AMR and UAMOR, set AMOR to all 1s */ |
| 880 | ld r5,VCPU_AMR(r4) |
| 881 | ld r6,VCPU_UAMOR(r4) |
| 882 | li r7,-1 |
| 883 | mtspr SPRN_AMR,r5 |
| 884 | mtspr SPRN_UAMOR,r6 |
| 885 | mtspr SPRN_AMOR,r7 |
| 886 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 887 | |
| 888 | /* Restore state of CTRL run bit; assume 1 on entry */ |
| 889 | lwz r5,VCPU_CTRL(r4) |
| 890 | andi. r5,r5,1 |
| 891 | bne 4f |
| 892 | mfspr r6,SPRN_CTRLF |
| 893 | clrrdi r6,r6,1 |
| 894 | mtspr SPRN_CTRLT,r6 |
| 895 | 4: |
| 896 | ld r6, VCPU_CTR(r4) |
| 897 | lwz r7, VCPU_XER(r4) |
| 898 | |
| 899 | mtctr r6 |
| 900 | mtxer r7 |
| 901 | |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 902 | kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */ |
Paul Mackerras | 4619ac8 | 2013-04-17 20:31:41 +0000 | [diff] [blame] | 903 | ld r10, VCPU_PC(r4) |
| 904 | ld r11, VCPU_MSR(r4) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 905 | ld r6, VCPU_SRR0(r4) |
| 906 | ld r7, VCPU_SRR1(r4) |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 907 | mtspr SPRN_SRR0, r6 |
| 908 | mtspr SPRN_SRR1, r7 |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 909 | |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 910 | deliver_guest_interrupt: |
Paul Mackerras | 4619ac8 | 2013-04-17 20:31:41 +0000 | [diff] [blame] | 911 | /* r11 = vcpu->arch.msr & ~MSR_HV */ |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 912 | rldicl r11, r11, 63 - MSR_HV_LG, 1 |
| 913 | rotldi r11, r11, 1 + MSR_HV_LG |
| 914 | ori r11, r11, MSR_ME |
| 915 | |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 916 | /* Check if we can deliver an external or decrementer interrupt now */ |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 917 | ld r0, VCPU_PENDING_EXC(r4) |
| 918 | rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63 |
| 919 | cmpdi cr1, r0, 0 |
| 920 | andi. r8, r11, MSR_EE |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 921 | BEGIN_FTR_SECTION |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 922 | mfspr r8, SPRN_LPCR |
| 923 | /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */ |
| 924 | rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH |
| 925 | mtspr SPRN_LPCR, r8 |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 926 | isync |
| 927 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
| 928 | beq 5f |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 929 | li r0, BOOK3S_INTERRUPT_EXTERNAL |
| 930 | bne cr1, 12f |
| 931 | mfspr r0, SPRN_DEC |
| 932 | cmpwi r0, 0 |
| 933 | li r0, BOOK3S_INTERRUPT_DECREMENTER |
| 934 | bge 5f |
| 935 | |
| 936 | 12: mtspr SPRN_SRR0, r10 |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 937 | mr r10,r0 |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 938 | mtspr SPRN_SRR1, r11 |
Michael Neuling | e4e3812 | 2014-03-25 10:47:02 +1100 | [diff] [blame] | 939 | mr r9, r4 |
| 940 | bl kvmppc_msr_interrupt |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 941 | 5: |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 942 | |
Liu Ping Fan | 27025a6 | 2013-11-19 14:12:48 +0800 | [diff] [blame] | 943 | /* |
| 944 | * Required state: |
| 945 | * R4 = vcpu |
| 946 | * R10: value for HSRR0 |
| 947 | * R11: value for HSRR1 |
| 948 | * R13 = PACA |
| 949 | */ |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 950 | fast_guest_return: |
Paul Mackerras | 4619ac8 | 2013-04-17 20:31:41 +0000 | [diff] [blame] | 951 | li r0,0 |
| 952 | stb r0,VCPU_CEDED(r4) /* cancel cede */ |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 953 | mtspr SPRN_HSRR0,r10 |
| 954 | mtspr SPRN_HSRR1,r11 |
| 955 | |
| 956 | /* Activate guest mode, so faults get handled by KVM */ |
Paul Mackerras | 44a3add | 2013-10-04 21:45:04 +1000 | [diff] [blame] | 957 | li r9, KVM_GUEST_MODE_GUEST_HV |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 958 | stb r9, HSTATE_IN_GUEST(r13) |
| 959 | |
| 960 | /* Enter guest */ |
| 961 | |
Paul Mackerras | 0acb911 | 2013-02-04 18:10:51 +0000 | [diff] [blame] | 962 | BEGIN_FTR_SECTION |
| 963 | ld r5, VCPU_CFAR(r4) |
| 964 | mtspr SPRN_CFAR, r5 |
| 965 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) |
Paul Mackerras | 4b8473c | 2013-09-20 14:52:39 +1000 | [diff] [blame] | 966 | BEGIN_FTR_SECTION |
| 967 | ld r0, VCPU_PPR(r4) |
| 968 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) |
Paul Mackerras | 0acb911 | 2013-02-04 18:10:51 +0000 | [diff] [blame] | 969 | |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 970 | ld r5, VCPU_LR(r4) |
| 971 | lwz r6, VCPU_CR(r4) |
| 972 | mtlr r5 |
| 973 | mtcr r6 |
| 974 | |
Michael Neuling | c75df6f | 2012-06-25 13:33:10 +0000 | [diff] [blame] | 975 | ld r1, VCPU_GPR(R1)(r4) |
| 976 | ld r2, VCPU_GPR(R2)(r4) |
| 977 | ld r3, VCPU_GPR(R3)(r4) |
| 978 | ld r5, VCPU_GPR(R5)(r4) |
| 979 | ld r6, VCPU_GPR(R6)(r4) |
| 980 | ld r7, VCPU_GPR(R7)(r4) |
| 981 | ld r8, VCPU_GPR(R8)(r4) |
| 982 | ld r9, VCPU_GPR(R9)(r4) |
| 983 | ld r10, VCPU_GPR(R10)(r4) |
| 984 | ld r11, VCPU_GPR(R11)(r4) |
| 985 | ld r12, VCPU_GPR(R12)(r4) |
| 986 | ld r13, VCPU_GPR(R13)(r4) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 987 | |
Paul Mackerras | 4b8473c | 2013-09-20 14:52:39 +1000 | [diff] [blame] | 988 | BEGIN_FTR_SECTION |
| 989 | mtspr SPRN_PPR, r0 |
| 990 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) |
| 991 | ld r0, VCPU_GPR(R0)(r4) |
Michael Neuling | c75df6f | 2012-06-25 13:33:10 +0000 | [diff] [blame] | 992 | ld r4, VCPU_GPR(R4)(r4) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 993 | |
| 994 | hrfid |
| 995 | b . |
| 996 | |
| 997 | /****************************************************************************** |
| 998 | * * |
| 999 | * Exit code * |
| 1000 | * * |
| 1001 | *****************************************************************************/ |
| 1002 | |
| 1003 | /* |
| 1004 | * We come here from the first-level interrupt handlers. |
| 1005 | */ |
Aneesh Kumar K.V | dd96b2c | 2013-10-07 22:17:55 +0530 | [diff] [blame] | 1006 | .globl kvmppc_interrupt_hv |
| 1007 | kvmppc_interrupt_hv: |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1008 | /* |
| 1009 | * Register contents: |
| 1010 | * R12 = interrupt vector |
| 1011 | * R13 = PACA |
| 1012 | * guest CR, R12 saved in shadow VCPU SCRATCH1/0 |
| 1013 | * guest R13 saved in SPRN_SCRATCH0 |
| 1014 | */ |
Aneesh Kumar K.V | 36e7bb3 | 2013-11-11 19:29:47 +0530 | [diff] [blame] | 1015 | std r9, HSTATE_SCRATCH2(r13) |
Paul Mackerras | 44a3add | 2013-10-04 21:45:04 +1000 | [diff] [blame] | 1016 | |
| 1017 | lbz r9, HSTATE_IN_GUEST(r13) |
| 1018 | cmpwi r9, KVM_GUEST_MODE_HOST_HV |
| 1019 | beq kvmppc_bad_host_intr |
Aneesh Kumar K.V | dd96b2c | 2013-10-07 22:17:55 +0530 | [diff] [blame] | 1020 | #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE |
| 1021 | cmpwi r9, KVM_GUEST_MODE_GUEST |
Aneesh Kumar K.V | 36e7bb3 | 2013-11-11 19:29:47 +0530 | [diff] [blame] | 1022 | ld r9, HSTATE_SCRATCH2(r13) |
Aneesh Kumar K.V | dd96b2c | 2013-10-07 22:17:55 +0530 | [diff] [blame] | 1023 | beq kvmppc_interrupt_pr |
| 1024 | #endif |
Paul Mackerras | 44a3add | 2013-10-04 21:45:04 +1000 | [diff] [blame] | 1025 | /* We're now back in the host but in guest MMU context */ |
| 1026 | li r9, KVM_GUEST_MODE_HOST_HV |
| 1027 | stb r9, HSTATE_IN_GUEST(r13) |
| 1028 | |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1029 | ld r9, HSTATE_KVM_VCPU(r13) |
| 1030 | |
| 1031 | /* Save registers */ |
| 1032 | |
Michael Neuling | c75df6f | 2012-06-25 13:33:10 +0000 | [diff] [blame] | 1033 | std r0, VCPU_GPR(R0)(r9) |
| 1034 | std r1, VCPU_GPR(R1)(r9) |
| 1035 | std r2, VCPU_GPR(R2)(r9) |
| 1036 | std r3, VCPU_GPR(R3)(r9) |
| 1037 | std r4, VCPU_GPR(R4)(r9) |
| 1038 | std r5, VCPU_GPR(R5)(r9) |
| 1039 | std r6, VCPU_GPR(R6)(r9) |
| 1040 | std r7, VCPU_GPR(R7)(r9) |
| 1041 | std r8, VCPU_GPR(R8)(r9) |
Aneesh Kumar K.V | 36e7bb3 | 2013-11-11 19:29:47 +0530 | [diff] [blame] | 1042 | ld r0, HSTATE_SCRATCH2(r13) |
Michael Neuling | c75df6f | 2012-06-25 13:33:10 +0000 | [diff] [blame] | 1043 | std r0, VCPU_GPR(R9)(r9) |
| 1044 | std r10, VCPU_GPR(R10)(r9) |
| 1045 | std r11, VCPU_GPR(R11)(r9) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1046 | ld r3, HSTATE_SCRATCH0(r13) |
| 1047 | lwz r4, HSTATE_SCRATCH1(r13) |
Michael Neuling | c75df6f | 2012-06-25 13:33:10 +0000 | [diff] [blame] | 1048 | std r3, VCPU_GPR(R12)(r9) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1049 | stw r4, VCPU_CR(r9) |
Paul Mackerras | 0acb911 | 2013-02-04 18:10:51 +0000 | [diff] [blame] | 1050 | BEGIN_FTR_SECTION |
| 1051 | ld r3, HSTATE_CFAR(r13) |
| 1052 | std r3, VCPU_CFAR(r9) |
| 1053 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) |
Paul Mackerras | 4b8473c | 2013-09-20 14:52:39 +1000 | [diff] [blame] | 1054 | BEGIN_FTR_SECTION |
| 1055 | ld r4, HSTATE_PPR(r13) |
| 1056 | std r4, VCPU_PPR(r9) |
| 1057 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1058 | |
| 1059 | /* Restore R1/R2 so we can handle faults */ |
| 1060 | ld r1, HSTATE_HOST_R1(r13) |
| 1061 | ld r2, PACATOC(r13) |
| 1062 | |
| 1063 | mfspr r10, SPRN_SRR0 |
| 1064 | mfspr r11, SPRN_SRR1 |
| 1065 | std r10, VCPU_SRR0(r9) |
| 1066 | std r11, VCPU_SRR1(r9) |
| 1067 | andi. r0, r12, 2 /* need to read HSRR0/1? */ |
| 1068 | beq 1f |
| 1069 | mfspr r10, SPRN_HSRR0 |
| 1070 | mfspr r11, SPRN_HSRR1 |
| 1071 | clrrdi r12, r12, 2 |
| 1072 | 1: std r10, VCPU_PC(r9) |
| 1073 | std r11, VCPU_MSR(r9) |
| 1074 | |
| 1075 | GET_SCRATCH0(r3) |
| 1076 | mflr r4 |
Michael Neuling | c75df6f | 2012-06-25 13:33:10 +0000 | [diff] [blame] | 1077 | std r3, VCPU_GPR(R13)(r9) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1078 | std r4, VCPU_LR(r9) |
| 1079 | |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1080 | stw r12,VCPU_TRAP(r9) |
| 1081 | |
Paul Mackerras | 697d389 | 2011-12-12 12:36:37 +0000 | [diff] [blame] | 1082 | /* Save HEIR (HV emulation assist reg) in last_inst |
| 1083 | if this is an HEI (HV emulation interrupt, e40) */ |
| 1084 | li r3,KVM_INST_FETCH_FAILED |
| 1085 | BEGIN_FTR_SECTION |
| 1086 | cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST |
| 1087 | bne 11f |
| 1088 | mfspr r3,SPRN_HEIR |
| 1089 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
| 1090 | 11: stw r3,VCPU_LAST_INST(r9) |
| 1091 | |
| 1092 | /* these are volatile across C function calls */ |
| 1093 | mfctr r3 |
| 1094 | mfxer r4 |
| 1095 | std r3, VCPU_CTR(r9) |
| 1096 | stw r4, VCPU_XER(r9) |
| 1097 | |
| 1098 | BEGIN_FTR_SECTION |
| 1099 | /* If this is a page table miss then see if it's theirs or ours */ |
| 1100 | cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE |
| 1101 | beq kvmppc_hdsi |
Paul Mackerras | 342d3db | 2011-12-12 12:38:05 +0000 | [diff] [blame] | 1102 | cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE |
| 1103 | beq kvmppc_hisi |
Paul Mackerras | 697d389 | 2011-12-12 12:36:37 +0000 | [diff] [blame] | 1104 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
| 1105 | |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1106 | /* See if this is a leftover HDEC interrupt */ |
| 1107 | cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER |
| 1108 | bne 2f |
| 1109 | mfspr r3,SPRN_HDEC |
| 1110 | cmpwi r3,0 |
| 1111 | bge ignore_hdec |
| 1112 | 2: |
Paul Mackerras | 697d389 | 2011-12-12 12:36:37 +0000 | [diff] [blame] | 1113 | /* See if this is an hcall we can handle in real mode */ |
Paul Mackerras | a8606e2 | 2011-06-29 00:22:05 +0000 | [diff] [blame] | 1114 | cmpwi r12,BOOK3S_INTERRUPT_SYSCALL |
| 1115 | beq hcall_try_real_mode |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1116 | |
Benjamin Herrenschmidt | 54695c3 | 2013-04-17 20:30:50 +0000 | [diff] [blame] | 1117 | /* Only handle external interrupts here on arch 206 and later */ |
Paul Mackerras | 9e368f2 | 2011-06-29 00:40:08 +0000 | [diff] [blame] | 1118 | BEGIN_FTR_SECTION |
Benjamin Herrenschmidt | 54695c3 | 2013-04-17 20:30:50 +0000 | [diff] [blame] | 1119 | b ext_interrupt_to_host |
| 1120 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206) |
| 1121 | |
| 1122 | /* External interrupt ? */ |
| 1123 | cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL |
| 1124 | bne+ ext_interrupt_to_host |
| 1125 | |
| 1126 | /* External interrupt, first check for host_ipi. If this is |
| 1127 | * set, we know the host wants us out so let's do it now |
| 1128 | */ |
Paul Mackerras | c934243 | 2013-09-06 13:24:13 +1000 | [diff] [blame] | 1129 | bl kvmppc_read_intr |
| 1130 | cmpdi r3, 0 |
| 1131 | bgt ext_interrupt_to_host |
Benjamin Herrenschmidt | 54695c3 | 2013-04-17 20:30:50 +0000 | [diff] [blame] | 1132 | |
Paul Mackerras | 4619ac8 | 2013-04-17 20:31:41 +0000 | [diff] [blame] | 1133 | /* Check if any CPU is heading out to the host, if so head out too */ |
| 1134 | ld r5, HSTATE_KVM_VCORE(r13) |
| 1135 | lwz r0, VCORE_ENTRY_EXIT(r5) |
| 1136 | cmpwi r0, 0x100 |
| 1137 | bge ext_interrupt_to_host |
| 1138 | |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 1139 | /* Return to guest after delivering any pending interrupt */ |
| 1140 | mr r4, r9 |
| 1141 | b deliver_guest_interrupt |
Benjamin Herrenschmidt | 54695c3 | 2013-04-17 20:30:50 +0000 | [diff] [blame] | 1142 | |
Benjamin Herrenschmidt | 54695c3 | 2013-04-17 20:30:50 +0000 | [diff] [blame] | 1143 | ext_interrupt_to_host: |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1144 | |
Paul Mackerras | b4072df | 2012-11-23 22:37:50 +0000 | [diff] [blame] | 1145 | guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */ |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1146 | /* Save more register state */ |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1147 | mfdar r6 |
| 1148 | mfdsisr r7 |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1149 | std r6, VCPU_DAR(r9) |
| 1150 | stw r7, VCPU_DSISR(r9) |
Paul Mackerras | 9e368f2 | 2011-06-29 00:40:08 +0000 | [diff] [blame] | 1151 | BEGIN_FTR_SECTION |
Paul Mackerras | 697d389 | 2011-12-12 12:36:37 +0000 | [diff] [blame] | 1152 | /* don't overwrite fault_dar/fault_dsisr if HDSI */ |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1153 | cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE |
| 1154 | beq 6f |
Paul Mackerras | 9e368f2 | 2011-06-29 00:40:08 +0000 | [diff] [blame] | 1155 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
Paul Mackerras | 697d389 | 2011-12-12 12:36:37 +0000 | [diff] [blame] | 1156 | std r6, VCPU_FAULT_DAR(r9) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1157 | stw r7, VCPU_FAULT_DSISR(r9) |
| 1158 | |
Paul Mackerras | b4072df | 2012-11-23 22:37:50 +0000 | [diff] [blame] | 1159 | /* See if it is a machine check */ |
| 1160 | cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK |
| 1161 | beq machine_check_realmode |
| 1162 | mc_cont: |
| 1163 | |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1164 | /* Save guest CTRL register, set runlatch to 1 */ |
Paul Mackerras | 697d389 | 2011-12-12 12:36:37 +0000 | [diff] [blame] | 1165 | 6: mfspr r6,SPRN_CTRLF |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1166 | stw r6,VCPU_CTRL(r9) |
| 1167 | andi. r0,r6,1 |
| 1168 | bne 4f |
| 1169 | ori r6,r6,1 |
| 1170 | mtspr SPRN_CTRLT,r6 |
| 1171 | 4: |
| 1172 | /* Read the guest SLB and save it away */ |
| 1173 | lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */ |
| 1174 | mtctr r0 |
| 1175 | li r6,0 |
| 1176 | addi r7,r9,VCPU_SLB |
| 1177 | li r5,0 |
| 1178 | 1: slbmfee r8,r6 |
| 1179 | andis. r0,r8,SLB_ESID_V@h |
| 1180 | beq 2f |
| 1181 | add r8,r8,r6 /* put index in */ |
| 1182 | slbmfev r3,r6 |
| 1183 | std r8,VCPU_SLB_E(r7) |
| 1184 | std r3,VCPU_SLB_V(r7) |
| 1185 | addi r7,r7,VCPU_SLB_SIZE |
| 1186 | addi r5,r5,1 |
| 1187 | 2: addi r6,r6,1 |
| 1188 | bdnz 1b |
| 1189 | stw r5,VCPU_SLB_MAX(r9) |
| 1190 | |
| 1191 | /* |
| 1192 | * Save the guest PURR/SPURR |
| 1193 | */ |
Paul Mackerras | 9e368f2 | 2011-06-29 00:40:08 +0000 | [diff] [blame] | 1194 | BEGIN_FTR_SECTION |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1195 | mfspr r5,SPRN_PURR |
| 1196 | mfspr r6,SPRN_SPURR |
| 1197 | ld r7,VCPU_PURR(r9) |
| 1198 | ld r8,VCPU_SPURR(r9) |
| 1199 | std r5,VCPU_PURR(r9) |
| 1200 | std r6,VCPU_SPURR(r9) |
| 1201 | subf r5,r7,r5 |
| 1202 | subf r6,r8,r6 |
| 1203 | |
| 1204 | /* |
| 1205 | * Restore host PURR/SPURR and add guest times |
| 1206 | * so that the time in the guest gets accounted. |
| 1207 | */ |
| 1208 | ld r3,HSTATE_PURR(r13) |
| 1209 | ld r4,HSTATE_SPURR(r13) |
| 1210 | add r3,r3,r5 |
| 1211 | add r4,r4,r6 |
| 1212 | mtspr SPRN_PURR,r3 |
| 1213 | mtspr SPRN_SPURR,r4 |
Paul Mackerras | 9e368f2 | 2011-06-29 00:40:08 +0000 | [diff] [blame] | 1214 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1215 | |
Paul Mackerras | 93b0f4d | 2013-09-06 13:17:46 +1000 | [diff] [blame] | 1216 | /* Save DEC */ |
| 1217 | mfspr r5,SPRN_DEC |
| 1218 | mftb r6 |
| 1219 | extsw r5,r5 |
| 1220 | add r5,r5,r6 |
Paul Mackerras | c5fb80d | 2014-03-25 10:47:07 +1100 | [diff] [blame] | 1221 | /* r5 is a guest timebase value here, convert to host TB */ |
| 1222 | ld r3,HSTATE_KVM_VCORE(r13) |
| 1223 | ld r4,VCORE_TB_OFFSET(r3) |
| 1224 | subf r5,r4,r5 |
Paul Mackerras | 93b0f4d | 2013-09-06 13:17:46 +1000 | [diff] [blame] | 1225 | std r5,VCPU_DEC_EXPIRES(r9) |
| 1226 | |
Michael Neuling | b005255e | 2014-01-08 21:25:21 +1100 | [diff] [blame] | 1227 | BEGIN_FTR_SECTION |
| 1228 | b 8f |
| 1229 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) |
Michael Neuling | b005255e | 2014-01-08 21:25:21 +1100 | [diff] [blame] | 1230 | /* Save POWER8-specific registers */ |
| 1231 | mfspr r5, SPRN_IAMR |
| 1232 | mfspr r6, SPRN_PSPB |
| 1233 | mfspr r7, SPRN_FSCR |
| 1234 | std r5, VCPU_IAMR(r9) |
| 1235 | stw r6, VCPU_PSPB(r9) |
| 1236 | std r7, VCPU_FSCR(r9) |
| 1237 | mfspr r5, SPRN_IC |
| 1238 | mfspr r6, SPRN_VTB |
| 1239 | mfspr r7, SPRN_TAR |
| 1240 | std r5, VCPU_IC(r9) |
| 1241 | std r6, VCPU_VTB(r9) |
| 1242 | std r7, VCPU_TAR(r9) |
Michael Neuling | 7b49041 | 2014-01-08 21:25:32 +1100 | [diff] [blame] | 1243 | mfspr r8, SPRN_EBBHR |
Michael Neuling | b005255e | 2014-01-08 21:25:21 +1100 | [diff] [blame] | 1244 | std r8, VCPU_EBBHR(r9) |
| 1245 | mfspr r5, SPRN_EBBRR |
| 1246 | mfspr r6, SPRN_BESCR |
| 1247 | mfspr r7, SPRN_CSIGR |
| 1248 | mfspr r8, SPRN_TACR |
| 1249 | std r5, VCPU_EBBRR(r9) |
| 1250 | std r6, VCPU_BESCR(r9) |
| 1251 | std r7, VCPU_CSIGR(r9) |
| 1252 | std r8, VCPU_TACR(r9) |
| 1253 | mfspr r5, SPRN_TCSCR |
| 1254 | mfspr r6, SPRN_ACOP |
| 1255 | mfspr r7, SPRN_PID |
| 1256 | mfspr r8, SPRN_WORT |
| 1257 | std r5, VCPU_TCSCR(r9) |
| 1258 | std r6, VCPU_ACOP(r9) |
| 1259 | stw r7, VCPU_GUEST_PID(r9) |
| 1260 | std r8, VCPU_WORT(r9) |
| 1261 | 8: |
| 1262 | |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1263 | /* Save and reset AMR and UAMOR before turning on the MMU */ |
Paul Mackerras | 9e368f2 | 2011-06-29 00:40:08 +0000 | [diff] [blame] | 1264 | BEGIN_FTR_SECTION |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1265 | mfspr r5,SPRN_AMR |
| 1266 | mfspr r6,SPRN_UAMOR |
| 1267 | std r5,VCPU_AMR(r9) |
| 1268 | std r6,VCPU_UAMOR(r9) |
| 1269 | li r6,0 |
| 1270 | mtspr SPRN_AMR,r6 |
Paul Mackerras | 9e368f2 | 2011-06-29 00:40:08 +0000 | [diff] [blame] | 1271 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1272 | |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1273 | /* Switch DSCR back to host value */ |
Paul Mackerras | 9e368f2 | 2011-06-29 00:40:08 +0000 | [diff] [blame] | 1274 | BEGIN_FTR_SECTION |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1275 | mfspr r8, SPRN_DSCR |
| 1276 | ld r7, HSTATE_DSCR(r13) |
Paul Mackerras | cfc8602 | 2013-09-21 09:53:28 +1000 | [diff] [blame] | 1277 | std r8, VCPU_DSCR(r9) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1278 | mtspr SPRN_DSCR, r7 |
Paul Mackerras | 9e368f2 | 2011-06-29 00:40:08 +0000 | [diff] [blame] | 1279 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1280 | |
| 1281 | /* Save non-volatile GPRs */ |
Michael Neuling | c75df6f | 2012-06-25 13:33:10 +0000 | [diff] [blame] | 1282 | std r14, VCPU_GPR(R14)(r9) |
| 1283 | std r15, VCPU_GPR(R15)(r9) |
| 1284 | std r16, VCPU_GPR(R16)(r9) |
| 1285 | std r17, VCPU_GPR(R17)(r9) |
| 1286 | std r18, VCPU_GPR(R18)(r9) |
| 1287 | std r19, VCPU_GPR(R19)(r9) |
| 1288 | std r20, VCPU_GPR(R20)(r9) |
| 1289 | std r21, VCPU_GPR(R21)(r9) |
| 1290 | std r22, VCPU_GPR(R22)(r9) |
| 1291 | std r23, VCPU_GPR(R23)(r9) |
| 1292 | std r24, VCPU_GPR(R24)(r9) |
| 1293 | std r25, VCPU_GPR(R25)(r9) |
| 1294 | std r26, VCPU_GPR(R26)(r9) |
| 1295 | std r27, VCPU_GPR(R27)(r9) |
| 1296 | std r28, VCPU_GPR(R28)(r9) |
| 1297 | std r29, VCPU_GPR(R29)(r9) |
| 1298 | std r30, VCPU_GPR(R30)(r9) |
| 1299 | std r31, VCPU_GPR(R31)(r9) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1300 | |
| 1301 | /* Save SPRGs */ |
| 1302 | mfspr r3, SPRN_SPRG0 |
| 1303 | mfspr r4, SPRN_SPRG1 |
| 1304 | mfspr r5, SPRN_SPRG2 |
| 1305 | mfspr r6, SPRN_SPRG3 |
| 1306 | std r3, VCPU_SPRG0(r9) |
| 1307 | std r4, VCPU_SPRG1(r9) |
| 1308 | std r5, VCPU_SPRG2(r9) |
| 1309 | std r6, VCPU_SPRG3(r9) |
| 1310 | |
Paul Mackerras | 8943633 | 2012-03-02 01:38:23 +0000 | [diff] [blame] | 1311 | /* save FP state */ |
| 1312 | mr r3, r9 |
Paul Mackerras | 595e4f7 | 2013-10-15 20:43:04 +1100 | [diff] [blame] | 1313 | bl kvmppc_save_fp |
Paul Mackerras | 8943633 | 2012-03-02 01:38:23 +0000 | [diff] [blame] | 1314 | |
Paul Mackerras | 0a8ecce | 2014-04-14 08:56:26 +1000 | [diff] [blame] | 1315 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
| 1316 | BEGIN_FTR_SECTION |
| 1317 | b 2f |
| 1318 | END_FTR_SECTION_IFCLR(CPU_FTR_TM) |
| 1319 | /* Turn on TM. */ |
| 1320 | mfmsr r8 |
| 1321 | li r0, 1 |
| 1322 | rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG |
| 1323 | mtmsrd r8 |
| 1324 | |
| 1325 | ld r5, VCPU_MSR(r9) |
| 1326 | rldicl. r5, r5, 64 - MSR_TS_S_LG, 62 |
| 1327 | beq 1f /* TM not active in guest. */ |
| 1328 | |
| 1329 | li r3, TM_CAUSE_KVM_RESCHED |
| 1330 | |
| 1331 | /* Clear the MSR RI since r1, r13 are all going to be foobar. */ |
| 1332 | li r5, 0 |
| 1333 | mtmsrd r5, 1 |
| 1334 | |
| 1335 | /* All GPRs are volatile at this point. */ |
| 1336 | TRECLAIM(R3) |
| 1337 | |
| 1338 | /* Temporarily store r13 and r9 so we have some regs to play with */ |
| 1339 | SET_SCRATCH0(r13) |
| 1340 | GET_PACA(r13) |
| 1341 | std r9, PACATMSCRATCH(r13) |
| 1342 | ld r9, HSTATE_KVM_VCPU(r13) |
| 1343 | |
| 1344 | /* Get a few more GPRs free. */ |
| 1345 | std r29, VCPU_GPRS_TM(29)(r9) |
| 1346 | std r30, VCPU_GPRS_TM(30)(r9) |
| 1347 | std r31, VCPU_GPRS_TM(31)(r9) |
| 1348 | |
| 1349 | /* Save away PPR and DSCR soon so don't run with user values. */ |
| 1350 | mfspr r31, SPRN_PPR |
| 1351 | HMT_MEDIUM |
| 1352 | mfspr r30, SPRN_DSCR |
| 1353 | ld r29, HSTATE_DSCR(r13) |
| 1354 | mtspr SPRN_DSCR, r29 |
| 1355 | |
| 1356 | /* Save all but r9, r13 & r29-r31 */ |
| 1357 | reg = 0 |
| 1358 | .rept 29 |
| 1359 | .if (reg != 9) && (reg != 13) |
| 1360 | std reg, VCPU_GPRS_TM(reg)(r9) |
| 1361 | .endif |
| 1362 | reg = reg + 1 |
| 1363 | .endr |
| 1364 | /* ... now save r13 */ |
| 1365 | GET_SCRATCH0(r4) |
| 1366 | std r4, VCPU_GPRS_TM(13)(r9) |
| 1367 | /* ... and save r9 */ |
| 1368 | ld r4, PACATMSCRATCH(r13) |
| 1369 | std r4, VCPU_GPRS_TM(9)(r9) |
| 1370 | |
| 1371 | /* Reload stack pointer and TOC. */ |
| 1372 | ld r1, HSTATE_HOST_R1(r13) |
| 1373 | ld r2, PACATOC(r13) |
| 1374 | |
| 1375 | /* Set MSR RI now we have r1 and r13 back. */ |
| 1376 | li r5, MSR_RI |
| 1377 | mtmsrd r5, 1 |
| 1378 | |
| 1379 | /* Save away checkpinted SPRs. */ |
| 1380 | std r31, VCPU_PPR_TM(r9) |
| 1381 | std r30, VCPU_DSCR_TM(r9) |
| 1382 | mflr r5 |
| 1383 | mfcr r6 |
| 1384 | mfctr r7 |
| 1385 | mfspr r8, SPRN_AMR |
| 1386 | mfspr r10, SPRN_TAR |
| 1387 | std r5, VCPU_LR_TM(r9) |
| 1388 | stw r6, VCPU_CR_TM(r9) |
| 1389 | std r7, VCPU_CTR_TM(r9) |
| 1390 | std r8, VCPU_AMR_TM(r9) |
| 1391 | std r10, VCPU_TAR_TM(r9) |
| 1392 | |
| 1393 | /* Restore r12 as trap number. */ |
| 1394 | lwz r12, VCPU_TRAP(r9) |
| 1395 | |
| 1396 | /* Save FP/VSX. */ |
| 1397 | addi r3, r9, VCPU_FPRS_TM |
| 1398 | bl .store_fp_state |
| 1399 | addi r3, r9, VCPU_VRS_TM |
| 1400 | bl .store_vr_state |
| 1401 | mfspr r6, SPRN_VRSAVE |
| 1402 | stw r6, VCPU_VRSAVE_TM(r9) |
| 1403 | 1: |
| 1404 | /* |
| 1405 | * We need to save these SPRs after the treclaim so that the software |
| 1406 | * error code is recorded correctly in the TEXASR. Also the user may |
| 1407 | * change these outside of a transaction, so they must always be |
| 1408 | * context switched. |
| 1409 | */ |
| 1410 | mfspr r5, SPRN_TFHAR |
| 1411 | mfspr r6, SPRN_TFIAR |
| 1412 | mfspr r7, SPRN_TEXASR |
| 1413 | std r5, VCPU_TFHAR(r9) |
| 1414 | std r6, VCPU_TFIAR(r9) |
| 1415 | std r7, VCPU_TEXASR(r9) |
| 1416 | 2: |
| 1417 | #endif |
| 1418 | |
Paul Mackerras | a8606e2 | 2011-06-29 00:22:05 +0000 | [diff] [blame] | 1419 | /* Increment yield count if they have a VPA */ |
| 1420 | ld r8, VCPU_VPA(r9) /* do they have a VPA? */ |
| 1421 | cmpdi r8, 0 |
| 1422 | beq 25f |
| 1423 | lwz r3, LPPACA_YIELDCOUNT(r8) |
| 1424 | addi r3, r3, 1 |
| 1425 | stw r3, LPPACA_YIELDCOUNT(r8) |
Paul Mackerras | c35635e | 2013-04-18 19:51:04 +0000 | [diff] [blame] | 1426 | li r3, 1 |
| 1427 | stb r3, VCPU_VPA_DIRTY(r9) |
Paul Mackerras | a8606e2 | 2011-06-29 00:22:05 +0000 | [diff] [blame] | 1428 | 25: |
| 1429 | /* Save PMU registers if requested */ |
| 1430 | /* r8 and cr0.eq are live here */ |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1431 | li r3, 1 |
| 1432 | sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */ |
| 1433 | mfspr r4, SPRN_MMCR0 /* save MMCR0 */ |
| 1434 | mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */ |
Paul Mackerras | 8943633 | 2012-03-02 01:38:23 +0000 | [diff] [blame] | 1435 | mfspr r6, SPRN_MMCRA |
| 1436 | BEGIN_FTR_SECTION |
| 1437 | /* On P7, clear MMCRA in order to disable SDAR updates */ |
| 1438 | li r7, 0 |
| 1439 | mtspr SPRN_MMCRA, r7 |
| 1440 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1441 | isync |
Paul Mackerras | a8606e2 | 2011-06-29 00:22:05 +0000 | [diff] [blame] | 1442 | beq 21f /* if no VPA, save PMU stuff anyway */ |
| 1443 | lbz r7, LPPACA_PMCINUSE(r8) |
| 1444 | cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */ |
| 1445 | bne 21f |
| 1446 | std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */ |
| 1447 | b 22f |
| 1448 | 21: mfspr r5, SPRN_MMCR1 |
Paul Mackerras | 1494178 | 2013-09-06 13:11:18 +1000 | [diff] [blame] | 1449 | mfspr r7, SPRN_SIAR |
| 1450 | mfspr r8, SPRN_SDAR |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1451 | std r4, VCPU_MMCR(r9) |
| 1452 | std r5, VCPU_MMCR + 8(r9) |
| 1453 | std r6, VCPU_MMCR + 16(r9) |
Paul Mackerras | 1494178 | 2013-09-06 13:11:18 +1000 | [diff] [blame] | 1454 | std r7, VCPU_SIAR(r9) |
| 1455 | std r8, VCPU_SDAR(r9) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1456 | mfspr r3, SPRN_PMC1 |
| 1457 | mfspr r4, SPRN_PMC2 |
| 1458 | mfspr r5, SPRN_PMC3 |
| 1459 | mfspr r6, SPRN_PMC4 |
| 1460 | mfspr r7, SPRN_PMC5 |
| 1461 | mfspr r8, SPRN_PMC6 |
Paul Mackerras | 9e368f2 | 2011-06-29 00:40:08 +0000 | [diff] [blame] | 1462 | BEGIN_FTR_SECTION |
| 1463 | mfspr r10, SPRN_PMC7 |
| 1464 | mfspr r11, SPRN_PMC8 |
| 1465 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1466 | stw r3, VCPU_PMC(r9) |
| 1467 | stw r4, VCPU_PMC + 4(r9) |
| 1468 | stw r5, VCPU_PMC + 8(r9) |
| 1469 | stw r6, VCPU_PMC + 12(r9) |
| 1470 | stw r7, VCPU_PMC + 16(r9) |
| 1471 | stw r8, VCPU_PMC + 20(r9) |
Paul Mackerras | 9e368f2 | 2011-06-29 00:40:08 +0000 | [diff] [blame] | 1472 | BEGIN_FTR_SECTION |
| 1473 | stw r10, VCPU_PMC + 24(r9) |
| 1474 | stw r11, VCPU_PMC + 28(r9) |
| 1475 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) |
Michael Neuling | b005255e | 2014-01-08 21:25:21 +1100 | [diff] [blame] | 1476 | BEGIN_FTR_SECTION |
| 1477 | mfspr r4, SPRN_MMCR2 |
| 1478 | mfspr r5, SPRN_SIER |
| 1479 | mfspr r6, SPRN_SPMC1 |
| 1480 | mfspr r7, SPRN_SPMC2 |
| 1481 | mfspr r8, SPRN_MMCRS |
| 1482 | std r4, VCPU_MMCR + 24(r9) |
| 1483 | std r5, VCPU_SIER(r9) |
| 1484 | stw r6, VCPU_PMC + 24(r9) |
| 1485 | stw r7, VCPU_PMC + 28(r9) |
| 1486 | std r8, VCPU_MMCR + 32(r9) |
| 1487 | lis r4, 0x8000 |
| 1488 | mtspr SPRN_MMCRS, r4 |
| 1489 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1490 | 22: |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1491 | /* Clear out SLB */ |
| 1492 | li r5,0 |
| 1493 | slbmte r5,r5 |
| 1494 | slbia |
| 1495 | ptesync |
| 1496 | |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 1497 | hdec_soon: /* r12 = trap, r13 = paca */ |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1498 | BEGIN_FTR_SECTION |
| 1499 | b 32f |
| 1500 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) |
| 1501 | /* |
| 1502 | * POWER7 guest -> host partition switch code. |
| 1503 | * We don't have to lock against tlbies but we do |
| 1504 | * have to coordinate the hardware threads. |
| 1505 | */ |
| 1506 | /* Increment the threads-exiting-guest count in the 0xff00 |
| 1507 | bits of vcore->entry_exit_count */ |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1508 | ld r5,HSTATE_KVM_VCORE(r13) |
| 1509 | addi r6,r5,VCORE_ENTRY_EXIT |
| 1510 | 41: lwarx r3,0,r6 |
| 1511 | addi r0,r3,0x100 |
| 1512 | stwcx. r0,0,r6 |
| 1513 | bne 41b |
Paul Mackerras | f019b7a | 2013-11-16 17:46:03 +1100 | [diff] [blame] | 1514 | isync /* order stwcx. vs. reading napping_threads */ |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1515 | |
| 1516 | /* |
| 1517 | * At this point we have an interrupt that we have to pass |
| 1518 | * up to the kernel or qemu; we can't handle it in real mode. |
| 1519 | * Thus we have to do a partition switch, so we have to |
| 1520 | * collect the other threads, if we are the first thread |
| 1521 | * to take an interrupt. To do this, we set the HDEC to 0, |
| 1522 | * which causes an HDEC interrupt in all threads within 2ns |
| 1523 | * because the HDEC register is shared between all 4 threads. |
| 1524 | * However, we don't need to bother if this is an HDEC |
| 1525 | * interrupt, since the other threads will already be on their |
| 1526 | * way here in that case. |
| 1527 | */ |
| 1528 | cmpwi r3,0x100 /* Are we the first here? */ |
| 1529 | bge 43f |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1530 | cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER |
| 1531 | beq 40f |
| 1532 | li r0,0 |
| 1533 | mtspr SPRN_HDEC,r0 |
| 1534 | 40: |
| 1535 | /* |
| 1536 | * Send an IPI to any napping threads, since an HDEC interrupt |
| 1537 | * doesn't wake CPUs up from nap. |
| 1538 | */ |
| 1539 | lwz r3,VCORE_NAPPING_THREADS(r5) |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 1540 | lbz r4,HSTATE_PTID(r13) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1541 | li r0,1 |
| 1542 | sld r0,r0,r4 |
| 1543 | andc. r3,r3,r0 /* no sense IPI'ing ourselves */ |
| 1544 | beq 43f |
Paul Mackerras | f019b7a | 2013-11-16 17:46:03 +1100 | [diff] [blame] | 1545 | /* Order entry/exit update vs. IPIs */ |
| 1546 | sync |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1547 | mulli r4,r4,PACA_SIZE /* get paca for thread 0 */ |
| 1548 | subf r6,r4,r13 |
| 1549 | 42: andi. r0,r3,1 |
| 1550 | beq 44f |
| 1551 | ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */ |
| 1552 | li r0,IPI_PRIORITY |
| 1553 | li r7,XICS_MFRR |
| 1554 | stbcix r0,r7,r8 /* trigger the IPI */ |
| 1555 | 44: srdi. r3,r3,1 |
| 1556 | addi r6,r6,PACA_SIZE |
| 1557 | bne 42b |
| 1558 | |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 1559 | secondary_too_late: |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1560 | /* Secondary threads wait for primary to do partition switch */ |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 1561 | 43: ld r5,HSTATE_KVM_VCORE(r13) |
| 1562 | ld r4,VCORE_KVM(r5) /* pointer to struct kvm */ |
| 1563 | lbz r3,HSTATE_PTID(r13) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1564 | cmpwi r3,0 |
| 1565 | beq 15f |
| 1566 | HMT_LOW |
| 1567 | 13: lbz r3,VCORE_IN_GUEST(r5) |
| 1568 | cmpwi r3,0 |
| 1569 | bne 13b |
| 1570 | HMT_MEDIUM |
| 1571 | b 16f |
| 1572 | |
| 1573 | /* Primary thread waits for all the secondaries to exit guest */ |
| 1574 | 15: lwz r3,VCORE_ENTRY_EXIT(r5) |
| 1575 | srwi r0,r3,8 |
| 1576 | clrldi r3,r3,56 |
| 1577 | cmpw r3,r0 |
| 1578 | bne 15b |
| 1579 | isync |
| 1580 | |
| 1581 | /* Primary thread switches back to host partition */ |
| 1582 | ld r6,KVM_HOST_SDR1(r4) |
| 1583 | lwz r7,KVM_HOST_LPID(r4) |
| 1584 | li r8,LPID_RSVD /* switch to reserved LPID */ |
| 1585 | mtspr SPRN_LPID,r8 |
| 1586 | ptesync |
| 1587 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ |
| 1588 | mtspr SPRN_LPID,r7 |
| 1589 | isync |
| 1590 | |
Michael Neuling | b005255e | 2014-01-08 21:25:21 +1100 | [diff] [blame] | 1591 | BEGIN_FTR_SECTION |
| 1592 | /* DPDES is shared between threads */ |
| 1593 | mfspr r7, SPRN_DPDES |
| 1594 | std r7, VCORE_DPDES(r5) |
| 1595 | /* clear DPDES so we don't get guest doorbells in the host */ |
| 1596 | li r8, 0 |
| 1597 | mtspr SPRN_DPDES, r8 |
| 1598 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
| 1599 | |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1600 | /* Subtract timebase offset from timebase */ |
| 1601 | ld r8,VCORE_TB_OFFSET(r5) |
| 1602 | cmpdi r8,0 |
| 1603 | beq 17f |
Paul Mackerras | c5fb80d | 2014-03-25 10:47:07 +1100 | [diff] [blame] | 1604 | mftb r6 /* current guest timebase */ |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1605 | subf r8,r8,r6 |
| 1606 | mtspr SPRN_TBU40,r8 /* update upper 40 bits */ |
| 1607 | mftb r7 /* check if lower 24 bits overflowed */ |
| 1608 | clrldi r6,r6,40 |
| 1609 | clrldi r7,r7,40 |
| 1610 | cmpld r7,r6 |
| 1611 | bge 17f |
| 1612 | addis r8,r8,0x100 /* if so, increment upper 40 bits */ |
| 1613 | mtspr SPRN_TBU40,r8 |
| 1614 | |
| 1615 | /* Reset PCR */ |
| 1616 | 17: ld r0, VCORE_PCR(r5) |
| 1617 | cmpdi r0, 0 |
| 1618 | beq 18f |
| 1619 | li r0, 0 |
| 1620 | mtspr SPRN_PCR, r0 |
| 1621 | 18: |
| 1622 | /* Signal secondary CPUs to continue */ |
| 1623 | stb r0,VCORE_IN_GUEST(r5) |
| 1624 | lis r8,0x7fff /* MAX_INT@h */ |
| 1625 | mtspr SPRN_HDEC,r8 |
| 1626 | |
| 1627 | 16: ld r8,KVM_HOST_LPCR(r4) |
| 1628 | mtspr SPRN_LPCR,r8 |
| 1629 | isync |
| 1630 | b 33f |
| 1631 | |
| 1632 | /* |
| 1633 | * PPC970 guest -> host partition switch code. |
| 1634 | * We have to lock against concurrent tlbies, and |
| 1635 | * we have to flush the whole TLB. |
| 1636 | */ |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 1637 | 32: ld r5,HSTATE_KVM_VCORE(r13) |
| 1638 | ld r4,VCORE_KVM(r5) /* pointer to struct kvm */ |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1639 | |
| 1640 | /* Take the guest's tlbie_lock */ |
| 1641 | #ifdef __BIG_ENDIAN__ |
| 1642 | lwz r8,PACA_LOCK_TOKEN(r13) |
| 1643 | #else |
| 1644 | lwz r8,PACAPACAINDEX(r13) |
| 1645 | #endif |
| 1646 | addi r3,r4,KVM_TLBIE_LOCK |
| 1647 | 24: lwarx r0,0,r3 |
| 1648 | cmpwi r0,0 |
| 1649 | bne 24b |
| 1650 | stwcx. r8,0,r3 |
| 1651 | bne 24b |
| 1652 | isync |
| 1653 | |
| 1654 | ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */ |
| 1655 | li r0,0x18f |
| 1656 | rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */ |
| 1657 | or r0,r7,r0 |
| 1658 | ptesync |
| 1659 | sync |
| 1660 | mtspr SPRN_HID4,r0 /* switch to reserved LPID */ |
| 1661 | isync |
| 1662 | li r0,0 |
| 1663 | stw r0,0(r3) /* drop guest tlbie_lock */ |
| 1664 | |
| 1665 | /* invalidate the whole TLB */ |
| 1666 | li r0,256 |
| 1667 | mtctr r0 |
| 1668 | li r6,0 |
| 1669 | 25: tlbiel r6 |
| 1670 | addi r6,r6,0x1000 |
| 1671 | bdnz 25b |
| 1672 | ptesync |
| 1673 | |
| 1674 | /* take native_tlbie_lock */ |
| 1675 | ld r3,toc_tlbie_lock@toc(2) |
| 1676 | 24: lwarx r0,0,r3 |
| 1677 | cmpwi r0,0 |
| 1678 | bne 24b |
| 1679 | stwcx. r8,0,r3 |
| 1680 | bne 24b |
| 1681 | isync |
| 1682 | |
| 1683 | ld r6,KVM_HOST_SDR1(r4) |
| 1684 | mtspr SPRN_SDR1,r6 /* switch to host page table */ |
| 1685 | |
| 1686 | /* Set up host HID4 value */ |
| 1687 | sync |
| 1688 | mtspr SPRN_HID4,r7 |
| 1689 | isync |
| 1690 | li r0,0 |
| 1691 | stw r0,0(r3) /* drop native_tlbie_lock */ |
| 1692 | |
| 1693 | lis r8,0x7fff /* MAX_INT@h */ |
| 1694 | mtspr SPRN_HDEC,r8 |
| 1695 | |
| 1696 | /* Disable HDEC interrupts */ |
| 1697 | mfspr r0,SPRN_HID0 |
| 1698 | li r3,0 |
| 1699 | rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1 |
| 1700 | sync |
| 1701 | mtspr SPRN_HID0,r0 |
| 1702 | mfspr r0,SPRN_HID0 |
| 1703 | mfspr r0,SPRN_HID0 |
| 1704 | mfspr r0,SPRN_HID0 |
| 1705 | mfspr r0,SPRN_HID0 |
| 1706 | mfspr r0,SPRN_HID0 |
| 1707 | mfspr r0,SPRN_HID0 |
| 1708 | |
| 1709 | /* load host SLB entries */ |
| 1710 | 33: ld r8,PACA_SLBSHADOWPTR(r13) |
| 1711 | |
| 1712 | .rept SLB_NUM_BOLTED |
| 1713 | ld r5,SLBSHADOW_SAVEAREA(r8) |
| 1714 | ld r6,SLBSHADOW_SAVEAREA+8(r8) |
| 1715 | andis. r7,r5,SLB_ESID_V@h |
| 1716 | beq 1f |
| 1717 | slbmte r6,r5 |
| 1718 | 1: addi r8,r8,16 |
| 1719 | .endr |
| 1720 | |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1721 | /* Unset guest mode */ |
| 1722 | li r0, KVM_GUEST_MODE_NONE |
| 1723 | stb r0, HSTATE_IN_GUEST(r13) |
| 1724 | |
Paul Mackerras | 218309b | 2013-09-06 13:23:44 +1000 | [diff] [blame] | 1725 | ld r0, 112+PPC_LR_STKOFF(r1) |
| 1726 | addi r1, r1, 112 |
| 1727 | mtlr r0 |
| 1728 | blr |
Paul Mackerras | b4072df | 2012-11-23 22:37:50 +0000 | [diff] [blame] | 1729 | |
Paul Mackerras | 697d389 | 2011-12-12 12:36:37 +0000 | [diff] [blame] | 1730 | /* |
| 1731 | * Check whether an HDSI is an HPTE not found fault or something else. |
| 1732 | * If it is an HPTE not found fault that is due to the guest accessing |
| 1733 | * a page that they have mapped but which we have paged out, then |
| 1734 | * we continue on with the guest exit path. In all other cases, |
| 1735 | * reflect the HDSI to the guest as a DSI. |
| 1736 | */ |
| 1737 | kvmppc_hdsi: |
| 1738 | mfspr r4, SPRN_HDAR |
| 1739 | mfspr r6, SPRN_HDSISR |
Paul Mackerras | 4cf302b | 2011-12-12 12:38:51 +0000 | [diff] [blame] | 1740 | /* HPTE not found fault or protection fault? */ |
| 1741 | andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h |
Paul Mackerras | 697d389 | 2011-12-12 12:36:37 +0000 | [diff] [blame] | 1742 | beq 1f /* if not, send it to the guest */ |
| 1743 | andi. r0, r11, MSR_DR /* data relocation enabled? */ |
| 1744 | beq 3f |
| 1745 | clrrdi r0, r4, 28 |
Michael Neuling | c75df6f | 2012-06-25 13:33:10 +0000 | [diff] [blame] | 1746 | PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */ |
Paul Mackerras | 697d389 | 2011-12-12 12:36:37 +0000 | [diff] [blame] | 1747 | bne 1f /* if no SLB entry found */ |
| 1748 | 4: std r4, VCPU_FAULT_DAR(r9) |
| 1749 | stw r6, VCPU_FAULT_DSISR(r9) |
| 1750 | |
| 1751 | /* Search the hash table. */ |
| 1752 | mr r3, r9 /* vcpu pointer */ |
Paul Mackerras | 342d3db | 2011-12-12 12:38:05 +0000 | [diff] [blame] | 1753 | li r7, 1 /* data fault */ |
Paul Mackerras | 697d389 | 2011-12-12 12:36:37 +0000 | [diff] [blame] | 1754 | bl .kvmppc_hpte_hv_fault |
| 1755 | ld r9, HSTATE_KVM_VCPU(r13) |
| 1756 | ld r10, VCPU_PC(r9) |
| 1757 | ld r11, VCPU_MSR(r9) |
| 1758 | li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE |
| 1759 | cmpdi r3, 0 /* retry the instruction */ |
| 1760 | beq 6f |
| 1761 | cmpdi r3, -1 /* handle in kernel mode */ |
Paul Mackerras | b4072df | 2012-11-23 22:37:50 +0000 | [diff] [blame] | 1762 | beq guest_exit_cont |
Paul Mackerras | 697d389 | 2011-12-12 12:36:37 +0000 | [diff] [blame] | 1763 | cmpdi r3, -2 /* MMIO emulation; need instr word */ |
| 1764 | beq 2f |
| 1765 | |
| 1766 | /* Synthesize a DSI for the guest */ |
| 1767 | ld r4, VCPU_FAULT_DAR(r9) |
| 1768 | mr r6, r3 |
| 1769 | 1: mtspr SPRN_DAR, r4 |
| 1770 | mtspr SPRN_DSISR, r6 |
| 1771 | mtspr SPRN_SRR0, r10 |
| 1772 | mtspr SPRN_SRR1, r11 |
| 1773 | li r10, BOOK3S_INTERRUPT_DATA_STORAGE |
Michael Neuling | e4e3812 | 2014-03-25 10:47:02 +1100 | [diff] [blame] | 1774 | bl kvmppc_msr_interrupt |
Paul Mackerras | b4072df | 2012-11-23 22:37:50 +0000 | [diff] [blame] | 1775 | fast_interrupt_c_return: |
Paul Mackerras | 697d389 | 2011-12-12 12:36:37 +0000 | [diff] [blame] | 1776 | 6: ld r7, VCPU_CTR(r9) |
| 1777 | lwz r8, VCPU_XER(r9) |
| 1778 | mtctr r7 |
| 1779 | mtxer r8 |
| 1780 | mr r4, r9 |
| 1781 | b fast_guest_return |
| 1782 | |
| 1783 | 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */ |
| 1784 | ld r5, KVM_VRMA_SLB_V(r5) |
| 1785 | b 4b |
| 1786 | |
| 1787 | /* If this is for emulated MMIO, load the instruction word */ |
| 1788 | 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */ |
| 1789 | |
| 1790 | /* Set guest mode to 'jump over instruction' so if lwz faults |
| 1791 | * we'll just continue at the next IP. */ |
| 1792 | li r0, KVM_GUEST_MODE_SKIP |
| 1793 | stb r0, HSTATE_IN_GUEST(r13) |
| 1794 | |
| 1795 | /* Do the access with MSR:DR enabled */ |
| 1796 | mfmsr r3 |
| 1797 | ori r4, r3, MSR_DR /* Enable paging for data */ |
| 1798 | mtmsrd r4 |
| 1799 | lwz r8, 0(r10) |
| 1800 | mtmsrd r3 |
| 1801 | |
| 1802 | /* Store the result */ |
| 1803 | stw r8, VCPU_LAST_INST(r9) |
| 1804 | |
| 1805 | /* Unset guest mode. */ |
Paul Mackerras | 44a3add | 2013-10-04 21:45:04 +1000 | [diff] [blame] | 1806 | li r0, KVM_GUEST_MODE_HOST_HV |
Paul Mackerras | 697d389 | 2011-12-12 12:36:37 +0000 | [diff] [blame] | 1807 | stb r0, HSTATE_IN_GUEST(r13) |
Paul Mackerras | b4072df | 2012-11-23 22:37:50 +0000 | [diff] [blame] | 1808 | b guest_exit_cont |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1809 | |
Paul Mackerras | a8606e2 | 2011-06-29 00:22:05 +0000 | [diff] [blame] | 1810 | /* |
Paul Mackerras | 342d3db | 2011-12-12 12:38:05 +0000 | [diff] [blame] | 1811 | * Similarly for an HISI, reflect it to the guest as an ISI unless |
| 1812 | * it is an HPTE not found fault for a page that we have paged out. |
| 1813 | */ |
| 1814 | kvmppc_hisi: |
| 1815 | andis. r0, r11, SRR1_ISI_NOPT@h |
| 1816 | beq 1f |
| 1817 | andi. r0, r11, MSR_IR /* instruction relocation enabled? */ |
| 1818 | beq 3f |
| 1819 | clrrdi r0, r10, 28 |
Michael Neuling | c75df6f | 2012-06-25 13:33:10 +0000 | [diff] [blame] | 1820 | PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */ |
Paul Mackerras | 342d3db | 2011-12-12 12:38:05 +0000 | [diff] [blame] | 1821 | bne 1f /* if no SLB entry found */ |
| 1822 | 4: |
| 1823 | /* Search the hash table. */ |
| 1824 | mr r3, r9 /* vcpu pointer */ |
| 1825 | mr r4, r10 |
| 1826 | mr r6, r11 |
| 1827 | li r7, 0 /* instruction fault */ |
| 1828 | bl .kvmppc_hpte_hv_fault |
| 1829 | ld r9, HSTATE_KVM_VCPU(r13) |
| 1830 | ld r10, VCPU_PC(r9) |
| 1831 | ld r11, VCPU_MSR(r9) |
| 1832 | li r12, BOOK3S_INTERRUPT_H_INST_STORAGE |
| 1833 | cmpdi r3, 0 /* retry the instruction */ |
Paul Mackerras | b4072df | 2012-11-23 22:37:50 +0000 | [diff] [blame] | 1834 | beq fast_interrupt_c_return |
Paul Mackerras | 342d3db | 2011-12-12 12:38:05 +0000 | [diff] [blame] | 1835 | cmpdi r3, -1 /* handle in kernel mode */ |
Paul Mackerras | b4072df | 2012-11-23 22:37:50 +0000 | [diff] [blame] | 1836 | beq guest_exit_cont |
Paul Mackerras | 342d3db | 2011-12-12 12:38:05 +0000 | [diff] [blame] | 1837 | |
| 1838 | /* Synthesize an ISI for the guest */ |
| 1839 | mr r11, r3 |
| 1840 | 1: mtspr SPRN_SRR0, r10 |
| 1841 | mtspr SPRN_SRR1, r11 |
| 1842 | li r10, BOOK3S_INTERRUPT_INST_STORAGE |
Michael Neuling | e4e3812 | 2014-03-25 10:47:02 +1100 | [diff] [blame] | 1843 | bl kvmppc_msr_interrupt |
Paul Mackerras | b4072df | 2012-11-23 22:37:50 +0000 | [diff] [blame] | 1844 | b fast_interrupt_c_return |
Paul Mackerras | 342d3db | 2011-12-12 12:38:05 +0000 | [diff] [blame] | 1845 | |
| 1846 | 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */ |
| 1847 | ld r5, KVM_VRMA_SLB_V(r6) |
| 1848 | b 4b |
| 1849 | |
| 1850 | /* |
Paul Mackerras | a8606e2 | 2011-06-29 00:22:05 +0000 | [diff] [blame] | 1851 | * Try to handle an hcall in real mode. |
| 1852 | * Returns to the guest if we handle it, or continues on up to |
| 1853 | * the kernel if we can't (i.e. if we don't have a handler for |
| 1854 | * it, or if the handler returns H_TOO_HARD). |
| 1855 | */ |
| 1856 | .globl hcall_try_real_mode |
| 1857 | hcall_try_real_mode: |
Michael Neuling | c75df6f | 2012-06-25 13:33:10 +0000 | [diff] [blame] | 1858 | ld r3,VCPU_GPR(R3)(r9) |
Paul Mackerras | a8606e2 | 2011-06-29 00:22:05 +0000 | [diff] [blame] | 1859 | andi. r0,r11,MSR_PR |
Liu Ping Fan | 27025a6 | 2013-11-19 14:12:48 +0800 | [diff] [blame] | 1860 | /* sc 1 from userspace - reflect to guest syscall */ |
| 1861 | bne sc_1_fast_return |
Paul Mackerras | a8606e2 | 2011-06-29 00:22:05 +0000 | [diff] [blame] | 1862 | clrrdi r3,r3,2 |
| 1863 | cmpldi r3,hcall_real_table_end - hcall_real_table |
Paul Mackerras | b4072df | 2012-11-23 22:37:50 +0000 | [diff] [blame] | 1864 | bge guest_exit_cont |
Paul Mackerras | a8606e2 | 2011-06-29 00:22:05 +0000 | [diff] [blame] | 1865 | LOAD_REG_ADDR(r4, hcall_real_table) |
Paul Mackerras | 4baa1d8 | 2013-07-08 20:09:53 +1000 | [diff] [blame] | 1866 | lwax r3,r3,r4 |
Paul Mackerras | a8606e2 | 2011-06-29 00:22:05 +0000 | [diff] [blame] | 1867 | cmpwi r3,0 |
Paul Mackerras | b4072df | 2012-11-23 22:37:50 +0000 | [diff] [blame] | 1868 | beq guest_exit_cont |
Paul Mackerras | a8606e2 | 2011-06-29 00:22:05 +0000 | [diff] [blame] | 1869 | add r3,r3,r4 |
| 1870 | mtctr r3 |
| 1871 | mr r3,r9 /* get vcpu pointer */ |
Michael Neuling | c75df6f | 2012-06-25 13:33:10 +0000 | [diff] [blame] | 1872 | ld r4,VCPU_GPR(R4)(r9) |
Paul Mackerras | a8606e2 | 2011-06-29 00:22:05 +0000 | [diff] [blame] | 1873 | bctrl |
| 1874 | cmpdi r3,H_TOO_HARD |
| 1875 | beq hcall_real_fallback |
| 1876 | ld r4,HSTATE_KVM_VCPU(r13) |
Michael Neuling | c75df6f | 2012-06-25 13:33:10 +0000 | [diff] [blame] | 1877 | std r3,VCPU_GPR(R3)(r4) |
Paul Mackerras | a8606e2 | 2011-06-29 00:22:05 +0000 | [diff] [blame] | 1878 | ld r10,VCPU_PC(r4) |
| 1879 | ld r11,VCPU_MSR(r4) |
| 1880 | b fast_guest_return |
| 1881 | |
Liu Ping Fan | 27025a6 | 2013-11-19 14:12:48 +0800 | [diff] [blame] | 1882 | sc_1_fast_return: |
| 1883 | mtspr SPRN_SRR0,r10 |
| 1884 | mtspr SPRN_SRR1,r11 |
| 1885 | li r10, BOOK3S_INTERRUPT_SYSCALL |
Michael Neuling | e4e3812 | 2014-03-25 10:47:02 +1100 | [diff] [blame] | 1886 | bl kvmppc_msr_interrupt |
Liu Ping Fan | 27025a6 | 2013-11-19 14:12:48 +0800 | [diff] [blame] | 1887 | mr r4,r9 |
| 1888 | b fast_guest_return |
| 1889 | |
Paul Mackerras | a8606e2 | 2011-06-29 00:22:05 +0000 | [diff] [blame] | 1890 | /* We've attempted a real mode hcall, but it's punted it back |
| 1891 | * to userspace. We need to restore some clobbered volatiles |
| 1892 | * before resuming the pass-it-to-qemu path */ |
| 1893 | hcall_real_fallback: |
| 1894 | li r12,BOOK3S_INTERRUPT_SYSCALL |
| 1895 | ld r9, HSTATE_KVM_VCPU(r13) |
Paul Mackerras | a8606e2 | 2011-06-29 00:22:05 +0000 | [diff] [blame] | 1896 | |
Paul Mackerras | b4072df | 2012-11-23 22:37:50 +0000 | [diff] [blame] | 1897 | b guest_exit_cont |
Paul Mackerras | a8606e2 | 2011-06-29 00:22:05 +0000 | [diff] [blame] | 1898 | |
| 1899 | .globl hcall_real_table |
| 1900 | hcall_real_table: |
| 1901 | .long 0 /* 0 - unused */ |
| 1902 | .long .kvmppc_h_remove - hcall_real_table |
| 1903 | .long .kvmppc_h_enter - hcall_real_table |
| 1904 | .long .kvmppc_h_read - hcall_real_table |
| 1905 | .long 0 /* 0x10 - H_CLEAR_MOD */ |
| 1906 | .long 0 /* 0x14 - H_CLEAR_REF */ |
| 1907 | .long .kvmppc_h_protect - hcall_real_table |
Laurent Dufour | 69e9fbb2 | 2014-02-21 16:31:10 +0100 | [diff] [blame] | 1908 | .long .kvmppc_h_get_tce - hcall_real_table |
David Gibson | 54738c0 | 2011-06-29 00:22:41 +0000 | [diff] [blame] | 1909 | .long .kvmppc_h_put_tce - hcall_real_table |
Paul Mackerras | a8606e2 | 2011-06-29 00:22:05 +0000 | [diff] [blame] | 1910 | .long 0 /* 0x24 - H_SET_SPRG0 */ |
| 1911 | .long .kvmppc_h_set_dabr - hcall_real_table |
| 1912 | .long 0 /* 0x2c */ |
| 1913 | .long 0 /* 0x30 */ |
| 1914 | .long 0 /* 0x34 */ |
| 1915 | .long 0 /* 0x38 */ |
| 1916 | .long 0 /* 0x3c */ |
| 1917 | .long 0 /* 0x40 */ |
| 1918 | .long 0 /* 0x44 */ |
| 1919 | .long 0 /* 0x48 */ |
| 1920 | .long 0 /* 0x4c */ |
| 1921 | .long 0 /* 0x50 */ |
| 1922 | .long 0 /* 0x54 */ |
| 1923 | .long 0 /* 0x58 */ |
| 1924 | .long 0 /* 0x5c */ |
| 1925 | .long 0 /* 0x60 */ |
Benjamin Herrenschmidt | e7d26f2 | 2013-04-17 20:31:15 +0000 | [diff] [blame] | 1926 | #ifdef CONFIG_KVM_XICS |
| 1927 | .long .kvmppc_rm_h_eoi - hcall_real_table |
| 1928 | .long .kvmppc_rm_h_cppr - hcall_real_table |
| 1929 | .long .kvmppc_rm_h_ipi - hcall_real_table |
| 1930 | .long 0 /* 0x70 - H_IPOLL */ |
| 1931 | .long .kvmppc_rm_h_xirr - hcall_real_table |
| 1932 | #else |
| 1933 | .long 0 /* 0x64 - H_EOI */ |
| 1934 | .long 0 /* 0x68 - H_CPPR */ |
| 1935 | .long 0 /* 0x6c - H_IPI */ |
| 1936 | .long 0 /* 0x70 - H_IPOLL */ |
| 1937 | .long 0 /* 0x74 - H_XIRR */ |
| 1938 | #endif |
Paul Mackerras | a8606e2 | 2011-06-29 00:22:05 +0000 | [diff] [blame] | 1939 | .long 0 /* 0x78 */ |
| 1940 | .long 0 /* 0x7c */ |
| 1941 | .long 0 /* 0x80 */ |
| 1942 | .long 0 /* 0x84 */ |
| 1943 | .long 0 /* 0x88 */ |
| 1944 | .long 0 /* 0x8c */ |
| 1945 | .long 0 /* 0x90 */ |
| 1946 | .long 0 /* 0x94 */ |
| 1947 | .long 0 /* 0x98 */ |
| 1948 | .long 0 /* 0x9c */ |
| 1949 | .long 0 /* 0xa0 */ |
| 1950 | .long 0 /* 0xa4 */ |
| 1951 | .long 0 /* 0xa8 */ |
| 1952 | .long 0 /* 0xac */ |
| 1953 | .long 0 /* 0xb0 */ |
| 1954 | .long 0 /* 0xb4 */ |
| 1955 | .long 0 /* 0xb8 */ |
| 1956 | .long 0 /* 0xbc */ |
| 1957 | .long 0 /* 0xc0 */ |
| 1958 | .long 0 /* 0xc4 */ |
| 1959 | .long 0 /* 0xc8 */ |
| 1960 | .long 0 /* 0xcc */ |
| 1961 | .long 0 /* 0xd0 */ |
| 1962 | .long 0 /* 0xd4 */ |
| 1963 | .long 0 /* 0xd8 */ |
| 1964 | .long 0 /* 0xdc */ |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 1965 | .long .kvmppc_h_cede - hcall_real_table |
Paul Mackerras | a8606e2 | 2011-06-29 00:22:05 +0000 | [diff] [blame] | 1966 | .long 0 /* 0xe4 */ |
| 1967 | .long 0 /* 0xe8 */ |
| 1968 | .long 0 /* 0xec */ |
| 1969 | .long 0 /* 0xf0 */ |
| 1970 | .long 0 /* 0xf4 */ |
| 1971 | .long 0 /* 0xf8 */ |
| 1972 | .long 0 /* 0xfc */ |
| 1973 | .long 0 /* 0x100 */ |
| 1974 | .long 0 /* 0x104 */ |
| 1975 | .long 0 /* 0x108 */ |
| 1976 | .long 0 /* 0x10c */ |
| 1977 | .long 0 /* 0x110 */ |
| 1978 | .long 0 /* 0x114 */ |
| 1979 | .long 0 /* 0x118 */ |
| 1980 | .long 0 /* 0x11c */ |
| 1981 | .long 0 /* 0x120 */ |
| 1982 | .long .kvmppc_h_bulk_remove - hcall_real_table |
Paul Mackerras | 8563bf5 | 2014-01-08 21:25:29 +1100 | [diff] [blame] | 1983 | .long 0 /* 0x128 */ |
| 1984 | .long 0 /* 0x12c */ |
| 1985 | .long 0 /* 0x130 */ |
| 1986 | .long .kvmppc_h_set_xdabr - hcall_real_table |
Paul Mackerras | a8606e2 | 2011-06-29 00:22:05 +0000 | [diff] [blame] | 1987 | hcall_real_table_end: |
| 1988 | |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 1989 | ignore_hdec: |
| 1990 | mr r4,r9 |
| 1991 | b fast_guest_return |
| 1992 | |
Paul Mackerras | 8563bf5 | 2014-01-08 21:25:29 +1100 | [diff] [blame] | 1993 | _GLOBAL(kvmppc_h_set_xdabr) |
| 1994 | andi. r0, r5, DABRX_USER | DABRX_KERNEL |
| 1995 | beq 6f |
| 1996 | li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI |
| 1997 | andc. r0, r5, r0 |
| 1998 | beq 3f |
| 1999 | 6: li r3, H_PARAMETER |
| 2000 | blr |
| 2001 | |
Paul Mackerras | a8606e2 | 2011-06-29 00:22:05 +0000 | [diff] [blame] | 2002 | _GLOBAL(kvmppc_h_set_dabr) |
Paul Mackerras | 8563bf5 | 2014-01-08 21:25:29 +1100 | [diff] [blame] | 2003 | li r5, DABRX_USER | DABRX_KERNEL |
| 2004 | 3: |
Michael Neuling | eee7ff9 | 2014-01-08 21:25:19 +1100 | [diff] [blame] | 2005 | BEGIN_FTR_SECTION |
| 2006 | b 2f |
| 2007 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
Paul Mackerras | a8606e2 | 2011-06-29 00:22:05 +0000 | [diff] [blame] | 2008 | std r4,VCPU_DABR(r3) |
Paul Mackerras | 8563bf5 | 2014-01-08 21:25:29 +1100 | [diff] [blame] | 2009 | stw r5, VCPU_DABRX(r3) |
| 2010 | mtspr SPRN_DABRX, r5 |
Paul Mackerras | 8943633 | 2012-03-02 01:38:23 +0000 | [diff] [blame] | 2011 | /* Work around P7 bug where DABR can get corrupted on mtspr */ |
| 2012 | 1: mtspr SPRN_DABR,r4 |
| 2013 | mfspr r5, SPRN_DABR |
| 2014 | cmpd r4, r5 |
| 2015 | bne 1b |
| 2016 | isync |
Paul Mackerras | a8606e2 | 2011-06-29 00:22:05 +0000 | [diff] [blame] | 2017 | li r3,0 |
| 2018 | blr |
| 2019 | |
Paul Mackerras | 8563bf5 | 2014-01-08 21:25:29 +1100 | [diff] [blame] | 2020 | /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */ |
| 2021 | 2: rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW |
| 2022 | rlwimi r5, r4, 1, DAWRX_WT |
| 2023 | clrrdi r4, r4, 3 |
| 2024 | std r4, VCPU_DAWR(r3) |
| 2025 | std r5, VCPU_DAWRX(r3) |
| 2026 | mtspr SPRN_DAWR, r4 |
| 2027 | mtspr SPRN_DAWRX, r5 |
| 2028 | li r3, 0 |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 2029 | blr |
| 2030 | |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2031 | _GLOBAL(kvmppc_h_cede) |
| 2032 | ori r11,r11,MSR_EE |
| 2033 | std r11,VCPU_MSR(r3) |
| 2034 | li r0,1 |
| 2035 | stb r0,VCPU_CEDED(r3) |
| 2036 | sync /* order setting ceded vs. testing prodded */ |
| 2037 | lbz r5,VCPU_PRODDED(r3) |
| 2038 | cmpwi r5,0 |
Paul Mackerras | 04f995a | 2012-08-06 00:03:28 +0000 | [diff] [blame] | 2039 | bne kvm_cede_prodded |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2040 | li r0,0 /* set trap to 0 to say hcall is handled */ |
| 2041 | stw r0,VCPU_TRAP(r3) |
| 2042 | li r0,H_SUCCESS |
Michael Neuling | c75df6f | 2012-06-25 13:33:10 +0000 | [diff] [blame] | 2043 | std r0,VCPU_GPR(R3)(r3) |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2044 | BEGIN_FTR_SECTION |
Paul Mackerras | 04f995a | 2012-08-06 00:03:28 +0000 | [diff] [blame] | 2045 | b kvm_cede_exit /* just send it up to host on 970 */ |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2046 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206) |
| 2047 | |
| 2048 | /* |
| 2049 | * Set our bit in the bitmask of napping threads unless all the |
| 2050 | * other threads are already napping, in which case we send this |
| 2051 | * up to the host. |
| 2052 | */ |
| 2053 | ld r5,HSTATE_KVM_VCORE(r13) |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 2054 | lbz r6,HSTATE_PTID(r13) |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2055 | lwz r8,VCORE_ENTRY_EXIT(r5) |
| 2056 | clrldi r8,r8,56 |
| 2057 | li r0,1 |
| 2058 | sld r0,r0,r6 |
| 2059 | addi r6,r5,VCORE_NAPPING_THREADS |
| 2060 | 31: lwarx r4,0,r6 |
| 2061 | or r4,r4,r0 |
Michael Neuling | c75df6f | 2012-06-25 13:33:10 +0000 | [diff] [blame] | 2062 | PPC_POPCNTW(R7,R4) |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2063 | cmpw r7,r8 |
Paul Mackerras | 04f995a | 2012-08-06 00:03:28 +0000 | [diff] [blame] | 2064 | bge kvm_cede_exit |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2065 | stwcx. r4,0,r6 |
| 2066 | bne 31b |
Paul Mackerras | f019b7a | 2013-11-16 17:46:03 +1100 | [diff] [blame] | 2067 | /* order napping_threads update vs testing entry_exit_count */ |
| 2068 | isync |
Paul Mackerras | e0b7ec0 | 2014-01-08 21:25:20 +1100 | [diff] [blame] | 2069 | li r0,NAPPING_CEDE |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2070 | stb r0,HSTATE_NAPPING(r13) |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2071 | lwz r7,VCORE_ENTRY_EXIT(r5) |
| 2072 | cmpwi r7,0x100 |
| 2073 | bge 33f /* another thread already exiting */ |
| 2074 | |
| 2075 | /* |
| 2076 | * Although not specifically required by the architecture, POWER7 |
| 2077 | * preserves the following registers in nap mode, even if an SMT mode |
| 2078 | * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3, |
| 2079 | * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR. |
| 2080 | */ |
| 2081 | /* Save non-volatile GPRs */ |
Michael Neuling | c75df6f | 2012-06-25 13:33:10 +0000 | [diff] [blame] | 2082 | std r14, VCPU_GPR(R14)(r3) |
| 2083 | std r15, VCPU_GPR(R15)(r3) |
| 2084 | std r16, VCPU_GPR(R16)(r3) |
| 2085 | std r17, VCPU_GPR(R17)(r3) |
| 2086 | std r18, VCPU_GPR(R18)(r3) |
| 2087 | std r19, VCPU_GPR(R19)(r3) |
| 2088 | std r20, VCPU_GPR(R20)(r3) |
| 2089 | std r21, VCPU_GPR(R21)(r3) |
| 2090 | std r22, VCPU_GPR(R22)(r3) |
| 2091 | std r23, VCPU_GPR(R23)(r3) |
| 2092 | std r24, VCPU_GPR(R24)(r3) |
| 2093 | std r25, VCPU_GPR(R25)(r3) |
| 2094 | std r26, VCPU_GPR(R26)(r3) |
| 2095 | std r27, VCPU_GPR(R27)(r3) |
| 2096 | std r28, VCPU_GPR(R28)(r3) |
| 2097 | std r29, VCPU_GPR(R29)(r3) |
| 2098 | std r30, VCPU_GPR(R30)(r3) |
| 2099 | std r31, VCPU_GPR(R31)(r3) |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2100 | |
| 2101 | /* save FP state */ |
Paul Mackerras | 595e4f7 | 2013-10-15 20:43:04 +1100 | [diff] [blame] | 2102 | bl kvmppc_save_fp |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2103 | |
| 2104 | /* |
Paul Mackerras | aa31e84 | 2014-01-08 21:25:26 +1100 | [diff] [blame] | 2105 | * Take a nap until a decrementer or external or doobell interrupt |
| 2106 | * occurs, with PECE1, PECE0 and PECEDP set in LPCR |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2107 | */ |
Paul Mackerras | f0888f7 | 2012-02-03 00:54:17 +0000 | [diff] [blame] | 2108 | li r0,1 |
| 2109 | stb r0,HSTATE_HWTHREAD_REQ(r13) |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2110 | mfspr r5,SPRN_LPCR |
| 2111 | ori r5,r5,LPCR_PECE0 | LPCR_PECE1 |
Paul Mackerras | aa31e84 | 2014-01-08 21:25:26 +1100 | [diff] [blame] | 2112 | BEGIN_FTR_SECTION |
| 2113 | oris r5,r5,LPCR_PECEDP@h |
| 2114 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2115 | mtspr SPRN_LPCR,r5 |
| 2116 | isync |
| 2117 | li r0, 0 |
| 2118 | std r0, HSTATE_SCRATCH0(r13) |
| 2119 | ptesync |
| 2120 | ld r0, HSTATE_SCRATCH0(r13) |
| 2121 | 1: cmpd r0, r0 |
| 2122 | bne 1b |
| 2123 | nap |
| 2124 | b . |
| 2125 | |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 2126 | 33: mr r4, r3 |
| 2127 | li r3, 0 |
| 2128 | li r12, 0 |
| 2129 | b 34f |
| 2130 | |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2131 | kvm_end_cede: |
Paul Mackerras | 4619ac8 | 2013-04-17 20:31:41 +0000 | [diff] [blame] | 2132 | /* get vcpu pointer */ |
| 2133 | ld r4, HSTATE_KVM_VCPU(r13) |
| 2134 | |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2135 | /* Woken by external or decrementer interrupt */ |
| 2136 | ld r1, HSTATE_HOST_R1(r13) |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2137 | |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2138 | /* load up FP state */ |
| 2139 | bl kvmppc_load_fp |
| 2140 | |
| 2141 | /* Load NV GPRS */ |
Michael Neuling | c75df6f | 2012-06-25 13:33:10 +0000 | [diff] [blame] | 2142 | ld r14, VCPU_GPR(R14)(r4) |
| 2143 | ld r15, VCPU_GPR(R15)(r4) |
| 2144 | ld r16, VCPU_GPR(R16)(r4) |
| 2145 | ld r17, VCPU_GPR(R17)(r4) |
| 2146 | ld r18, VCPU_GPR(R18)(r4) |
| 2147 | ld r19, VCPU_GPR(R19)(r4) |
| 2148 | ld r20, VCPU_GPR(R20)(r4) |
| 2149 | ld r21, VCPU_GPR(R21)(r4) |
| 2150 | ld r22, VCPU_GPR(R22)(r4) |
| 2151 | ld r23, VCPU_GPR(R23)(r4) |
| 2152 | ld r24, VCPU_GPR(R24)(r4) |
| 2153 | ld r25, VCPU_GPR(R25)(r4) |
| 2154 | ld r26, VCPU_GPR(R26)(r4) |
| 2155 | ld r27, VCPU_GPR(R27)(r4) |
| 2156 | ld r28, VCPU_GPR(R28)(r4) |
| 2157 | ld r29, VCPU_GPR(R29)(r4) |
| 2158 | ld r30, VCPU_GPR(R30)(r4) |
| 2159 | ld r31, VCPU_GPR(R31)(r4) |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 2160 | |
| 2161 | /* Check the wake reason in SRR1 to see why we got here */ |
| 2162 | bl kvmppc_check_wake_reason |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2163 | |
| 2164 | /* clear our bit in vcore->napping_threads */ |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 2165 | 34: ld r5,HSTATE_KVM_VCORE(r13) |
| 2166 | lbz r7,HSTATE_PTID(r13) |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2167 | li r0,1 |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 2168 | sld r0,r0,r7 |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2169 | addi r6,r5,VCORE_NAPPING_THREADS |
| 2170 | 32: lwarx r7,0,r6 |
| 2171 | andc r7,r7,r0 |
| 2172 | stwcx. r7,0,r6 |
| 2173 | bne 32b |
| 2174 | li r0,0 |
| 2175 | stb r0,HSTATE_NAPPING(r13) |
| 2176 | |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 2177 | /* See if the wake reason means we need to exit */ |
| 2178 | stw r12, VCPU_TRAP(r4) |
Paul Mackerras | 4619ac8 | 2013-04-17 20:31:41 +0000 | [diff] [blame] | 2179 | mr r9, r4 |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 2180 | cmpdi r3, 0 |
| 2181 | bgt guest_exit_cont |
Paul Mackerras | 4619ac8 | 2013-04-17 20:31:41 +0000 | [diff] [blame] | 2182 | |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2183 | /* see if any other thread is already exiting */ |
| 2184 | lwz r0,VCORE_ENTRY_EXIT(r5) |
| 2185 | cmpwi r0,0x100 |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 2186 | bge guest_exit_cont |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2187 | |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 2188 | b kvmppc_cede_reentry /* if not go back to guest */ |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2189 | |
| 2190 | /* cede when already previously prodded case */ |
Paul Mackerras | 04f995a | 2012-08-06 00:03:28 +0000 | [diff] [blame] | 2191 | kvm_cede_prodded: |
| 2192 | li r0,0 |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2193 | stb r0,VCPU_PRODDED(r3) |
| 2194 | sync /* order testing prodded vs. clearing ceded */ |
| 2195 | stb r0,VCPU_CEDED(r3) |
| 2196 | li r3,H_SUCCESS |
| 2197 | blr |
| 2198 | |
| 2199 | /* we've ceded but we want to give control to the host */ |
Paul Mackerras | 04f995a | 2012-08-06 00:03:28 +0000 | [diff] [blame] | 2200 | kvm_cede_exit: |
Paul Mackerras | 4619ac8 | 2013-04-17 20:31:41 +0000 | [diff] [blame] | 2201 | b hcall_real_fallback |
Paul Mackerras | 19ccb76 | 2011-07-23 17:42:46 +1000 | [diff] [blame] | 2202 | |
Paul Mackerras | b4072df | 2012-11-23 22:37:50 +0000 | [diff] [blame] | 2203 | /* Try to handle a machine check in real mode */ |
| 2204 | machine_check_realmode: |
| 2205 | mr r3, r9 /* get vcpu pointer */ |
| 2206 | bl .kvmppc_realmode_machine_check |
| 2207 | nop |
| 2208 | cmpdi r3, 0 /* continue exiting from guest? */ |
| 2209 | ld r9, HSTATE_KVM_VCPU(r13) |
| 2210 | li r12, BOOK3S_INTERRUPT_MACHINE_CHECK |
| 2211 | beq mc_cont |
| 2212 | /* If not, deliver a machine check. SRR0/1 are already set */ |
| 2213 | li r10, BOOK3S_INTERRUPT_MACHINE_CHECK |
Michael Neuling | e4e3812 | 2014-03-25 10:47:02 +1100 | [diff] [blame] | 2214 | bl kvmppc_msr_interrupt |
Paul Mackerras | b4072df | 2012-11-23 22:37:50 +0000 | [diff] [blame] | 2215 | b fast_interrupt_c_return |
| 2216 | |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 2217 | /* |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 2218 | * Check the reason we woke from nap, and take appropriate action. |
| 2219 | * Returns: |
| 2220 | * 0 if nothing needs to be done |
| 2221 | * 1 if something happened that needs to be handled by the host |
| 2222 | * -1 if there was a guest wakeup (IPI) |
| 2223 | * |
| 2224 | * Also sets r12 to the interrupt vector for any interrupt that needs |
| 2225 | * to be handled now by the host (0x500 for external interrupt), or zero. |
| 2226 | */ |
| 2227 | kvmppc_check_wake_reason: |
| 2228 | mfspr r6, SPRN_SRR1 |
Paul Mackerras | aa31e84 | 2014-01-08 21:25:26 +1100 | [diff] [blame] | 2229 | BEGIN_FTR_SECTION |
| 2230 | rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */ |
| 2231 | FTR_SECTION_ELSE |
| 2232 | rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */ |
| 2233 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S) |
| 2234 | cmpwi r6, 8 /* was it an external interrupt? */ |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 2235 | li r12, BOOK3S_INTERRUPT_EXTERNAL |
| 2236 | beq kvmppc_read_intr /* if so, see what it was */ |
| 2237 | li r3, 0 |
| 2238 | li r12, 0 |
| 2239 | cmpwi r6, 6 /* was it the decrementer? */ |
| 2240 | beq 0f |
Paul Mackerras | aa31e84 | 2014-01-08 21:25:26 +1100 | [diff] [blame] | 2241 | BEGIN_FTR_SECTION |
| 2242 | cmpwi r6, 5 /* privileged doorbell? */ |
| 2243 | beq 0f |
Paul Mackerras | 5d00f66 | 2014-01-08 21:25:28 +1100 | [diff] [blame] | 2244 | cmpwi r6, 3 /* hypervisor doorbell? */ |
| 2245 | beq 3f |
Paul Mackerras | aa31e84 | 2014-01-08 21:25:26 +1100 | [diff] [blame] | 2246 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 2247 | li r3, 1 /* anything else, return 1 */ |
| 2248 | 0: blr |
| 2249 | |
Paul Mackerras | 5d00f66 | 2014-01-08 21:25:28 +1100 | [diff] [blame] | 2250 | /* hypervisor doorbell */ |
| 2251 | 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL |
| 2252 | li r3, 1 |
| 2253 | blr |
| 2254 | |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 2255 | /* |
Paul Mackerras | c934243 | 2013-09-06 13:24:13 +1000 | [diff] [blame] | 2256 | * Determine what sort of external interrupt is pending (if any). |
| 2257 | * Returns: |
| 2258 | * 0 if no interrupt is pending |
| 2259 | * 1 if an interrupt is pending that needs to be handled by the host |
| 2260 | * -1 if there was a guest wakeup IPI (which has now been cleared) |
| 2261 | */ |
| 2262 | kvmppc_read_intr: |
| 2263 | /* see if a host IPI is pending */ |
| 2264 | li r3, 1 |
| 2265 | lbz r0, HSTATE_HOST_IPI(r13) |
| 2266 | cmpwi r0, 0 |
| 2267 | bne 1f |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 2268 | |
Paul Mackerras | c934243 | 2013-09-06 13:24:13 +1000 | [diff] [blame] | 2269 | /* Now read the interrupt from the ICP */ |
| 2270 | ld r6, HSTATE_XICS_PHYS(r13) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 2271 | li r7, XICS_XIRR |
Paul Mackerras | c934243 | 2013-09-06 13:24:13 +1000 | [diff] [blame] | 2272 | cmpdi r6, 0 |
| 2273 | beq- 1f |
| 2274 | lwzcix r0, r6, r7 |
| 2275 | rlwinm. r3, r0, 0, 0xffffff |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 2276 | sync |
Paul Mackerras | c934243 | 2013-09-06 13:24:13 +1000 | [diff] [blame] | 2277 | beq 1f /* if nothing pending in the ICP */ |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 2278 | |
Paul Mackerras | c934243 | 2013-09-06 13:24:13 +1000 | [diff] [blame] | 2279 | /* We found something in the ICP... |
| 2280 | * |
| 2281 | * If it's not an IPI, stash it in the PACA and return to |
| 2282 | * the host, we don't (yet) handle directing real external |
| 2283 | * interrupts directly to the guest |
| 2284 | */ |
| 2285 | cmpwi r3, XICS_IPI /* if there is, is it an IPI? */ |
Paul Mackerras | c934243 | 2013-09-06 13:24:13 +1000 | [diff] [blame] | 2286 | bne 42f |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 2287 | |
Paul Mackerras | c934243 | 2013-09-06 13:24:13 +1000 | [diff] [blame] | 2288 | /* It's an IPI, clear the MFRR and EOI it */ |
| 2289 | li r3, 0xff |
| 2290 | li r8, XICS_MFRR |
| 2291 | stbcix r3, r6, r8 /* clear the IPI */ |
| 2292 | stwcix r0, r6, r7 /* EOI it */ |
| 2293 | sync |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 2294 | |
Paul Mackerras | c934243 | 2013-09-06 13:24:13 +1000 | [diff] [blame] | 2295 | /* We need to re-check host IPI now in case it got set in the |
| 2296 | * meantime. If it's clear, we bounce the interrupt to the |
| 2297 | * guest |
| 2298 | */ |
| 2299 | lbz r0, HSTATE_HOST_IPI(r13) |
| 2300 | cmpwi r0, 0 |
| 2301 | bne- 43f |
| 2302 | |
| 2303 | /* OK, it's an IPI for us */ |
| 2304 | li r3, -1 |
| 2305 | 1: blr |
| 2306 | |
| 2307 | 42: /* It's not an IPI and it's for the host, stash it in the PACA |
| 2308 | * before exit, it will be picked up by the host ICP driver |
| 2309 | */ |
| 2310 | stw r0, HSTATE_SAVED_XIRR(r13) |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 2311 | li r3, 1 |
Paul Mackerras | c934243 | 2013-09-06 13:24:13 +1000 | [diff] [blame] | 2312 | b 1b |
| 2313 | |
| 2314 | 43: /* We raced with the host, we need to resend that IPI, bummer */ |
| 2315 | li r0, IPI_PRIORITY |
| 2316 | stbcix r0, r6, r8 /* set the IPI */ |
| 2317 | sync |
Paul Mackerras | e3bbbbf | 2014-01-08 21:25:25 +1100 | [diff] [blame] | 2318 | li r3, 1 |
Paul Mackerras | c934243 | 2013-09-06 13:24:13 +1000 | [diff] [blame] | 2319 | b 1b |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 2320 | |
| 2321 | /* |
| 2322 | * Save away FP, VMX and VSX registers. |
| 2323 | * r3 = vcpu pointer |
Paul Mackerras | 595e4f7 | 2013-10-15 20:43:04 +1100 | [diff] [blame] | 2324 | * N.B. r30 and r31 are volatile across this function, |
| 2325 | * thus it is not callable from C. |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 2326 | */ |
Paul Mackerras | 595e4f7 | 2013-10-15 20:43:04 +1100 | [diff] [blame] | 2327 | kvmppc_save_fp: |
| 2328 | mflr r30 |
| 2329 | mr r31,r3 |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 2330 | mfmsr r5 |
| 2331 | ori r8,r5,MSR_FP |
| 2332 | #ifdef CONFIG_ALTIVEC |
| 2333 | BEGIN_FTR_SECTION |
| 2334 | oris r8,r8,MSR_VEC@h |
| 2335 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) |
| 2336 | #endif |
| 2337 | #ifdef CONFIG_VSX |
| 2338 | BEGIN_FTR_SECTION |
| 2339 | oris r8,r8,MSR_VSX@h |
| 2340 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) |
| 2341 | #endif |
| 2342 | mtmsrd r8 |
| 2343 | isync |
Paul Mackerras | 595e4f7 | 2013-10-15 20:43:04 +1100 | [diff] [blame] | 2344 | addi r3,r3,VCPU_FPRS |
| 2345 | bl .store_fp_state |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 2346 | #ifdef CONFIG_ALTIVEC |
| 2347 | BEGIN_FTR_SECTION |
Paul Mackerras | 595e4f7 | 2013-10-15 20:43:04 +1100 | [diff] [blame] | 2348 | addi r3,r31,VCPU_VRS |
| 2349 | bl .store_vr_state |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 2350 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) |
| 2351 | #endif |
| 2352 | mfspr r6,SPRN_VRSAVE |
Paul Mackerras | e724f08 | 2014-03-13 20:02:48 +1100 | [diff] [blame] | 2353 | stw r6,VCPU_VRSAVE(r31) |
Paul Mackerras | 595e4f7 | 2013-10-15 20:43:04 +1100 | [diff] [blame] | 2354 | mtlr r30 |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 2355 | blr |
| 2356 | |
| 2357 | /* |
| 2358 | * Load up FP, VMX and VSX registers |
| 2359 | * r4 = vcpu pointer |
Paul Mackerras | 595e4f7 | 2013-10-15 20:43:04 +1100 | [diff] [blame] | 2360 | * N.B. r30 and r31 are volatile across this function, |
| 2361 | * thus it is not callable from C. |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 2362 | */ |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 2363 | kvmppc_load_fp: |
Paul Mackerras | 595e4f7 | 2013-10-15 20:43:04 +1100 | [diff] [blame] | 2364 | mflr r30 |
| 2365 | mr r31,r4 |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 2366 | mfmsr r9 |
| 2367 | ori r8,r9,MSR_FP |
| 2368 | #ifdef CONFIG_ALTIVEC |
| 2369 | BEGIN_FTR_SECTION |
| 2370 | oris r8,r8,MSR_VEC@h |
| 2371 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) |
| 2372 | #endif |
| 2373 | #ifdef CONFIG_VSX |
| 2374 | BEGIN_FTR_SECTION |
| 2375 | oris r8,r8,MSR_VSX@h |
| 2376 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) |
| 2377 | #endif |
| 2378 | mtmsrd r8 |
| 2379 | isync |
Paul Mackerras | 595e4f7 | 2013-10-15 20:43:04 +1100 | [diff] [blame] | 2380 | addi r3,r4,VCPU_FPRS |
| 2381 | bl .load_fp_state |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 2382 | #ifdef CONFIG_ALTIVEC |
| 2383 | BEGIN_FTR_SECTION |
Paul Mackerras | 595e4f7 | 2013-10-15 20:43:04 +1100 | [diff] [blame] | 2384 | addi r3,r31,VCPU_VRS |
| 2385 | bl .load_vr_state |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 2386 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) |
| 2387 | #endif |
Paul Mackerras | e724f08 | 2014-03-13 20:02:48 +1100 | [diff] [blame] | 2388 | lwz r7,VCPU_VRSAVE(r31) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 2389 | mtspr SPRN_VRSAVE,r7 |
Paul Mackerras | 595e4f7 | 2013-10-15 20:43:04 +1100 | [diff] [blame] | 2390 | mtlr r30 |
| 2391 | mr r4,r31 |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 2392 | blr |
Paul Mackerras | 44a3add | 2013-10-04 21:45:04 +1000 | [diff] [blame] | 2393 | |
| 2394 | /* |
| 2395 | * We come here if we get any exception or interrupt while we are |
| 2396 | * executing host real mode code while in guest MMU context. |
| 2397 | * For now just spin, but we should do something better. |
| 2398 | */ |
| 2399 | kvmppc_bad_host_intr: |
| 2400 | b . |
Michael Neuling | e4e3812 | 2014-03-25 10:47:02 +1100 | [diff] [blame] | 2401 | |
| 2402 | /* |
| 2403 | * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken |
| 2404 | * from VCPU_INTR_MSR and is modified based on the required TM state changes. |
| 2405 | * r11 has the guest MSR value (in/out) |
| 2406 | * r9 has a vcpu pointer (in) |
| 2407 | * r0 is used as a scratch register |
| 2408 | */ |
| 2409 | kvmppc_msr_interrupt: |
| 2410 | rldicl r0, r11, 64 - MSR_TS_S_LG, 62 |
| 2411 | cmpwi r0, 2 /* Check if we are in transactional state.. */ |
| 2412 | ld r11, VCPU_INTR_MSR(r9) |
| 2413 | bne 1f |
| 2414 | /* ... if transactional, change to suspended */ |
| 2415 | li r0, 1 |
| 2416 | 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG |
| 2417 | blr |