Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1 | /* Realtek PCI-Express SD/MMC Card Interface driver |
| 2 | * |
Wei WANG | 6228218 | 2013-08-21 09:46:27 +0800 | [diff] [blame] | 3 | * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License as published by the |
| 7 | * Free Software Foundation; either version 2, or (at your option) any |
| 8 | * later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, but |
| 11 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 13 | * General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along |
| 16 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 17 | * |
| 18 | * Author: |
| 19 | * Wei WANG <wei_wang@realsil.com.cn> |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 20 | */ |
| 21 | |
| 22 | #include <linux/module.h> |
Wei WANG | 433e075 | 2012-11-20 11:24:44 +0800 | [diff] [blame] | 23 | #include <linux/slab.h> |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 24 | #include <linux/highmem.h> |
| 25 | #include <linux/delay.h> |
| 26 | #include <linux/platform_device.h> |
Micky Ching | 6291e71 | 2014-06-06 15:05:45 +0800 | [diff] [blame] | 27 | #include <linux/workqueue.h> |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 28 | #include <linux/mmc/host.h> |
| 29 | #include <linux/mmc/mmc.h> |
| 30 | #include <linux/mmc/sd.h> |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 31 | #include <linux/mmc/sdio.h> |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 32 | #include <linux/mmc/card.h> |
| 33 | #include <linux/mfd/rtsx_pci.h> |
| 34 | #include <asm/unaligned.h> |
| 35 | |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 36 | struct realtek_pci_sdmmc { |
| 37 | struct platform_device *pdev; |
| 38 | struct rtsx_pcr *pcr; |
| 39 | struct mmc_host *mmc; |
| 40 | struct mmc_request *mrq; |
Micky Ching | 6291e71 | 2014-06-06 15:05:45 +0800 | [diff] [blame] | 41 | struct workqueue_struct *workq; |
| 42 | #define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq" |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 43 | |
Micky Ching | 6291e71 | 2014-06-06 15:05:45 +0800 | [diff] [blame] | 44 | struct work_struct work; |
Micky Ching | 98fcc57 | 2014-04-29 09:54:54 +0800 | [diff] [blame] | 45 | struct mutex host_mutex; |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 46 | |
| 47 | u8 ssc_depth; |
| 48 | unsigned int clock; |
| 49 | bool vpclk; |
| 50 | bool double_clk; |
| 51 | bool eject; |
| 52 | bool initial_mode; |
Wei WANG | d88691b | 2013-03-08 15:05:57 +0800 | [diff] [blame] | 53 | int power_state; |
| 54 | #define SDMMC_POWER_ON 1 |
| 55 | #define SDMMC_POWER_OFF 0 |
Micky Ching | 6291e71 | 2014-06-06 15:05:45 +0800 | [diff] [blame] | 56 | |
| 57 | unsigned int sg_count; |
| 58 | s32 cookie; |
| 59 | unsigned int cookie_sg_count; |
| 60 | bool using_cookie; |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 61 | }; |
| 62 | |
| 63 | static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host) |
| 64 | { |
| 65 | return &(host->pdev->dev); |
| 66 | } |
| 67 | |
| 68 | static inline void sd_clear_error(struct realtek_pci_sdmmc *host) |
| 69 | { |
| 70 | rtsx_pci_write_register(host->pcr, CARD_STOP, |
| 71 | SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR); |
| 72 | } |
| 73 | |
| 74 | #ifdef DEBUG |
Micky Ching | 755987f9 | 2014-12-23 09:19:42 +0800 | [diff] [blame] | 75 | static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end) |
| 76 | { |
| 77 | u16 len = end - start + 1; |
| 78 | int i; |
| 79 | u8 data[8]; |
| 80 | |
| 81 | for (i = 0; i < len; i += 8) { |
| 82 | int j; |
| 83 | int n = min(8, len - i); |
| 84 | |
| 85 | memset(&data, 0, sizeof(data)); |
| 86 | for (j = 0; j < n; j++) |
| 87 | rtsx_pci_read_register(host->pcr, start + i + j, |
| 88 | data + j); |
| 89 | dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n", |
| 90 | start + i, n, data); |
| 91 | } |
| 92 | } |
| 93 | |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 94 | static void sd_print_debug_regs(struct realtek_pci_sdmmc *host) |
| 95 | { |
Micky Ching | 755987f9 | 2014-12-23 09:19:42 +0800 | [diff] [blame] | 96 | dump_reg_range(host, 0xFDA0, 0xFDB3); |
| 97 | dump_reg_range(host, 0xFD52, 0xFD69); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 98 | } |
| 99 | #else |
| 100 | #define sd_print_debug_regs(host) |
| 101 | #endif /* DEBUG */ |
| 102 | |
Micky Ching | b22217f | 2015-01-14 11:09:11 +0800 | [diff] [blame^] | 103 | static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host) |
| 104 | { |
| 105 | return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST; |
| 106 | } |
| 107 | |
Micky Ching | 2d48e5f | 2014-12-23 09:19:44 +0800 | [diff] [blame] | 108 | static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd) |
| 109 | { |
| 110 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, |
| 111 | SD_CMD_START | cmd->opcode); |
| 112 | rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg); |
| 113 | } |
| 114 | |
| 115 | static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz) |
| 116 | { |
| 117 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks); |
| 118 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8); |
| 119 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz); |
| 120 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8); |
| 121 | } |
| 122 | |
| 123 | static int sd_response_type(struct mmc_command *cmd) |
| 124 | { |
| 125 | switch (mmc_resp_type(cmd)) { |
| 126 | case MMC_RSP_NONE: |
| 127 | return SD_RSP_TYPE_R0; |
| 128 | case MMC_RSP_R1: |
| 129 | return SD_RSP_TYPE_R1; |
| 130 | case MMC_RSP_R1 & ~MMC_RSP_CRC: |
| 131 | return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7; |
| 132 | case MMC_RSP_R1B: |
| 133 | return SD_RSP_TYPE_R1b; |
| 134 | case MMC_RSP_R2: |
| 135 | return SD_RSP_TYPE_R2; |
| 136 | case MMC_RSP_R3: |
| 137 | return SD_RSP_TYPE_R3; |
| 138 | default: |
| 139 | return -EINVAL; |
| 140 | } |
| 141 | } |
| 142 | |
| 143 | static int sd_status_index(int resp_type) |
| 144 | { |
| 145 | if (resp_type == SD_RSP_TYPE_R0) |
| 146 | return 0; |
| 147 | else if (resp_type == SD_RSP_TYPE_R2) |
| 148 | return 16; |
| 149 | |
| 150 | return 5; |
| 151 | } |
Micky Ching | 6291e71 | 2014-06-06 15:05:45 +0800 | [diff] [blame] | 152 | /* |
| 153 | * sd_pre_dma_transfer - do dma_map_sg() or using cookie |
| 154 | * |
| 155 | * @pre: if called in pre_req() |
| 156 | * return: |
| 157 | * 0 - do dma_map_sg() |
| 158 | * 1 - using cookie |
| 159 | */ |
| 160 | static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host, |
| 161 | struct mmc_data *data, bool pre) |
| 162 | { |
| 163 | struct rtsx_pcr *pcr = host->pcr; |
| 164 | int read = data->flags & MMC_DATA_READ; |
| 165 | int count = 0; |
| 166 | int using_cookie = 0; |
| 167 | |
| 168 | if (!pre && data->host_cookie && data->host_cookie != host->cookie) { |
| 169 | dev_err(sdmmc_dev(host), |
| 170 | "error: data->host_cookie = %d, host->cookie = %d\n", |
| 171 | data->host_cookie, host->cookie); |
| 172 | data->host_cookie = 0; |
| 173 | } |
| 174 | |
| 175 | if (pre || data->host_cookie != host->cookie) { |
| 176 | count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read); |
| 177 | } else { |
| 178 | count = host->cookie_sg_count; |
| 179 | using_cookie = 1; |
| 180 | } |
| 181 | |
| 182 | if (pre) { |
| 183 | host->cookie_sg_count = count; |
| 184 | if (++host->cookie < 0) |
| 185 | host->cookie = 1; |
| 186 | data->host_cookie = host->cookie; |
| 187 | } else { |
| 188 | host->sg_count = count; |
| 189 | } |
| 190 | |
| 191 | return using_cookie; |
| 192 | } |
| 193 | |
| 194 | static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, |
| 195 | bool is_first_req) |
| 196 | { |
| 197 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); |
| 198 | struct mmc_data *data = mrq->data; |
| 199 | |
| 200 | if (data->host_cookie) { |
| 201 | dev_err(sdmmc_dev(host), |
| 202 | "error: reset data->host_cookie = %d\n", |
| 203 | data->host_cookie); |
| 204 | data->host_cookie = 0; |
| 205 | } |
| 206 | |
| 207 | sd_pre_dma_transfer(host, data, true); |
| 208 | dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count); |
| 209 | } |
| 210 | |
| 211 | static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, |
| 212 | int err) |
| 213 | { |
| 214 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); |
| 215 | struct rtsx_pcr *pcr = host->pcr; |
| 216 | struct mmc_data *data = mrq->data; |
| 217 | int read = data->flags & MMC_DATA_READ; |
| 218 | |
| 219 | rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read); |
| 220 | data->host_cookie = 0; |
| 221 | } |
| 222 | |
Micky Ching | 98fcc57 | 2014-04-29 09:54:54 +0800 | [diff] [blame] | 223 | static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host, |
| 224 | struct mmc_command *cmd) |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 225 | { |
| 226 | struct rtsx_pcr *pcr = host->pcr; |
| 227 | u8 cmd_idx = (u8)cmd->opcode; |
| 228 | u32 arg = cmd->arg; |
| 229 | int err = 0; |
| 230 | int timeout = 100; |
| 231 | int i; |
Micky Ching | 98fcc57 | 2014-04-29 09:54:54 +0800 | [diff] [blame] | 232 | u8 *ptr; |
Micky Ching | 2d48e5f | 2014-12-23 09:19:44 +0800 | [diff] [blame] | 233 | int rsp_type; |
| 234 | int stat_idx; |
Micky Ching | 98fcc57 | 2014-04-29 09:54:54 +0800 | [diff] [blame] | 235 | bool clock_toggled = false; |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 236 | |
| 237 | dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", |
| 238 | __func__, cmd_idx, arg); |
| 239 | |
Micky Ching | 2d48e5f | 2014-12-23 09:19:44 +0800 | [diff] [blame] | 240 | rsp_type = sd_response_type(cmd); |
| 241 | if (rsp_type < 0) |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 242 | goto out; |
Micky Ching | 2d48e5f | 2014-12-23 09:19:44 +0800 | [diff] [blame] | 243 | |
| 244 | stat_idx = sd_status_index(rsp_type); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 245 | |
| 246 | if (rsp_type == SD_RSP_TYPE_R1b) |
| 247 | timeout = 3000; |
| 248 | |
| 249 | if (cmd->opcode == SD_SWITCH_VOLTAGE) { |
| 250 | err = rtsx_pci_write_register(pcr, SD_BUS_STAT, |
| 251 | 0xFF, SD_CLK_TOGGLE_EN); |
| 252 | if (err < 0) |
| 253 | goto out; |
Micky Ching | 98fcc57 | 2014-04-29 09:54:54 +0800 | [diff] [blame] | 254 | |
| 255 | clock_toggled = true; |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 256 | } |
| 257 | |
| 258 | rtsx_pci_init_cmd(pcr); |
Micky Ching | 2d48e5f | 2014-12-23 09:19:44 +0800 | [diff] [blame] | 259 | sd_cmd_set_sd_cmd(pcr, cmd); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 260 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type); |
| 261 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, |
| 262 | 0x01, PINGPONG_BUFFER); |
| 263 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, |
| 264 | 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); |
| 265 | rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, |
| 266 | SD_TRANSFER_END | SD_STAT_IDLE, |
| 267 | SD_TRANSFER_END | SD_STAT_IDLE); |
| 268 | |
| 269 | if (rsp_type == SD_RSP_TYPE_R2) { |
| 270 | /* Read data from ping-pong buffer */ |
| 271 | for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++) |
| 272 | rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 273 | } else if (rsp_type != SD_RSP_TYPE_R0) { |
| 274 | /* Read data from SD_CMDx registers */ |
| 275 | for (i = SD_CMD0; i <= SD_CMD4; i++) |
| 276 | rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 277 | } |
| 278 | |
| 279 | rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0); |
| 280 | |
Micky Ching | 98fcc57 | 2014-04-29 09:54:54 +0800 | [diff] [blame] | 281 | err = rtsx_pci_send_cmd(pcr, timeout); |
| 282 | if (err < 0) { |
| 283 | sd_print_debug_regs(host); |
| 284 | sd_clear_error(host); |
| 285 | dev_dbg(sdmmc_dev(host), |
| 286 | "rtsx_pci_send_cmd error (err = %d)\n", err); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 287 | goto out; |
| 288 | } |
| 289 | |
| 290 | if (rsp_type == SD_RSP_TYPE_R0) { |
| 291 | err = 0; |
| 292 | goto out; |
| 293 | } |
| 294 | |
| 295 | /* Eliminate returned value of CHECK_REG_CMD */ |
| 296 | ptr = rtsx_pci_get_cmd_data(pcr) + 1; |
| 297 | |
| 298 | /* Check (Start,Transmission) bit of Response */ |
| 299 | if ((ptr[0] & 0xC0) != 0) { |
| 300 | err = -EILSEQ; |
| 301 | dev_dbg(sdmmc_dev(host), "Invalid response bit\n"); |
| 302 | goto out; |
| 303 | } |
| 304 | |
| 305 | /* Check CRC7 */ |
| 306 | if (!(rsp_type & SD_NO_CHECK_CRC7)) { |
| 307 | if (ptr[stat_idx] & SD_CRC7_ERR) { |
| 308 | err = -EILSEQ; |
| 309 | dev_dbg(sdmmc_dev(host), "CRC7 error\n"); |
| 310 | goto out; |
| 311 | } |
| 312 | } |
| 313 | |
| 314 | if (rsp_type == SD_RSP_TYPE_R2) { |
Roger Tseng | d1419d5 | 2014-08-15 14:06:00 +0800 | [diff] [blame] | 315 | /* |
| 316 | * The controller offloads the last byte {CRC-7, end bit 1'b1} |
| 317 | * of response type R2. Assign dummy CRC, 0, and end bit to the |
| 318 | * byte(ptr[16], goes into the LSB of resp[3] later). |
| 319 | */ |
| 320 | ptr[16] = 1; |
| 321 | |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 322 | for (i = 0; i < 4; i++) { |
| 323 | cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4); |
| 324 | dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n", |
| 325 | i, cmd->resp[i]); |
| 326 | } |
| 327 | } else { |
| 328 | cmd->resp[0] = get_unaligned_be32(ptr + 1); |
| 329 | dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n", |
| 330 | cmd->resp[0]); |
| 331 | } |
| 332 | |
| 333 | out: |
| 334 | cmd->error = err; |
Wei WANG | 1b8055b | 2013-08-21 09:46:26 +0800 | [diff] [blame] | 335 | |
Micky Ching | 98fcc57 | 2014-04-29 09:54:54 +0800 | [diff] [blame] | 336 | if (err && clock_toggled) |
| 337 | rtsx_pci_write_register(pcr, SD_BUS_STAT, |
| 338 | SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 339 | } |
| 340 | |
Micky Ching | 56d1c0d | 2014-12-23 09:19:46 +0800 | [diff] [blame] | 341 | static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd, |
| 342 | u16 byte_cnt, u8 *buf, int buf_len, int timeout) |
| 343 | { |
| 344 | struct rtsx_pcr *pcr = host->pcr; |
| 345 | int err; |
| 346 | u8 trans_mode; |
| 347 | |
| 348 | dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", |
| 349 | __func__, cmd->opcode, cmd->arg); |
| 350 | |
| 351 | if (!buf) |
| 352 | buf_len = 0; |
| 353 | |
| 354 | if (cmd->opcode == MMC_SEND_TUNING_BLOCK) |
| 355 | trans_mode = SD_TM_AUTO_TUNING; |
| 356 | else |
| 357 | trans_mode = SD_TM_NORMAL_READ; |
| 358 | |
| 359 | rtsx_pci_init_cmd(pcr); |
| 360 | sd_cmd_set_sd_cmd(pcr, cmd); |
| 361 | sd_cmd_set_data_len(pcr, 1, byte_cnt); |
| 362 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, |
| 363 | SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | |
| 364 | SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); |
| 365 | if (trans_mode != SD_TM_AUTO_TUNING) |
| 366 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, |
| 367 | CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); |
| 368 | |
| 369 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, |
| 370 | 0xFF, trans_mode | SD_TRANSFER_START); |
| 371 | rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, |
| 372 | SD_TRANSFER_END, SD_TRANSFER_END); |
| 373 | |
| 374 | err = rtsx_pci_send_cmd(pcr, timeout); |
| 375 | if (err < 0) { |
| 376 | sd_print_debug_regs(host); |
| 377 | dev_dbg(sdmmc_dev(host), |
| 378 | "rtsx_pci_send_cmd fail (err = %d)\n", err); |
| 379 | return err; |
| 380 | } |
| 381 | |
| 382 | if (buf && buf_len) { |
| 383 | err = rtsx_pci_read_ppbuf(pcr, buf, buf_len); |
| 384 | if (err < 0) { |
| 385 | dev_dbg(sdmmc_dev(host), |
| 386 | "rtsx_pci_read_ppbuf fail (err = %d)\n", err); |
| 387 | return err; |
| 388 | } |
| 389 | } |
| 390 | |
| 391 | return 0; |
| 392 | } |
| 393 | |
| 394 | static int sd_write_data(struct realtek_pci_sdmmc *host, |
| 395 | struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len, |
| 396 | int timeout) |
| 397 | { |
| 398 | struct rtsx_pcr *pcr = host->pcr; |
| 399 | int err; |
| 400 | |
| 401 | dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", |
| 402 | __func__, cmd->opcode, cmd->arg); |
| 403 | |
| 404 | if (!buf) |
| 405 | buf_len = 0; |
| 406 | |
| 407 | sd_send_cmd_get_rsp(host, cmd); |
| 408 | if (cmd->error) |
| 409 | return cmd->error; |
| 410 | |
| 411 | if (buf && buf_len) { |
| 412 | err = rtsx_pci_write_ppbuf(pcr, buf, buf_len); |
| 413 | if (err < 0) { |
| 414 | dev_dbg(sdmmc_dev(host), |
| 415 | "rtsx_pci_write_ppbuf fail (err = %d)\n", err); |
| 416 | return err; |
| 417 | } |
| 418 | } |
| 419 | |
| 420 | rtsx_pci_init_cmd(pcr); |
| 421 | sd_cmd_set_data_len(pcr, 1, byte_cnt); |
| 422 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, |
| 423 | SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | |
| 424 | SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0); |
| 425 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, |
| 426 | SD_TRANSFER_START | SD_TM_AUTO_WRITE_3); |
| 427 | rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, |
| 428 | SD_TRANSFER_END, SD_TRANSFER_END); |
| 429 | |
| 430 | err = rtsx_pci_send_cmd(pcr, timeout); |
| 431 | if (err < 0) { |
| 432 | sd_print_debug_regs(host); |
| 433 | dev_dbg(sdmmc_dev(host), |
| 434 | "rtsx_pci_send_cmd fail (err = %d)\n", err); |
| 435 | return err; |
| 436 | } |
| 437 | |
| 438 | return 0; |
| 439 | } |
| 440 | |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 441 | static int sd_read_long_data(struct realtek_pci_sdmmc *host, |
| 442 | struct mmc_request *mrq) |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 443 | { |
| 444 | struct rtsx_pcr *pcr = host->pcr; |
| 445 | struct mmc_host *mmc = host->mmc; |
| 446 | struct mmc_card *card = mmc->card; |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 447 | struct mmc_command *cmd = mrq->cmd; |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 448 | struct mmc_data *data = mrq->data; |
Jackey Shen | 71ef1ea | 2013-05-17 17:17:43 +0800 | [diff] [blame] | 449 | int uhs = mmc_card_uhs(card); |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 450 | u8 cfg2 = 0; |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 451 | int err; |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 452 | int resp_type; |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 453 | size_t data_len = data->blksz * data->blocks; |
| 454 | |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 455 | dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", |
| 456 | __func__, cmd->opcode, cmd->arg); |
| 457 | |
| 458 | resp_type = sd_response_type(cmd); |
| 459 | if (resp_type < 0) |
| 460 | return resp_type; |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 461 | |
| 462 | if (!uhs) |
| 463 | cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; |
| 464 | |
| 465 | rtsx_pci_init_cmd(pcr); |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 466 | sd_cmd_set_sd_cmd(pcr, cmd); |
| 467 | sd_cmd_set_data_len(pcr, data->blocks, data->blksz); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 468 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, |
| 469 | DMA_DONE_INT, DMA_DONE_INT); |
| 470 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 471 | 0xFF, (u8)(data_len >> 24)); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 472 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 473 | 0xFF, (u8)(data_len >> 16)); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 474 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 475 | 0xFF, (u8)(data_len >> 8)); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 476 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 477 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, |
| 478 | 0x03 | DMA_PACK_SIZE_MASK, |
| 479 | DMA_DIR_FROM_CARD | DMA_EN | DMA_512); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 480 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, |
| 481 | 0x01, RING_BUFFER); |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 482 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 483 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 484 | SD_TRANSFER_START | SD_TM_AUTO_READ_2); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 485 | rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, |
| 486 | SD_TRANSFER_END, SD_TRANSFER_END); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 487 | rtsx_pci_send_cmd_no_wait(pcr); |
| 488 | |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 489 | err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000); |
| 490 | if (err < 0) { |
| 491 | sd_print_debug_regs(host); |
| 492 | sd_clear_error(host); |
| 493 | return err; |
| 494 | } |
| 495 | |
| 496 | return 0; |
| 497 | } |
| 498 | |
| 499 | static int sd_write_long_data(struct realtek_pci_sdmmc *host, |
| 500 | struct mmc_request *mrq) |
| 501 | { |
| 502 | struct rtsx_pcr *pcr = host->pcr; |
| 503 | struct mmc_host *mmc = host->mmc; |
| 504 | struct mmc_card *card = mmc->card; |
| 505 | struct mmc_command *cmd = mrq->cmd; |
| 506 | struct mmc_data *data = mrq->data; |
| 507 | int uhs = mmc_card_uhs(card); |
| 508 | u8 cfg2; |
| 509 | int err; |
| 510 | size_t data_len = data->blksz * data->blocks; |
| 511 | |
| 512 | sd_send_cmd_get_rsp(host, cmd); |
| 513 | if (cmd->error) |
| 514 | return cmd->error; |
| 515 | |
| 516 | dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", |
| 517 | __func__, cmd->opcode, cmd->arg); |
| 518 | |
| 519 | cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | |
| 520 | SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0; |
| 521 | |
| 522 | if (!uhs) |
| 523 | cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; |
| 524 | |
| 525 | rtsx_pci_init_cmd(pcr); |
| 526 | sd_cmd_set_data_len(pcr, data->blocks, data->blksz); |
| 527 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, |
| 528 | DMA_DONE_INT, DMA_DONE_INT); |
| 529 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, |
| 530 | 0xFF, (u8)(data_len >> 24)); |
| 531 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, |
| 532 | 0xFF, (u8)(data_len >> 16)); |
| 533 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, |
| 534 | 0xFF, (u8)(data_len >> 8)); |
| 535 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); |
| 536 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, |
| 537 | 0x03 | DMA_PACK_SIZE_MASK, |
| 538 | DMA_DIR_TO_CARD | DMA_EN | DMA_512); |
| 539 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, |
| 540 | 0x01, RING_BUFFER); |
| 541 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2); |
| 542 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, |
| 543 | SD_TRANSFER_START | SD_TM_AUTO_WRITE_3); |
| 544 | rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, |
| 545 | SD_TRANSFER_END, SD_TRANSFER_END); |
| 546 | rtsx_pci_send_cmd_no_wait(pcr); |
| 547 | err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 548 | if (err < 0) { |
Micky Ching | 98fcc57 | 2014-04-29 09:54:54 +0800 | [diff] [blame] | 549 | sd_clear_error(host); |
| 550 | return err; |
Micky Ching | c42deff | 2014-02-17 16:45:48 +0800 | [diff] [blame] | 551 | } |
Micky Ching | 98fcc57 | 2014-04-29 09:54:54 +0800 | [diff] [blame] | 552 | |
Micky Ching | c42deff | 2014-02-17 16:45:48 +0800 | [diff] [blame] | 553 | return 0; |
| 554 | } |
| 555 | |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 556 | static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq) |
| 557 | { |
| 558 | struct mmc_data *data = mrq->data; |
| 559 | |
| 560 | if (data->flags & MMC_DATA_READ) |
| 561 | return sd_read_long_data(host, mrq); |
| 562 | |
| 563 | return sd_write_long_data(host, mrq); |
| 564 | } |
| 565 | |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 566 | static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host) |
| 567 | { |
| 568 | rtsx_pci_write_register(host->pcr, SD_CFG1, |
| 569 | SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128); |
| 570 | } |
| 571 | |
| 572 | static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host) |
| 573 | { |
| 574 | rtsx_pci_write_register(host->pcr, SD_CFG1, |
| 575 | SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0); |
| 576 | } |
| 577 | |
| 578 | static void sd_normal_rw(struct realtek_pci_sdmmc *host, |
| 579 | struct mmc_request *mrq) |
| 580 | { |
| 581 | struct mmc_command *cmd = mrq->cmd; |
| 582 | struct mmc_data *data = mrq->data; |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 583 | u8 *buf; |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 584 | |
| 585 | buf = kzalloc(data->blksz, GFP_NOIO); |
| 586 | if (!buf) { |
| 587 | cmd->error = -ENOMEM; |
| 588 | return; |
| 589 | } |
| 590 | |
| 591 | if (data->flags & MMC_DATA_READ) { |
| 592 | if (host->initial_mode) |
| 593 | sd_disable_initial_mode(host); |
| 594 | |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 595 | cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf, |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 596 | data->blksz, 200); |
| 597 | |
| 598 | if (host->initial_mode) |
| 599 | sd_enable_initial_mode(host); |
| 600 | |
| 601 | sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz); |
| 602 | } else { |
| 603 | sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz); |
| 604 | |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 605 | cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf, |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 606 | data->blksz, 200); |
| 607 | } |
| 608 | |
| 609 | kfree(buf); |
| 610 | } |
| 611 | |
Wei WANG | 84d72f9 | 2013-08-21 09:46:25 +0800 | [diff] [blame] | 612 | static int sd_change_phase(struct realtek_pci_sdmmc *host, |
| 613 | u8 sample_point, bool rx) |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 614 | { |
| 615 | struct rtsx_pcr *pcr = host->pcr; |
| 616 | int err; |
| 617 | |
Wei WANG | 84d72f9 | 2013-08-21 09:46:25 +0800 | [diff] [blame] | 618 | dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n", |
| 619 | __func__, rx ? "RX" : "TX", sample_point); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 620 | |
| 621 | rtsx_pci_init_cmd(pcr); |
| 622 | |
| 623 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK); |
Wei WANG | 84d72f9 | 2013-08-21 09:46:25 +0800 | [diff] [blame] | 624 | if (rx) |
| 625 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, |
| 626 | SD_VPRX_CTL, 0x1F, sample_point); |
| 627 | else |
| 628 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, |
| 629 | SD_VPTX_CTL, 0x1F, sample_point); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 630 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); |
| 631 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, |
| 632 | PHASE_NOT_RESET, PHASE_NOT_RESET); |
| 633 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0); |
| 634 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); |
| 635 | |
| 636 | err = rtsx_pci_send_cmd(pcr, 100); |
| 637 | if (err < 0) |
| 638 | return err; |
| 639 | |
| 640 | return 0; |
| 641 | } |
| 642 | |
Micky Ching | abcc6b2 | 2014-02-17 16:45:47 +0800 | [diff] [blame] | 643 | static inline u32 test_phase_bit(u32 phase_map, unsigned int bit) |
| 644 | { |
| 645 | bit %= RTSX_PHASE_MAX; |
| 646 | return phase_map & (1 << bit); |
| 647 | } |
| 648 | |
| 649 | static int sd_get_phase_len(u32 phase_map, unsigned int start_bit) |
| 650 | { |
| 651 | int i; |
| 652 | |
| 653 | for (i = 0; i < RTSX_PHASE_MAX; i++) { |
| 654 | if (test_phase_bit(phase_map, start_bit + i) == 0) |
| 655 | return i; |
| 656 | } |
| 657 | return RTSX_PHASE_MAX; |
| 658 | } |
| 659 | |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 660 | static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map) |
| 661 | { |
Micky Ching | abcc6b2 | 2014-02-17 16:45:47 +0800 | [diff] [blame] | 662 | int start = 0, len = 0; |
| 663 | int start_final = 0, len_final = 0; |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 664 | u8 final_phase = 0xFF; |
| 665 | |
Micky Ching | abcc6b2 | 2014-02-17 16:45:47 +0800 | [diff] [blame] | 666 | if (phase_map == 0) { |
| 667 | dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map); |
| 668 | return final_phase; |
| 669 | } |
| 670 | |
| 671 | while (start < RTSX_PHASE_MAX) { |
| 672 | len = sd_get_phase_len(phase_map, start); |
| 673 | if (len_final < len) { |
| 674 | start_final = start; |
| 675 | len_final = len; |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 676 | } |
Micky Ching | abcc6b2 | 2014-02-17 16:45:47 +0800 | [diff] [blame] | 677 | start += len ? len : 1; |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 678 | } |
| 679 | |
Micky Ching | abcc6b2 | 2014-02-17 16:45:47 +0800 | [diff] [blame] | 680 | final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX; |
| 681 | dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n", |
| 682 | phase_map, len_final, final_phase); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 683 | |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 684 | return final_phase; |
| 685 | } |
| 686 | |
| 687 | static void sd_wait_data_idle(struct realtek_pci_sdmmc *host) |
| 688 | { |
| 689 | int err, i; |
| 690 | u8 val = 0; |
| 691 | |
| 692 | for (i = 0; i < 100; i++) { |
| 693 | err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val); |
| 694 | if (val & SD_DATA_IDLE) |
| 695 | return; |
| 696 | |
| 697 | udelay(100); |
| 698 | } |
| 699 | } |
| 700 | |
| 701 | static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host, |
| 702 | u8 opcode, u8 sample_point) |
| 703 | { |
| 704 | int err; |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 705 | struct mmc_command cmd = {0}; |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 706 | |
Wei WANG | 84d72f9 | 2013-08-21 09:46:25 +0800 | [diff] [blame] | 707 | err = sd_change_phase(host, sample_point, true); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 708 | if (err < 0) |
| 709 | return err; |
| 710 | |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 711 | cmd.opcode = opcode; |
| 712 | err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 713 | if (err < 0) { |
| 714 | /* Wait till SD DATA IDLE */ |
| 715 | sd_wait_data_idle(host); |
| 716 | sd_clear_error(host); |
| 717 | return err; |
| 718 | } |
| 719 | |
| 720 | return 0; |
| 721 | } |
| 722 | |
| 723 | static int sd_tuning_phase(struct realtek_pci_sdmmc *host, |
| 724 | u8 opcode, u32 *phase_map) |
| 725 | { |
| 726 | int err, i; |
| 727 | u32 raw_phase_map = 0; |
| 728 | |
Micky Ching | abcc6b2 | 2014-02-17 16:45:47 +0800 | [diff] [blame] | 729 | for (i = 0; i < RTSX_PHASE_MAX; i++) { |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 730 | err = sd_tuning_rx_cmd(host, opcode, (u8)i); |
| 731 | if (err == 0) |
| 732 | raw_phase_map |= 1 << i; |
| 733 | } |
| 734 | |
| 735 | if (phase_map) |
| 736 | *phase_map = raw_phase_map; |
| 737 | |
| 738 | return 0; |
| 739 | } |
| 740 | |
| 741 | static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode) |
| 742 | { |
| 743 | int err, i; |
| 744 | u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map; |
| 745 | u8 final_phase; |
| 746 | |
| 747 | for (i = 0; i < RX_TUNING_CNT; i++) { |
| 748 | err = sd_tuning_phase(host, opcode, &(raw_phase_map[i])); |
| 749 | if (err < 0) |
| 750 | return err; |
| 751 | |
| 752 | if (raw_phase_map[i] == 0) |
| 753 | break; |
| 754 | } |
| 755 | |
| 756 | phase_map = 0xFFFFFFFF; |
| 757 | for (i = 0; i < RX_TUNING_CNT; i++) { |
| 758 | dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n", |
| 759 | i, raw_phase_map[i]); |
| 760 | phase_map &= raw_phase_map[i]; |
| 761 | } |
| 762 | dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map); |
| 763 | |
| 764 | if (phase_map) { |
| 765 | final_phase = sd_search_final_phase(host, phase_map); |
| 766 | if (final_phase == 0xFF) |
| 767 | return -EINVAL; |
| 768 | |
Wei WANG | 84d72f9 | 2013-08-21 09:46:25 +0800 | [diff] [blame] | 769 | err = sd_change_phase(host, final_phase, true); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 770 | if (err < 0) |
| 771 | return err; |
| 772 | } else { |
| 773 | return -EINVAL; |
| 774 | } |
| 775 | |
| 776 | return 0; |
| 777 | } |
| 778 | |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 779 | static inline int sdio_extblock_cmd(struct mmc_command *cmd, |
| 780 | struct mmc_data *data) |
| 781 | { |
| 782 | return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512); |
| 783 | } |
| 784 | |
Micky Ching | 6291e71 | 2014-06-06 15:05:45 +0800 | [diff] [blame] | 785 | static inline int sd_rw_cmd(struct mmc_command *cmd) |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 786 | { |
Micky Ching | 6291e71 | 2014-06-06 15:05:45 +0800 | [diff] [blame] | 787 | return mmc_op_multi(cmd->opcode) || |
| 788 | (cmd->opcode == MMC_READ_SINGLE_BLOCK) || |
| 789 | (cmd->opcode == MMC_WRITE_BLOCK); |
| 790 | } |
| 791 | |
| 792 | static void sd_request(struct work_struct *work) |
| 793 | { |
| 794 | struct realtek_pci_sdmmc *host = container_of(work, |
| 795 | struct realtek_pci_sdmmc, work); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 796 | struct rtsx_pcr *pcr = host->pcr; |
Micky Ching | 6291e71 | 2014-06-06 15:05:45 +0800 | [diff] [blame] | 797 | |
| 798 | struct mmc_host *mmc = host->mmc; |
| 799 | struct mmc_request *mrq = host->mrq; |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 800 | struct mmc_command *cmd = mrq->cmd; |
| 801 | struct mmc_data *data = mrq->data; |
Micky Ching | 6291e71 | 2014-06-06 15:05:45 +0800 | [diff] [blame] | 802 | |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 803 | unsigned int data_size = 0; |
Wei WANG | c348195 | 2013-02-08 15:24:27 +0800 | [diff] [blame] | 804 | int err; |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 805 | |
Micky Ching | b22217f | 2015-01-14 11:09:11 +0800 | [diff] [blame^] | 806 | if (host->eject || !sd_get_cd_int(host)) { |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 807 | cmd->error = -ENOMEDIUM; |
| 808 | goto finish; |
| 809 | } |
| 810 | |
Wei WANG | c348195 | 2013-02-08 15:24:27 +0800 | [diff] [blame] | 811 | err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); |
| 812 | if (err) { |
| 813 | cmd->error = err; |
| 814 | goto finish; |
| 815 | } |
| 816 | |
Micky Ching | 98fcc57 | 2014-04-29 09:54:54 +0800 | [diff] [blame] | 817 | mutex_lock(&pcr->pcr_mutex); |
| 818 | |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 819 | rtsx_pci_start_run(pcr); |
| 820 | |
| 821 | rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth, |
| 822 | host->initial_mode, host->double_clk, host->vpclk); |
| 823 | rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL); |
| 824 | rtsx_pci_write_register(pcr, CARD_SHARE_MODE, |
| 825 | CARD_SHARE_MASK, CARD_SHARE_48_SD); |
| 826 | |
Micky Ching | 98fcc57 | 2014-04-29 09:54:54 +0800 | [diff] [blame] | 827 | mutex_lock(&host->host_mutex); |
| 828 | host->mrq = mrq; |
| 829 | mutex_unlock(&host->host_mutex); |
| 830 | |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 831 | if (mrq->data) |
| 832 | data_size = data->blocks * data->blksz; |
| 833 | |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 834 | if (!data_size) { |
Micky Ching | 98fcc57 | 2014-04-29 09:54:54 +0800 | [diff] [blame] | 835 | sd_send_cmd_get_rsp(host, cmd); |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 836 | } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) { |
| 837 | cmd->error = sd_rw_multi(host, mrq); |
| 838 | if (!host->using_cookie) |
| 839 | sdmmc_post_req(host->mmc, host->mrq, 0); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 840 | |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 841 | if (mmc_op_multi(cmd->opcode) && mrq->stop) |
| 842 | sd_send_cmd_get_rsp(host, mrq->stop); |
Micky Ching | c42deff | 2014-02-17 16:45:48 +0800 | [diff] [blame] | 843 | } else { |
Micky Ching | c42deff | 2014-02-17 16:45:48 +0800 | [diff] [blame] | 844 | sd_normal_rw(host, mrq); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 845 | } |
Micky Ching | 98fcc57 | 2014-04-29 09:54:54 +0800 | [diff] [blame] | 846 | |
| 847 | if (mrq->data) { |
| 848 | if (cmd->error || data->error) |
| 849 | data->bytes_xfered = 0; |
| 850 | else |
| 851 | data->bytes_xfered = data->blocks * data->blksz; |
| 852 | } |
| 853 | |
| 854 | mutex_unlock(&pcr->pcr_mutex); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 855 | |
| 856 | finish: |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 857 | if (cmd->error) { |
| 858 | dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n", |
| 859 | cmd->opcode, cmd->arg, cmd->error); |
| 860 | } |
Micky Ching | 98fcc57 | 2014-04-29 09:54:54 +0800 | [diff] [blame] | 861 | |
| 862 | mutex_lock(&host->host_mutex); |
| 863 | host->mrq = NULL; |
| 864 | mutex_unlock(&host->host_mutex); |
| 865 | |
| 866 | mmc_request_done(mmc, mrq); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 867 | } |
| 868 | |
Micky Ching | 6291e71 | 2014-06-06 15:05:45 +0800 | [diff] [blame] | 869 | static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) |
| 870 | { |
| 871 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); |
| 872 | struct mmc_data *data = mrq->data; |
| 873 | |
| 874 | mutex_lock(&host->host_mutex); |
| 875 | host->mrq = mrq; |
| 876 | mutex_unlock(&host->host_mutex); |
| 877 | |
Micky Ching | 1dcb357 | 2014-12-23 09:19:45 +0800 | [diff] [blame] | 878 | if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data)) |
Micky Ching | 6291e71 | 2014-06-06 15:05:45 +0800 | [diff] [blame] | 879 | host->using_cookie = sd_pre_dma_transfer(host, data, false); |
| 880 | |
| 881 | queue_work(host->workq, &host->work); |
| 882 | } |
| 883 | |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 884 | static int sd_set_bus_width(struct realtek_pci_sdmmc *host, |
| 885 | unsigned char bus_width) |
| 886 | { |
| 887 | int err = 0; |
| 888 | u8 width[] = { |
| 889 | [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT, |
| 890 | [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT, |
| 891 | [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT, |
| 892 | }; |
| 893 | |
| 894 | if (bus_width <= MMC_BUS_WIDTH_8) |
| 895 | err = rtsx_pci_write_register(host->pcr, SD_CFG1, |
| 896 | 0x03, width[bus_width]); |
| 897 | |
| 898 | return err; |
| 899 | } |
| 900 | |
| 901 | static int sd_power_on(struct realtek_pci_sdmmc *host) |
| 902 | { |
| 903 | struct rtsx_pcr *pcr = host->pcr; |
| 904 | int err; |
| 905 | |
Wei WANG | d88691b | 2013-03-08 15:05:57 +0800 | [diff] [blame] | 906 | if (host->power_state == SDMMC_POWER_ON) |
| 907 | return 0; |
| 908 | |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 909 | rtsx_pci_init_cmd(pcr); |
| 910 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL); |
| 911 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE, |
| 912 | CARD_SHARE_MASK, CARD_SHARE_48_SD); |
| 913 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, |
| 914 | SD_CLK_EN, SD_CLK_EN); |
| 915 | err = rtsx_pci_send_cmd(pcr, 100); |
| 916 | if (err < 0) |
| 917 | return err; |
| 918 | |
| 919 | err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD); |
| 920 | if (err < 0) |
| 921 | return err; |
| 922 | |
| 923 | err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD); |
| 924 | if (err < 0) |
| 925 | return err; |
| 926 | |
| 927 | err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); |
| 928 | if (err < 0) |
| 929 | return err; |
| 930 | |
Wei WANG | d88691b | 2013-03-08 15:05:57 +0800 | [diff] [blame] | 931 | host->power_state = SDMMC_POWER_ON; |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 932 | return 0; |
| 933 | } |
| 934 | |
| 935 | static int sd_power_off(struct realtek_pci_sdmmc *host) |
| 936 | { |
| 937 | struct rtsx_pcr *pcr = host->pcr; |
| 938 | int err; |
| 939 | |
Wei WANG | d88691b | 2013-03-08 15:05:57 +0800 | [diff] [blame] | 940 | host->power_state = SDMMC_POWER_OFF; |
| 941 | |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 942 | rtsx_pci_init_cmd(pcr); |
| 943 | |
| 944 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0); |
| 945 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0); |
| 946 | |
| 947 | err = rtsx_pci_send_cmd(pcr, 100); |
| 948 | if (err < 0) |
| 949 | return err; |
| 950 | |
| 951 | err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); |
| 952 | if (err < 0) |
| 953 | return err; |
| 954 | |
| 955 | return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD); |
| 956 | } |
| 957 | |
| 958 | static int sd_set_power_mode(struct realtek_pci_sdmmc *host, |
| 959 | unsigned char power_mode) |
| 960 | { |
| 961 | int err; |
| 962 | |
| 963 | if (power_mode == MMC_POWER_OFF) |
| 964 | err = sd_power_off(host); |
| 965 | else |
| 966 | err = sd_power_on(host); |
| 967 | |
| 968 | return err; |
| 969 | } |
| 970 | |
Wei WANG | 84d72f9 | 2013-08-21 09:46:25 +0800 | [diff] [blame] | 971 | static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing) |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 972 | { |
| 973 | struct rtsx_pcr *pcr = host->pcr; |
| 974 | int err = 0; |
| 975 | |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 976 | rtsx_pci_init_cmd(pcr); |
| 977 | |
| 978 | switch (timing) { |
| 979 | case MMC_TIMING_UHS_SDR104: |
| 980 | case MMC_TIMING_UHS_SDR50: |
| 981 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, |
| 982 | 0x0C | SD_ASYNC_FIFO_NOT_RST, |
| 983 | SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); |
| 984 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, |
| 985 | CLK_LOW_FREQ, CLK_LOW_FREQ); |
| 986 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, |
| 987 | CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); |
| 988 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); |
| 989 | break; |
| 990 | |
Seungwon Jeon | 1a0ae37 | 2014-03-14 21:12:38 +0900 | [diff] [blame] | 991 | case MMC_TIMING_MMC_DDR52: |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 992 | case MMC_TIMING_UHS_DDR50: |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 993 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, |
| 994 | 0x0C | SD_ASYNC_FIFO_NOT_RST, |
| 995 | SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST); |
| 996 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, |
| 997 | CLK_LOW_FREQ, CLK_LOW_FREQ); |
| 998 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, |
| 999 | CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); |
| 1000 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); |
| 1001 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, |
| 1002 | DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT); |
| 1003 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, |
| 1004 | DDR_VAR_RX_DAT | DDR_VAR_RX_CMD, |
| 1005 | DDR_VAR_RX_DAT | DDR_VAR_RX_CMD); |
| 1006 | break; |
| 1007 | |
| 1008 | case MMC_TIMING_MMC_HS: |
| 1009 | case MMC_TIMING_SD_HS: |
| 1010 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, |
| 1011 | 0x0C, SD_20_MODE); |
| 1012 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, |
| 1013 | CLK_LOW_FREQ, CLK_LOW_FREQ); |
| 1014 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, |
| 1015 | CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); |
| 1016 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); |
| 1017 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, |
| 1018 | SD20_TX_SEL_MASK, SD20_TX_14_AHEAD); |
| 1019 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, |
| 1020 | SD20_RX_SEL_MASK, SD20_RX_14_DELAY); |
| 1021 | break; |
| 1022 | |
| 1023 | default: |
| 1024 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, |
| 1025 | SD_CFG1, 0x0C, SD_20_MODE); |
| 1026 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, |
| 1027 | CLK_LOW_FREQ, CLK_LOW_FREQ); |
| 1028 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, |
| 1029 | CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); |
| 1030 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); |
| 1031 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, |
| 1032 | SD_PUSH_POINT_CTL, 0xFF, 0); |
| 1033 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, |
| 1034 | SD20_RX_SEL_MASK, SD20_RX_POS_EDGE); |
| 1035 | break; |
| 1036 | } |
| 1037 | |
| 1038 | err = rtsx_pci_send_cmd(pcr, 100); |
| 1039 | |
| 1040 | return err; |
| 1041 | } |
| 1042 | |
| 1043 | static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
| 1044 | { |
| 1045 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); |
| 1046 | struct rtsx_pcr *pcr = host->pcr; |
| 1047 | |
| 1048 | if (host->eject) |
| 1049 | return; |
| 1050 | |
Wei WANG | c348195 | 2013-02-08 15:24:27 +0800 | [diff] [blame] | 1051 | if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD)) |
| 1052 | return; |
| 1053 | |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1054 | mutex_lock(&pcr->pcr_mutex); |
| 1055 | |
| 1056 | rtsx_pci_start_run(pcr); |
| 1057 | |
| 1058 | sd_set_bus_width(host, ios->bus_width); |
| 1059 | sd_set_power_mode(host, ios->power_mode); |
Wei WANG | 84d72f9 | 2013-08-21 09:46:25 +0800 | [diff] [blame] | 1060 | sd_set_timing(host, ios->timing); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1061 | |
| 1062 | host->vpclk = false; |
| 1063 | host->double_clk = true; |
| 1064 | |
| 1065 | switch (ios->timing) { |
| 1066 | case MMC_TIMING_UHS_SDR104: |
| 1067 | case MMC_TIMING_UHS_SDR50: |
| 1068 | host->ssc_depth = RTSX_SSC_DEPTH_2M; |
| 1069 | host->vpclk = true; |
| 1070 | host->double_clk = false; |
| 1071 | break; |
Seungwon Jeon | 1a0ae37 | 2014-03-14 21:12:38 +0900 | [diff] [blame] | 1072 | case MMC_TIMING_MMC_DDR52: |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1073 | case MMC_TIMING_UHS_DDR50: |
| 1074 | case MMC_TIMING_UHS_SDR25: |
| 1075 | host->ssc_depth = RTSX_SSC_DEPTH_1M; |
| 1076 | break; |
| 1077 | default: |
| 1078 | host->ssc_depth = RTSX_SSC_DEPTH_500K; |
| 1079 | break; |
| 1080 | } |
| 1081 | |
| 1082 | host->initial_mode = (ios->clock <= 1000000) ? true : false; |
| 1083 | |
| 1084 | host->clock = ios->clock; |
| 1085 | rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth, |
| 1086 | host->initial_mode, host->double_clk, host->vpclk); |
| 1087 | |
| 1088 | mutex_unlock(&pcr->pcr_mutex); |
| 1089 | } |
| 1090 | |
| 1091 | static int sdmmc_get_ro(struct mmc_host *mmc) |
| 1092 | { |
| 1093 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); |
| 1094 | struct rtsx_pcr *pcr = host->pcr; |
| 1095 | int ro = 0; |
| 1096 | u32 val; |
| 1097 | |
| 1098 | if (host->eject) |
| 1099 | return -ENOMEDIUM; |
| 1100 | |
| 1101 | mutex_lock(&pcr->pcr_mutex); |
| 1102 | |
| 1103 | rtsx_pci_start_run(pcr); |
| 1104 | |
| 1105 | /* Check SD mechanical write-protect switch */ |
| 1106 | val = rtsx_pci_readl(pcr, RTSX_BIPR); |
| 1107 | dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); |
| 1108 | if (val & SD_WRITE_PROTECT) |
| 1109 | ro = 1; |
| 1110 | |
| 1111 | mutex_unlock(&pcr->pcr_mutex); |
| 1112 | |
| 1113 | return ro; |
| 1114 | } |
| 1115 | |
| 1116 | static int sdmmc_get_cd(struct mmc_host *mmc) |
| 1117 | { |
| 1118 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); |
| 1119 | struct rtsx_pcr *pcr = host->pcr; |
| 1120 | int cd = 0; |
| 1121 | u32 val; |
| 1122 | |
| 1123 | if (host->eject) |
Micky Ching | b22217f | 2015-01-14 11:09:11 +0800 | [diff] [blame^] | 1124 | return cd; |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1125 | |
| 1126 | mutex_lock(&pcr->pcr_mutex); |
| 1127 | |
| 1128 | rtsx_pci_start_run(pcr); |
| 1129 | |
| 1130 | /* Check SD card detect */ |
| 1131 | val = rtsx_pci_card_exist(pcr); |
| 1132 | dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); |
| 1133 | if (val & SD_EXIST) |
| 1134 | cd = 1; |
| 1135 | |
| 1136 | mutex_unlock(&pcr->pcr_mutex); |
| 1137 | |
| 1138 | return cd; |
| 1139 | } |
| 1140 | |
| 1141 | static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host) |
| 1142 | { |
| 1143 | struct rtsx_pcr *pcr = host->pcr; |
| 1144 | int err; |
| 1145 | u8 stat; |
| 1146 | |
| 1147 | /* Reference to Signal Voltage Switch Sequence in SD spec. |
| 1148 | * Wait for a period of time so that the card can drive SD_CMD and |
| 1149 | * SD_DAT[3:0] to low after sending back CMD11 response. |
| 1150 | */ |
| 1151 | mdelay(1); |
| 1152 | |
| 1153 | /* SD_CMD, SD_DAT[3:0] should be driven to low by card; |
| 1154 | * If either one of SD_CMD,SD_DAT[3:0] is not low, |
| 1155 | * abort the voltage switch sequence; |
| 1156 | */ |
| 1157 | err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); |
| 1158 | if (err < 0) |
| 1159 | return err; |
| 1160 | |
| 1161 | if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | |
| 1162 | SD_DAT1_STATUS | SD_DAT0_STATUS)) |
| 1163 | return -EINVAL; |
| 1164 | |
| 1165 | /* Stop toggle SD clock */ |
| 1166 | err = rtsx_pci_write_register(pcr, SD_BUS_STAT, |
| 1167 | 0xFF, SD_CLK_FORCE_STOP); |
| 1168 | if (err < 0) |
| 1169 | return err; |
| 1170 | |
| 1171 | return 0; |
| 1172 | } |
| 1173 | |
| 1174 | static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host) |
| 1175 | { |
| 1176 | struct rtsx_pcr *pcr = host->pcr; |
| 1177 | int err; |
| 1178 | u8 stat, mask, val; |
| 1179 | |
| 1180 | /* Wait 1.8V output of voltage regulator in card stable */ |
| 1181 | msleep(50); |
| 1182 | |
| 1183 | /* Toggle SD clock again */ |
| 1184 | err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN); |
| 1185 | if (err < 0) |
| 1186 | return err; |
| 1187 | |
| 1188 | /* Wait for a period of time so that the card can drive |
| 1189 | * SD_DAT[3:0] to high at 1.8V |
| 1190 | */ |
| 1191 | msleep(20); |
| 1192 | |
| 1193 | /* SD_CMD, SD_DAT[3:0] should be pulled high by host */ |
| 1194 | err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); |
| 1195 | if (err < 0) |
| 1196 | return err; |
| 1197 | |
| 1198 | mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | |
| 1199 | SD_DAT1_STATUS | SD_DAT0_STATUS; |
| 1200 | val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | |
| 1201 | SD_DAT1_STATUS | SD_DAT0_STATUS; |
| 1202 | if ((stat & mask) != val) { |
| 1203 | dev_dbg(sdmmc_dev(host), |
| 1204 | "%s: SD_BUS_STAT = 0x%x\n", __func__, stat); |
| 1205 | rtsx_pci_write_register(pcr, SD_BUS_STAT, |
| 1206 | SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); |
| 1207 | rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0); |
| 1208 | return -EINVAL; |
| 1209 | } |
| 1210 | |
| 1211 | return 0; |
| 1212 | } |
| 1213 | |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1214 | static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) |
| 1215 | { |
| 1216 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); |
| 1217 | struct rtsx_pcr *pcr = host->pcr; |
| 1218 | int err = 0; |
| 1219 | u8 voltage; |
| 1220 | |
| 1221 | dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n", |
| 1222 | __func__, ios->signal_voltage); |
| 1223 | |
| 1224 | if (host->eject) |
| 1225 | return -ENOMEDIUM; |
| 1226 | |
Wei WANG | c348195 | 2013-02-08 15:24:27 +0800 | [diff] [blame] | 1227 | err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); |
| 1228 | if (err) |
| 1229 | return err; |
| 1230 | |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1231 | mutex_lock(&pcr->pcr_mutex); |
| 1232 | |
| 1233 | rtsx_pci_start_run(pcr); |
| 1234 | |
| 1235 | if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) |
Wei WANG | ef85e73 | 2013-01-23 09:51:05 +0800 | [diff] [blame] | 1236 | voltage = OUTPUT_3V3; |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1237 | else |
Wei WANG | ef85e73 | 2013-01-23 09:51:05 +0800 | [diff] [blame] | 1238 | voltage = OUTPUT_1V8; |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1239 | |
Wei WANG | ef85e73 | 2013-01-23 09:51:05 +0800 | [diff] [blame] | 1240 | if (voltage == OUTPUT_1V8) { |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1241 | err = sd_wait_voltage_stable_1(host); |
| 1242 | if (err < 0) |
| 1243 | goto out; |
| 1244 | } |
| 1245 | |
Wei WANG | ef85e73 | 2013-01-23 09:51:05 +0800 | [diff] [blame] | 1246 | err = rtsx_pci_switch_output_voltage(pcr, voltage); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1247 | if (err < 0) |
| 1248 | goto out; |
| 1249 | |
Wei WANG | ef85e73 | 2013-01-23 09:51:05 +0800 | [diff] [blame] | 1250 | if (voltage == OUTPUT_1V8) { |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1251 | err = sd_wait_voltage_stable_2(host); |
| 1252 | if (err < 0) |
| 1253 | goto out; |
| 1254 | } |
| 1255 | |
Wei WANG | 1b8055b | 2013-08-21 09:46:26 +0800 | [diff] [blame] | 1256 | out: |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1257 | /* Stop toggle SD clock in idle */ |
| 1258 | err = rtsx_pci_write_register(pcr, SD_BUS_STAT, |
| 1259 | SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); |
| 1260 | |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1261 | mutex_unlock(&pcr->pcr_mutex); |
| 1262 | |
| 1263 | return err; |
| 1264 | } |
| 1265 | |
| 1266 | static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) |
| 1267 | { |
| 1268 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); |
| 1269 | struct rtsx_pcr *pcr = host->pcr; |
| 1270 | int err = 0; |
| 1271 | |
| 1272 | if (host->eject) |
| 1273 | return -ENOMEDIUM; |
| 1274 | |
Wei WANG | c348195 | 2013-02-08 15:24:27 +0800 | [diff] [blame] | 1275 | err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); |
| 1276 | if (err) |
| 1277 | return err; |
| 1278 | |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1279 | mutex_lock(&pcr->pcr_mutex); |
| 1280 | |
| 1281 | rtsx_pci_start_run(pcr); |
| 1282 | |
Wei WANG | 84d72f9 | 2013-08-21 09:46:25 +0800 | [diff] [blame] | 1283 | /* Set initial TX phase */ |
| 1284 | switch (mmc->ios.timing) { |
| 1285 | case MMC_TIMING_UHS_SDR104: |
| 1286 | err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false); |
| 1287 | break; |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1288 | |
Wei WANG | 84d72f9 | 2013-08-21 09:46:25 +0800 | [diff] [blame] | 1289 | case MMC_TIMING_UHS_SDR50: |
| 1290 | err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false); |
| 1291 | break; |
| 1292 | |
| 1293 | case MMC_TIMING_UHS_DDR50: |
| 1294 | err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false); |
| 1295 | break; |
| 1296 | |
| 1297 | default: |
| 1298 | err = 0; |
| 1299 | } |
| 1300 | |
| 1301 | if (err) |
| 1302 | goto out; |
| 1303 | |
| 1304 | /* Tuning RX phase */ |
| 1305 | if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) || |
| 1306 | (mmc->ios.timing == MMC_TIMING_UHS_SDR50)) |
| 1307 | err = sd_tuning_rx(host, opcode); |
| 1308 | else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) |
| 1309 | err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true); |
| 1310 | |
| 1311 | out: |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1312 | mutex_unlock(&pcr->pcr_mutex); |
| 1313 | |
| 1314 | return err; |
| 1315 | } |
| 1316 | |
| 1317 | static const struct mmc_host_ops realtek_pci_sdmmc_ops = { |
Micky Ching | 6291e71 | 2014-06-06 15:05:45 +0800 | [diff] [blame] | 1318 | .pre_req = sdmmc_pre_req, |
| 1319 | .post_req = sdmmc_post_req, |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1320 | .request = sdmmc_request, |
| 1321 | .set_ios = sdmmc_set_ios, |
| 1322 | .get_ro = sdmmc_get_ro, |
| 1323 | .get_cd = sdmmc_get_cd, |
| 1324 | .start_signal_voltage_switch = sdmmc_switch_voltage, |
| 1325 | .execute_tuning = sdmmc_execute_tuning, |
| 1326 | }; |
| 1327 | |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1328 | static void init_extra_caps(struct realtek_pci_sdmmc *host) |
| 1329 | { |
| 1330 | struct mmc_host *mmc = host->mmc; |
| 1331 | struct rtsx_pcr *pcr = host->pcr; |
| 1332 | |
| 1333 | dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps); |
| 1334 | |
| 1335 | if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50) |
| 1336 | mmc->caps |= MMC_CAP_UHS_SDR50; |
| 1337 | if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104) |
| 1338 | mmc->caps |= MMC_CAP_UHS_SDR104; |
| 1339 | if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50) |
| 1340 | mmc->caps |= MMC_CAP_UHS_DDR50; |
| 1341 | if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR) |
| 1342 | mmc->caps |= MMC_CAP_1_8V_DDR; |
| 1343 | if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT) |
| 1344 | mmc->caps |= MMC_CAP_8_BIT_DATA; |
| 1345 | } |
| 1346 | |
| 1347 | static void realtek_init_host(struct realtek_pci_sdmmc *host) |
| 1348 | { |
| 1349 | struct mmc_host *mmc = host->mmc; |
| 1350 | |
| 1351 | mmc->f_min = 250000; |
| 1352 | mmc->f_max = 208000000; |
| 1353 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; |
| 1354 | mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | |
| 1355 | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST | |
| 1356 | MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; |
Roger Tseng | 517bf80 | 2014-09-24 17:07:14 +0800 | [diff] [blame] | 1357 | mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE; |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1358 | mmc->max_current_330 = 400; |
| 1359 | mmc->max_current_180 = 800; |
| 1360 | mmc->ops = &realtek_pci_sdmmc_ops; |
| 1361 | |
| 1362 | init_extra_caps(host); |
| 1363 | |
| 1364 | mmc->max_segs = 256; |
| 1365 | mmc->max_seg_size = 65536; |
| 1366 | mmc->max_blk_size = 512; |
| 1367 | mmc->max_blk_count = 65535; |
| 1368 | mmc->max_req_size = 524288; |
| 1369 | } |
| 1370 | |
| 1371 | static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev) |
| 1372 | { |
| 1373 | struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); |
| 1374 | |
Micky Ching | 2057647 | 2014-12-23 09:19:43 +0800 | [diff] [blame] | 1375 | host->cookie = -1; |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1376 | mmc_detect_change(host->mmc, 0); |
| 1377 | } |
| 1378 | |
| 1379 | static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev) |
| 1380 | { |
| 1381 | struct mmc_host *mmc; |
| 1382 | struct realtek_pci_sdmmc *host; |
| 1383 | struct rtsx_pcr *pcr; |
| 1384 | struct pcr_handle *handle = pdev->dev.platform_data; |
| 1385 | |
| 1386 | if (!handle) |
| 1387 | return -ENXIO; |
| 1388 | |
| 1389 | pcr = handle->pcr; |
| 1390 | if (!pcr) |
| 1391 | return -ENXIO; |
| 1392 | |
| 1393 | dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n"); |
| 1394 | |
| 1395 | mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); |
| 1396 | if (!mmc) |
| 1397 | return -ENOMEM; |
| 1398 | |
| 1399 | host = mmc_priv(mmc); |
Micky Ching | 6291e71 | 2014-06-06 15:05:45 +0800 | [diff] [blame] | 1400 | host->workq = create_singlethread_workqueue(SDMMC_WORKQ_NAME); |
| 1401 | if (!host->workq) { |
| 1402 | mmc_free_host(mmc); |
| 1403 | return -ENOMEM; |
| 1404 | } |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1405 | host->pcr = pcr; |
| 1406 | host->mmc = mmc; |
| 1407 | host->pdev = pdev; |
Micky Ching | 2057647 | 2014-12-23 09:19:43 +0800 | [diff] [blame] | 1408 | host->cookie = -1; |
Wei WANG | d88691b | 2013-03-08 15:05:57 +0800 | [diff] [blame] | 1409 | host->power_state = SDMMC_POWER_OFF; |
Micky Ching | 6291e71 | 2014-06-06 15:05:45 +0800 | [diff] [blame] | 1410 | INIT_WORK(&host->work, sd_request); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1411 | platform_set_drvdata(pdev, host); |
| 1412 | pcr->slots[RTSX_SD_CARD].p_dev = pdev; |
| 1413 | pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event; |
| 1414 | |
Micky Ching | 98fcc57 | 2014-04-29 09:54:54 +0800 | [diff] [blame] | 1415 | mutex_init(&host->host_mutex); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1416 | |
| 1417 | realtek_init_host(host); |
| 1418 | |
| 1419 | mmc_add_host(mmc); |
| 1420 | |
| 1421 | return 0; |
| 1422 | } |
| 1423 | |
| 1424 | static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev) |
| 1425 | { |
| 1426 | struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); |
| 1427 | struct rtsx_pcr *pcr; |
| 1428 | struct mmc_host *mmc; |
| 1429 | |
| 1430 | if (!host) |
| 1431 | return 0; |
| 1432 | |
| 1433 | pcr = host->pcr; |
| 1434 | pcr->slots[RTSX_SD_CARD].p_dev = NULL; |
| 1435 | pcr->slots[RTSX_SD_CARD].card_event = NULL; |
| 1436 | mmc = host->mmc; |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1437 | |
Micky Ching | 6291e71 | 2014-06-06 15:05:45 +0800 | [diff] [blame] | 1438 | cancel_work_sync(&host->work); |
| 1439 | |
Micky Ching | 98fcc57 | 2014-04-29 09:54:54 +0800 | [diff] [blame] | 1440 | mutex_lock(&host->host_mutex); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1441 | if (host->mrq) { |
| 1442 | dev_dbg(&(pdev->dev), |
| 1443 | "%s: Controller removed during transfer\n", |
| 1444 | mmc_hostname(mmc)); |
| 1445 | |
Micky Ching | 98fcc57 | 2014-04-29 09:54:54 +0800 | [diff] [blame] | 1446 | rtsx_pci_complete_unfinished_transfer(pcr); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1447 | |
Micky Ching | 98fcc57 | 2014-04-29 09:54:54 +0800 | [diff] [blame] | 1448 | host->mrq->cmd->error = -ENOMEDIUM; |
| 1449 | if (host->mrq->stop) |
| 1450 | host->mrq->stop->error = -ENOMEDIUM; |
| 1451 | mmc_request_done(mmc, host->mrq); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1452 | } |
Micky Ching | 98fcc57 | 2014-04-29 09:54:54 +0800 | [diff] [blame] | 1453 | mutex_unlock(&host->host_mutex); |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1454 | |
| 1455 | mmc_remove_host(mmc); |
Micky Ching | 640e09b | 2014-02-17 16:45:46 +0800 | [diff] [blame] | 1456 | host->eject = true; |
| 1457 | |
Micky Ching | 6291e71 | 2014-06-06 15:05:45 +0800 | [diff] [blame] | 1458 | flush_workqueue(host->workq); |
| 1459 | destroy_workqueue(host->workq); |
| 1460 | host->workq = NULL; |
| 1461 | |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1462 | mmc_free_host(mmc); |
| 1463 | |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1464 | dev_dbg(&(pdev->dev), |
| 1465 | ": Realtek PCI-E SDMMC controller has been removed\n"); |
| 1466 | |
| 1467 | return 0; |
| 1468 | } |
| 1469 | |
| 1470 | static struct platform_device_id rtsx_pci_sdmmc_ids[] = { |
| 1471 | { |
| 1472 | .name = DRV_NAME_RTSX_PCI_SDMMC, |
| 1473 | }, { |
| 1474 | /* sentinel */ |
| 1475 | } |
| 1476 | }; |
| 1477 | MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids); |
| 1478 | |
| 1479 | static struct platform_driver rtsx_pci_sdmmc_driver = { |
| 1480 | .probe = rtsx_pci_sdmmc_drv_probe, |
| 1481 | .remove = rtsx_pci_sdmmc_drv_remove, |
| 1482 | .id_table = rtsx_pci_sdmmc_ids, |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1483 | .driver = { |
Wei WANG | ff984e5 | 2012-10-29 13:49:38 +0800 | [diff] [blame] | 1484 | .name = DRV_NAME_RTSX_PCI_SDMMC, |
| 1485 | }, |
| 1486 | }; |
| 1487 | module_platform_driver(rtsx_pci_sdmmc_driver); |
| 1488 | |
| 1489 | MODULE_LICENSE("GPL"); |
| 1490 | MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); |
| 1491 | MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver"); |