Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1 | /************************************************************************** |
| 2 | * |
| 3 | * Copyright (C) 2000-2008 Alacritech, Inc. All rights reserved. |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
| 8 | * |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * 2. Redistributions in binary form must reproduce the above |
| 12 | * copyright notice, this list of conditions and the following |
| 13 | * disclaimer in the documentation and/or other materials provided |
| 14 | * with the distribution. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY |
| 17 | * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 19 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR |
| 20 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 23 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 24 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 26 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | * |
| 29 | * The views and conclusions contained in the software and documentation |
| 30 | * are those of the authors and should not be interpreted as representing |
| 31 | * official policies, either expressed or implied, of Alacritech, Inc. |
| 32 | * |
| 33 | **************************************************************************/ |
| 34 | |
| 35 | /* |
| 36 | * FILENAME: sxg.c |
| 37 | * |
| 38 | * The SXG driver for Alacritech's 10Gbe products. |
| 39 | * |
| 40 | * NOTE: This is the standard, non-accelerated version of Alacritech's |
| 41 | * IS-NIC driver. |
| 42 | */ |
| 43 | |
| 44 | #include <linux/kernel.h> |
| 45 | #include <linux/string.h> |
| 46 | #include <linux/errno.h> |
| 47 | #include <linux/module.h> |
| 48 | #include <linux/moduleparam.h> |
| 49 | #include <linux/ioport.h> |
| 50 | #include <linux/slab.h> |
| 51 | #include <linux/interrupt.h> |
| 52 | #include <linux/timer.h> |
| 53 | #include <linux/pci.h> |
| 54 | #include <linux/spinlock.h> |
| 55 | #include <linux/init.h> |
| 56 | #include <linux/netdevice.h> |
| 57 | #include <linux/etherdevice.h> |
| 58 | #include <linux/ethtool.h> |
| 59 | #include <linux/skbuff.h> |
| 60 | #include <linux/delay.h> |
| 61 | #include <linux/types.h> |
| 62 | #include <linux/dma-mapping.h> |
| 63 | #include <linux/mii.h> |
| 64 | |
| 65 | #define SLIC_DUMP_ENABLED 0 |
| 66 | #define SLIC_GET_STATS_ENABLED 0 |
| 67 | #define LINUX_FREES_ADAPTER_RESOURCES 1 |
| 68 | #define SXG_OFFLOAD_IP_CHECKSUM 0 |
| 69 | #define SXG_POWER_MANAGEMENT_ENABLED 0 |
| 70 | #define VPCI 0 |
| 71 | #define DBG 1 |
| 72 | #define ATK_DEBUG 1 |
| 73 | |
| 74 | #include "sxg_os.h" |
| 75 | #include "sxghw.h" |
| 76 | #include "sxghif.h" |
| 77 | #include "sxg.h" |
| 78 | #include "sxgdbg.h" |
| 79 | |
| 80 | #include "sxgphycode.h" |
| 81 | #include "saharadbgdownload.h" |
| 82 | |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 83 | static int sxg_allocate_buffer_memory(p_adapter_t adapter, u32 Size, |
| 84 | SXG_BUFFER_TYPE BufferType); |
| 85 | static void sxg_allocate_rcvblock_complete(p_adapter_t adapter, void *RcvBlock, |
| 86 | dma_addr_t PhysicalAddress, |
| 87 | u32 Length); |
| 88 | static void sxg_allocate_sgl_buffer_complete(p_adapter_t adapter, |
| 89 | PSXG_SCATTER_GATHER SxgSgl, |
| 90 | dma_addr_t PhysicalAddress, |
| 91 | u32 Length); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 92 | |
| 93 | static void sxg_mcast_init_crc32(void); |
| 94 | |
| 95 | static int sxg_entry_open(p_net_device dev); |
| 96 | static int sxg_entry_halt(p_net_device dev); |
| 97 | static int sxg_ioctl(p_net_device dev, struct ifreq *rq, int cmd); |
| 98 | static int sxg_send_packets(struct sk_buff *skb, p_net_device dev); |
| 99 | static int sxg_transmit_packet(p_adapter_t adapter, struct sk_buff *skb); |
| 100 | static void sxg_dumb_sgl(PSCATTER_GATHER_LIST pSgl, PSXG_SCATTER_GATHER SxgSgl); |
| 101 | |
| 102 | static void sxg_handle_interrupt(p_adapter_t adapter); |
| 103 | static int sxg_process_isr(p_adapter_t adapter, u32 MessageId); |
| 104 | static u32 sxg_process_event_queue(p_adapter_t adapter, u32 RssId); |
| 105 | static void sxg_complete_slow_send(p_adapter_t adapter); |
| 106 | static struct sk_buff *sxg_slow_receive(p_adapter_t adapter, PSXG_EVENT Event); |
| 107 | static void sxg_process_rcv_error(p_adapter_t adapter, u32 ErrorStatus); |
| 108 | static bool sxg_mac_filter(p_adapter_t adapter, |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 109 | p_ether_header EtherHdr, ushort length); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 110 | |
| 111 | #if SLIC_GET_STATS_ENABLED |
| 112 | static struct net_device_stats *sxg_get_stats(p_net_device dev); |
| 113 | #endif |
| 114 | |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 115 | static int sxg_mac_set_address(p_net_device dev, void *ptr); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 116 | |
| 117 | static void sxg_adapter_set_hwaddr(p_adapter_t adapter); |
| 118 | |
| 119 | static void sxg_unmap_mmio_space(p_adapter_t adapter); |
| 120 | static void sxg_mcast_set_mask(p_adapter_t adapter); |
| 121 | |
| 122 | static int sxg_initialize_adapter(p_adapter_t adapter); |
| 123 | static void sxg_stock_rcv_buffers(p_adapter_t adapter); |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 124 | static void sxg_complete_descriptor_blocks(p_adapter_t adapter, |
| 125 | unsigned char Index); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 126 | static int sxg_initialize_link(p_adapter_t adapter); |
| 127 | static int sxg_phy_init(p_adapter_t adapter); |
| 128 | static void sxg_link_event(p_adapter_t adapter); |
| 129 | static SXG_LINK_STATE sxg_get_link_state(p_adapter_t adapter); |
| 130 | static void sxg_link_state(p_adapter_t adapter, SXG_LINK_STATE LinkState); |
| 131 | static int sxg_write_mdio_reg(p_adapter_t adapter, |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 132 | u32 DevAddr, u32 RegAddr, u32 Value); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 133 | static int sxg_read_mdio_reg(p_adapter_t adapter, |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 134 | u32 DevAddr, u32 RegAddr, u32 *pValue); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 135 | static void sxg_mcast_set_list(p_net_device dev); |
| 136 | |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 137 | #define XXXTODO 0 |
| 138 | |
| 139 | static unsigned int sxg_first_init = 1; |
| 140 | static char *sxg_banner = |
| 141 | "Alacritech SLIC Technology(tm) Server and Storage 10Gbe Accelerator (Non-Accelerated)\n"; |
| 142 | |
| 143 | static int sxg_debug = 1; |
| 144 | static int debug = -1; |
| 145 | static p_net_device head_netdevice = NULL; |
| 146 | |
| 147 | static sxgbase_driver_t sxg_global = { |
| 148 | .dynamic_intagg = 1, |
| 149 | }; |
| 150 | static int intagg_delay = 100; |
| 151 | static u32 dynamic_intagg = 0; |
| 152 | |
| 153 | #define DRV_NAME "sxg" |
| 154 | #define DRV_VERSION "1.0.1" |
| 155 | #define DRV_AUTHOR "Alacritech, Inc. Engineering" |
| 156 | #define DRV_DESCRIPTION "Alacritech SLIC Techonology(tm) Non-Accelerated 10Gbe Driver" |
| 157 | #define DRV_COPYRIGHT "Copyright 2000-2008 Alacritech, Inc. All rights reserved." |
| 158 | |
| 159 | MODULE_AUTHOR(DRV_AUTHOR); |
| 160 | MODULE_DESCRIPTION(DRV_DESCRIPTION); |
| 161 | MODULE_LICENSE("GPL"); |
| 162 | |
| 163 | module_param(dynamic_intagg, int, 0); |
| 164 | MODULE_PARM_DESC(dynamic_intagg, "Dynamic Interrupt Aggregation Setting"); |
| 165 | module_param(intagg_delay, int, 0); |
| 166 | MODULE_PARM_DESC(intagg_delay, "uSec Interrupt Aggregation Delay"); |
| 167 | |
| 168 | static struct pci_device_id sxg_pci_tbl[] __devinitdata = { |
| 169 | {PCI_DEVICE(SXG_VENDOR_ID, SXG_DEVICE_ID)}, |
| 170 | {0,} |
| 171 | }; |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 172 | |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 173 | MODULE_DEVICE_TABLE(pci, sxg_pci_tbl); |
| 174 | |
| 175 | /*********************************************************************** |
| 176 | ************************************************************************ |
| 177 | ************************************************************************ |
| 178 | ************************************************************************ |
| 179 | ************************************************************************/ |
| 180 | |
| 181 | static inline void sxg_reg32_write(void __iomem *reg, u32 value, bool flush) |
| 182 | { |
| 183 | writel(value, reg); |
| 184 | if (flush) |
| 185 | mb(); |
| 186 | } |
| 187 | |
| 188 | static inline void sxg_reg64_write(p_adapter_t adapter, void __iomem *reg, |
| 189 | u64 value, u32 cpu) |
| 190 | { |
| 191 | u32 value_high = (u32) (value >> 32); |
| 192 | u32 value_low = (u32) (value & 0x00000000FFFFFFFF); |
| 193 | unsigned long flags; |
| 194 | |
| 195 | spin_lock_irqsave(&adapter->Bit64RegLock, flags); |
| 196 | writel(value_high, (void __iomem *)(&adapter->UcodeRegs[cpu].Upper)); |
| 197 | writel(value_low, reg); |
| 198 | spin_unlock_irqrestore(&adapter->Bit64RegLock, flags); |
| 199 | } |
| 200 | |
| 201 | static void sxg_init_driver(void) |
| 202 | { |
| 203 | if (sxg_first_init) { |
| 204 | DBG_ERROR("sxg: %s sxg_first_init set jiffies[%lx]\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 205 | __func__, jiffies); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 206 | sxg_first_init = 0; |
| 207 | spin_lock_init(&sxg_global.driver_lock); |
| 208 | } |
| 209 | } |
| 210 | |
| 211 | static void sxg_dbg_macaddrs(p_adapter_t adapter) |
| 212 | { |
| 213 | DBG_ERROR(" (%s) curr %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n", |
| 214 | adapter->netdev->name, adapter->currmacaddr[0], |
| 215 | adapter->currmacaddr[1], adapter->currmacaddr[2], |
| 216 | adapter->currmacaddr[3], adapter->currmacaddr[4], |
| 217 | adapter->currmacaddr[5]); |
| 218 | DBG_ERROR(" (%s) mac %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n", |
| 219 | adapter->netdev->name, adapter->macaddr[0], |
| 220 | adapter->macaddr[1], adapter->macaddr[2], |
| 221 | adapter->macaddr[3], adapter->macaddr[4], |
| 222 | adapter->macaddr[5]); |
| 223 | return; |
| 224 | } |
| 225 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 226 | /* SXG Globals */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 227 | static SXG_DRIVER SxgDriver; |
| 228 | |
| 229 | #ifdef ATKDBG |
| 230 | static sxg_trace_buffer_t LSxgTraceBuffer; |
| 231 | #endif /* ATKDBG */ |
| 232 | static sxg_trace_buffer_t *SxgTraceBuffer = NULL; |
| 233 | |
| 234 | /* |
| 235 | * sxg_download_microcode |
| 236 | * |
| 237 | * Download Microcode to Sahara adapter |
| 238 | * |
| 239 | * Arguments - |
| 240 | * adapter - A pointer to our adapter structure |
| 241 | * UcodeSel - microcode file selection |
| 242 | * |
| 243 | * Return |
| 244 | * int |
| 245 | */ |
| 246 | static bool sxg_download_microcode(p_adapter_t adapter, SXG_UCODE_SEL UcodeSel) |
| 247 | { |
| 248 | PSXG_HW_REGS HwRegs = adapter->HwRegs; |
| 249 | u32 Section; |
| 250 | u32 ThisSectionSize; |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 251 | u32 *Instruction = NULL; |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 252 | u32 BaseAddress, AddressOffset, Address; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 253 | /* u32 Failure; */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 254 | u32 ValueRead; |
| 255 | u32 i; |
| 256 | u32 numSections = 0; |
| 257 | u32 sectionSize[16]; |
| 258 | u32 sectionStart[16]; |
| 259 | |
| 260 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DnldUcod", |
| 261 | adapter, 0, 0, 0); |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 262 | DBG_ERROR("sxg: %s ENTER\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 263 | |
| 264 | switch (UcodeSel) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 265 | case SXG_UCODE_SAHARA: /* Sahara operational ucode */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 266 | numSections = SNumSections; |
| 267 | for (i = 0; i < numSections; i++) { |
| 268 | sectionSize[i] = SSectionSize[i]; |
| 269 | sectionStart[i] = SSectionStart[i]; |
| 270 | } |
| 271 | break; |
| 272 | default: |
| 273 | printk(KERN_ERR KBUILD_MODNAME |
| 274 | ": Woah, big error with the microcode!\n"); |
| 275 | break; |
| 276 | } |
| 277 | |
| 278 | DBG_ERROR("sxg: RESET THE CARD\n"); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 279 | /* First, reset the card */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 280 | WRITE_REG(HwRegs->Reset, 0xDEAD, FLUSH); |
| 281 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 282 | /* Download each section of the microcode as specified in */ |
| 283 | /* its download file. The *download.c file is generated using */ |
| 284 | /* the saharaobjtoc facility which converts the metastep .obj */ |
| 285 | /* file to a .c file which contains a two dimentional array. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 286 | for (Section = 0; Section < numSections; Section++) { |
| 287 | DBG_ERROR("sxg: SECTION # %d\n", Section); |
| 288 | switch (UcodeSel) { |
| 289 | case SXG_UCODE_SAHARA: |
| 290 | Instruction = (u32 *) & SaharaUCode[Section][0]; |
| 291 | break; |
| 292 | default: |
| 293 | ASSERT(0); |
| 294 | break; |
| 295 | } |
| 296 | BaseAddress = sectionStart[Section]; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 297 | ThisSectionSize = sectionSize[Section] / 12; /* Size in instructions */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 298 | for (AddressOffset = 0; AddressOffset < ThisSectionSize; |
| 299 | AddressOffset++) { |
| 300 | Address = BaseAddress + AddressOffset; |
| 301 | ASSERT((Address & ~MICROCODE_ADDRESS_MASK) == 0); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 302 | /* Write instruction bits 31 - 0 */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 303 | WRITE_REG(HwRegs->UcodeDataLow, *Instruction, FLUSH); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 304 | /* Write instruction bits 63-32 */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 305 | WRITE_REG(HwRegs->UcodeDataMiddle, *(Instruction + 1), |
| 306 | FLUSH); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 307 | /* Write instruction bits 95-64 */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 308 | WRITE_REG(HwRegs->UcodeDataHigh, *(Instruction + 2), |
| 309 | FLUSH); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 310 | /* Write instruction address with the WRITE bit set */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 311 | WRITE_REG(HwRegs->UcodeAddr, |
| 312 | (Address | MICROCODE_ADDRESS_WRITE), FLUSH); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 313 | /* Sahara bug in the ucode download logic - the write to DataLow */ |
| 314 | /* for the next instruction could get corrupted. To avoid this, */ |
| 315 | /* write to DataLow again for this instruction (which may get */ |
| 316 | /* corrupted, but it doesn't matter), then increment the address */ |
| 317 | /* and write the data for the next instruction to DataLow. That */ |
| 318 | /* write should succeed. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 319 | WRITE_REG(HwRegs->UcodeDataLow, *Instruction, TRUE); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 320 | /* Advance 3 u32S to start of next instruction */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 321 | Instruction += 3; |
| 322 | } |
| 323 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 324 | /* Now repeat the entire operation reading the instruction back and */ |
| 325 | /* checking for parity errors */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 326 | for (Section = 0; Section < numSections; Section++) { |
| 327 | DBG_ERROR("sxg: check SECTION # %d\n", Section); |
| 328 | switch (UcodeSel) { |
| 329 | case SXG_UCODE_SAHARA: |
| 330 | Instruction = (u32 *) & SaharaUCode[Section][0]; |
| 331 | break; |
| 332 | default: |
| 333 | ASSERT(0); |
| 334 | break; |
| 335 | } |
| 336 | BaseAddress = sectionStart[Section]; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 337 | ThisSectionSize = sectionSize[Section] / 12; /* Size in instructions */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 338 | for (AddressOffset = 0; AddressOffset < ThisSectionSize; |
| 339 | AddressOffset++) { |
| 340 | Address = BaseAddress + AddressOffset; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 341 | /* Write the address with the READ bit set */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 342 | WRITE_REG(HwRegs->UcodeAddr, |
| 343 | (Address | MICROCODE_ADDRESS_READ), FLUSH); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 344 | /* Read it back and check parity bit. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 345 | READ_REG(HwRegs->UcodeAddr, ValueRead); |
| 346 | if (ValueRead & MICROCODE_ADDRESS_PARITY) { |
| 347 | DBG_ERROR("sxg: %s PARITY ERROR\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 348 | __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 349 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 350 | return (FALSE); /* Parity error */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 351 | } |
| 352 | ASSERT((ValueRead & MICROCODE_ADDRESS_MASK) == Address); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 353 | /* Read the instruction back and compare */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 354 | READ_REG(HwRegs->UcodeDataLow, ValueRead); |
| 355 | if (ValueRead != *Instruction) { |
| 356 | DBG_ERROR("sxg: %s MISCOMPARE LOW\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 357 | __func__); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 358 | return (FALSE); /* Miscompare */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 359 | } |
| 360 | READ_REG(HwRegs->UcodeDataMiddle, ValueRead); |
| 361 | if (ValueRead != *(Instruction + 1)) { |
| 362 | DBG_ERROR("sxg: %s MISCOMPARE MIDDLE\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 363 | __func__); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 364 | return (FALSE); /* Miscompare */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 365 | } |
| 366 | READ_REG(HwRegs->UcodeDataHigh, ValueRead); |
| 367 | if (ValueRead != *(Instruction + 2)) { |
| 368 | DBG_ERROR("sxg: %s MISCOMPARE HIGH\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 369 | __func__); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 370 | return (FALSE); /* Miscompare */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 371 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 372 | /* Advance 3 u32S to start of next instruction */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 373 | Instruction += 3; |
| 374 | } |
| 375 | } |
| 376 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 377 | /* Everything OK, Go. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 378 | WRITE_REG(HwRegs->UcodeAddr, MICROCODE_ADDRESS_GO, FLUSH); |
| 379 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 380 | /* Poll the CardUp register to wait for microcode to initialize */ |
| 381 | /* Give up after 10,000 attemps (500ms). */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 382 | for (i = 0; i < 10000; i++) { |
| 383 | udelay(50); |
| 384 | READ_REG(adapter->UcodeRegs[0].CardUp, ValueRead); |
| 385 | if (ValueRead == 0xCAFE) { |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 386 | DBG_ERROR("sxg: %s BOO YA 0xCAFE\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 387 | break; |
| 388 | } |
| 389 | } |
| 390 | if (i == 10000) { |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 391 | DBG_ERROR("sxg: %s TIMEOUT\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 392 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 393 | return (FALSE); /* Timeout */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 394 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 395 | /* Now write the LoadSync register. This is used to */ |
| 396 | /* synchronize with the card so it can scribble on the memory */ |
| 397 | /* that contained 0xCAFE from the "CardUp" step above */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 398 | if (UcodeSel == SXG_UCODE_SAHARA) { |
| 399 | WRITE_REG(adapter->UcodeRegs[0].LoadSync, 0, FLUSH); |
| 400 | } |
| 401 | |
| 402 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XDnldUcd", |
| 403 | adapter, 0, 0, 0); |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 404 | DBG_ERROR("sxg: %s EXIT\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 405 | |
| 406 | return (TRUE); |
| 407 | } |
| 408 | |
| 409 | /* |
| 410 | * sxg_allocate_resources - Allocate memory and locks |
| 411 | * |
| 412 | * Arguments - |
| 413 | * adapter - A pointer to our adapter structure |
| 414 | * |
| 415 | * Return |
| 416 | * int |
| 417 | */ |
| 418 | static int sxg_allocate_resources(p_adapter_t adapter) |
| 419 | { |
| 420 | int status; |
| 421 | u32 i; |
| 422 | u32 RssIds, IsrCount; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 423 | /* PSXG_XMT_RING XmtRing; */ |
| 424 | /* PSXG_RCV_RING RcvRing; */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 425 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 426 | DBG_ERROR("%s ENTER\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 427 | |
| 428 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AllocRes", |
| 429 | adapter, 0, 0, 0); |
| 430 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 431 | /* Windows tells us how many CPUs it plans to use for */ |
| 432 | /* RSS */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 433 | RssIds = SXG_RSS_CPU_COUNT(adapter); |
| 434 | IsrCount = adapter->MsiEnabled ? RssIds : 1; |
| 435 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 436 | DBG_ERROR("%s Setup the spinlocks\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 437 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 438 | /* Allocate spinlocks and initialize listheads first. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 439 | spin_lock_init(&adapter->RcvQLock); |
| 440 | spin_lock_init(&adapter->SglQLock); |
| 441 | spin_lock_init(&adapter->XmtZeroLock); |
| 442 | spin_lock_init(&adapter->Bit64RegLock); |
| 443 | spin_lock_init(&adapter->AdapterLock); |
| 444 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 445 | DBG_ERROR("%s Setup the lists\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 446 | |
| 447 | InitializeListHead(&adapter->FreeRcvBuffers); |
| 448 | InitializeListHead(&adapter->FreeRcvBlocks); |
| 449 | InitializeListHead(&adapter->AllRcvBlocks); |
| 450 | InitializeListHead(&adapter->FreeSglBuffers); |
| 451 | InitializeListHead(&adapter->AllSglBuffers); |
| 452 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 453 | /* Mark these basic allocations done. This flags essentially */ |
| 454 | /* tells the SxgFreeResources routine that it can grab spinlocks */ |
| 455 | /* and reference listheads. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 456 | adapter->BasicAllocations = TRUE; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 457 | /* Main allocation loop. Start with the maximum supported by */ |
| 458 | /* the microcode and back off if memory allocation */ |
| 459 | /* fails. If we hit a minimum, fail. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 460 | |
| 461 | for (;;) { |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 462 | DBG_ERROR("%s Allocate XmtRings size[%lx]\n", __func__, |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 463 | (sizeof(SXG_XMT_RING) * 1)); |
| 464 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 465 | /* Start with big items first - receive and transmit rings. At the moment */ |
| 466 | /* I'm going to keep the ring size fixed and adjust the number of */ |
| 467 | /* TCBs if we fail. Later we might consider reducing the ring size as well.. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 468 | adapter->XmtRings = pci_alloc_consistent(adapter->pcidev, |
| 469 | sizeof(SXG_XMT_RING) * |
| 470 | 1, |
| 471 | &adapter->PXmtRings); |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 472 | DBG_ERROR("%s XmtRings[%p]\n", __func__, adapter->XmtRings); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 473 | |
| 474 | if (!adapter->XmtRings) { |
| 475 | goto per_tcb_allocation_failed; |
| 476 | } |
| 477 | memset(adapter->XmtRings, 0, sizeof(SXG_XMT_RING) * 1); |
| 478 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 479 | DBG_ERROR("%s Allocate RcvRings size[%lx]\n", __func__, |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 480 | (sizeof(SXG_RCV_RING) * 1)); |
| 481 | adapter->RcvRings = |
| 482 | pci_alloc_consistent(adapter->pcidev, |
| 483 | sizeof(SXG_RCV_RING) * 1, |
| 484 | &adapter->PRcvRings); |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 485 | DBG_ERROR("%s RcvRings[%p]\n", __func__, adapter->RcvRings); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 486 | if (!adapter->RcvRings) { |
| 487 | goto per_tcb_allocation_failed; |
| 488 | } |
| 489 | memset(adapter->RcvRings, 0, sizeof(SXG_RCV_RING) * 1); |
| 490 | break; |
| 491 | |
| 492 | per_tcb_allocation_failed: |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 493 | /* an allocation failed. Free any successful allocations. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 494 | if (adapter->XmtRings) { |
| 495 | pci_free_consistent(adapter->pcidev, |
| 496 | sizeof(SXG_XMT_RING) * 4096, |
| 497 | adapter->XmtRings, |
| 498 | adapter->PXmtRings); |
| 499 | adapter->XmtRings = NULL; |
| 500 | } |
| 501 | if (adapter->RcvRings) { |
| 502 | pci_free_consistent(adapter->pcidev, |
| 503 | sizeof(SXG_RCV_RING) * 4096, |
| 504 | adapter->RcvRings, |
| 505 | adapter->PRcvRings); |
| 506 | adapter->RcvRings = NULL; |
| 507 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 508 | /* Loop around and try again.... */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 509 | } |
| 510 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 511 | DBG_ERROR("%s Initialize RCV ZERO and XMT ZERO rings\n", __func__); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 512 | /* Initialize rcv zero and xmt zero rings */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 513 | SXG_INITIALIZE_RING(adapter->RcvRingZeroInfo, SXG_RCV_RING_SIZE); |
| 514 | SXG_INITIALIZE_RING(adapter->XmtRingZeroInfo, SXG_XMT_RING_SIZE); |
| 515 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 516 | /* Sanity check receive data structure format */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 517 | ASSERT((adapter->ReceiveBufferSize == SXG_RCV_DATA_BUFFER_SIZE) || |
| 518 | (adapter->ReceiveBufferSize == SXG_RCV_JUMBO_BUFFER_SIZE)); |
| 519 | ASSERT(sizeof(SXG_RCV_DESCRIPTOR_BLOCK) == |
| 520 | SXG_RCV_DESCRIPTOR_BLOCK_SIZE); |
| 521 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 522 | /* Allocate receive data buffers. We allocate a block of buffers and */ |
| 523 | /* a corresponding descriptor block at once. See sxghw.h:SXG_RCV_BLOCK */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 524 | for (i = 0; i < SXG_INITIAL_RCV_DATA_BUFFERS; |
| 525 | i += SXG_RCV_DESCRIPTORS_PER_BLOCK) { |
| 526 | sxg_allocate_buffer_memory(adapter, |
| 527 | SXG_RCV_BLOCK_SIZE(adapter-> |
| 528 | ReceiveBufferSize), |
| 529 | SXG_BUFFER_TYPE_RCV); |
| 530 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 531 | /* NBL resource allocation can fail in the 'AllocateComplete' routine, which */ |
| 532 | /* doesn't return status. Make sure we got the number of buffers we requested */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 533 | if (adapter->FreeRcvBufferCount < SXG_INITIAL_RCV_DATA_BUFFERS) { |
| 534 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF6", |
| 535 | adapter, adapter->FreeRcvBufferCount, SXG_MAX_ENTRIES, |
| 536 | 0); |
| 537 | return (STATUS_RESOURCES); |
| 538 | } |
| 539 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 540 | DBG_ERROR("%s Allocate EventRings size[%lx]\n", __func__, |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 541 | (sizeof(SXG_EVENT_RING) * RssIds)); |
| 542 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 543 | /* Allocate event queues. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 544 | adapter->EventRings = pci_alloc_consistent(adapter->pcidev, |
| 545 | sizeof(SXG_EVENT_RING) * |
| 546 | RssIds, |
| 547 | &adapter->PEventRings); |
| 548 | |
| 549 | if (!adapter->EventRings) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 550 | /* Caller will call SxgFreeAdapter to clean up above allocations */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 551 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF8", |
| 552 | adapter, SXG_MAX_ENTRIES, 0, 0); |
| 553 | status = STATUS_RESOURCES; |
| 554 | goto per_tcb_allocation_failed; |
| 555 | } |
| 556 | memset(adapter->EventRings, 0, sizeof(SXG_EVENT_RING) * RssIds); |
| 557 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 558 | DBG_ERROR("%s Allocate ISR size[%x]\n", __func__, IsrCount); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 559 | /* Allocate ISR */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 560 | adapter->Isr = pci_alloc_consistent(adapter->pcidev, |
| 561 | IsrCount, &adapter->PIsr); |
| 562 | if (!adapter->Isr) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 563 | /* Caller will call SxgFreeAdapter to clean up above allocations */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 564 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF9", |
| 565 | adapter, SXG_MAX_ENTRIES, 0, 0); |
| 566 | status = STATUS_RESOURCES; |
| 567 | goto per_tcb_allocation_failed; |
| 568 | } |
| 569 | memset(adapter->Isr, 0, sizeof(u32) * IsrCount); |
| 570 | |
J.R. Mauro | d63d692 | 2008-10-03 12:21:49 -0400 | [diff] [blame] | 571 | DBG_ERROR("%s Allocate shared XMT ring zero index location size[%lx]\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 572 | __func__, sizeof(u32)); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 573 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 574 | /* Allocate shared XMT ring zero index location */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 575 | adapter->XmtRingZeroIndex = pci_alloc_consistent(adapter->pcidev, |
| 576 | sizeof(u32), |
| 577 | &adapter-> |
| 578 | PXmtRingZeroIndex); |
| 579 | if (!adapter->XmtRingZeroIndex) { |
| 580 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF10", |
| 581 | adapter, SXG_MAX_ENTRIES, 0, 0); |
| 582 | status = STATUS_RESOURCES; |
| 583 | goto per_tcb_allocation_failed; |
| 584 | } |
| 585 | memset(adapter->XmtRingZeroIndex, 0, sizeof(u32)); |
| 586 | |
| 587 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlcResS", |
| 588 | adapter, SXG_MAX_ENTRIES, 0, 0); |
| 589 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 590 | DBG_ERROR("%s EXIT\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 591 | return (STATUS_SUCCESS); |
| 592 | } |
| 593 | |
| 594 | /* |
| 595 | * sxg_config_pci - |
| 596 | * |
| 597 | * Set up PCI Configuration space |
| 598 | * |
| 599 | * Arguments - |
| 600 | * pcidev - A pointer to our adapter structure |
| 601 | * |
| 602 | */ |
| 603 | static void sxg_config_pci(struct pci_dev *pcidev) |
| 604 | { |
| 605 | u16 pci_command; |
| 606 | u16 new_command; |
| 607 | |
| 608 | pci_read_config_word(pcidev, PCI_COMMAND, &pci_command); |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 609 | DBG_ERROR("sxg: %s PCI command[%4.4x]\n", __func__, pci_command); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 610 | /* Set the command register */ |
| 611 | new_command = pci_command | (PCI_COMMAND_MEMORY | /* Memory Space Enable */ |
| 612 | PCI_COMMAND_MASTER | /* Bus master enable */ |
| 613 | PCI_COMMAND_INVALIDATE | /* Memory write and invalidate */ |
| 614 | PCI_COMMAND_PARITY | /* Parity error response */ |
| 615 | PCI_COMMAND_SERR | /* System ERR */ |
| 616 | PCI_COMMAND_FAST_BACK); /* Fast back-to-back */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 617 | if (pci_command != new_command) { |
| 618 | DBG_ERROR("%s -- Updating PCI COMMAND register %4.4x->%4.4x.\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 619 | __func__, pci_command, new_command); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 620 | pci_write_config_word(pcidev, PCI_COMMAND, new_command); |
| 621 | } |
| 622 | } |
| 623 | |
| 624 | static int sxg_entry_probe(struct pci_dev *pcidev, |
| 625 | const struct pci_device_id *pci_tbl_entry) |
| 626 | { |
| 627 | static int did_version = 0; |
| 628 | int err; |
| 629 | struct net_device *netdev; |
| 630 | p_adapter_t adapter; |
| 631 | void __iomem *memmapped_ioaddr; |
| 632 | u32 status = 0; |
| 633 | ulong mmio_start = 0; |
| 634 | ulong mmio_len = 0; |
| 635 | |
| 636 | DBG_ERROR("sxg: %s 2.6 VERSION ENTER jiffies[%lx] cpu %d\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 637 | __func__, jiffies, smp_processor_id()); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 638 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 639 | /* Initialize trace buffer */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 640 | #ifdef ATKDBG |
| 641 | SxgTraceBuffer = &LSxgTraceBuffer; |
| 642 | SXG_TRACE_INIT(SxgTraceBuffer, TRACE_NOISY); |
| 643 | #endif |
| 644 | |
| 645 | sxg_global.dynamic_intagg = dynamic_intagg; |
| 646 | |
| 647 | err = pci_enable_device(pcidev); |
| 648 | |
| 649 | DBG_ERROR("Call pci_enable_device(%p) status[%x]\n", pcidev, err); |
| 650 | if (err) { |
| 651 | return err; |
| 652 | } |
| 653 | |
| 654 | if (sxg_debug > 0 && did_version++ == 0) { |
| 655 | printk(KERN_INFO "%s\n", sxg_banner); |
| 656 | printk(KERN_INFO "%s\n", DRV_VERSION); |
| 657 | } |
| 658 | |
| 659 | if (!(err = pci_set_dma_mask(pcidev, DMA_64BIT_MASK))) { |
| 660 | DBG_ERROR("pci_set_dma_mask(DMA_64BIT_MASK) successful\n"); |
| 661 | } else { |
| 662 | if ((err = pci_set_dma_mask(pcidev, DMA_32BIT_MASK))) { |
| 663 | DBG_ERROR |
| 664 | ("No usable DMA configuration, aborting err[%x]\n", |
| 665 | err); |
| 666 | return err; |
| 667 | } |
| 668 | DBG_ERROR("pci_set_dma_mask(DMA_32BIT_MASK) successful\n"); |
| 669 | } |
| 670 | |
| 671 | DBG_ERROR("Call pci_request_regions\n"); |
| 672 | |
| 673 | err = pci_request_regions(pcidev, DRV_NAME); |
| 674 | if (err) { |
| 675 | DBG_ERROR("pci_request_regions FAILED err[%x]\n", err); |
| 676 | return err; |
| 677 | } |
| 678 | |
| 679 | DBG_ERROR("call pci_set_master\n"); |
| 680 | pci_set_master(pcidev); |
| 681 | |
| 682 | DBG_ERROR("call alloc_etherdev\n"); |
| 683 | netdev = alloc_etherdev(sizeof(adapter_t)); |
| 684 | if (!netdev) { |
| 685 | err = -ENOMEM; |
| 686 | goto err_out_exit_sxg_probe; |
| 687 | } |
| 688 | DBG_ERROR("alloc_etherdev for slic netdev[%p]\n", netdev); |
| 689 | |
| 690 | SET_NETDEV_DEV(netdev, &pcidev->dev); |
| 691 | |
| 692 | pci_set_drvdata(pcidev, netdev); |
| 693 | adapter = netdev_priv(netdev); |
| 694 | adapter->netdev = netdev; |
| 695 | adapter->pcidev = pcidev; |
| 696 | |
| 697 | mmio_start = pci_resource_start(pcidev, 0); |
| 698 | mmio_len = pci_resource_len(pcidev, 0); |
| 699 | |
| 700 | DBG_ERROR("sxg: call ioremap(mmio_start[%lx], mmio_len[%lx])\n", |
| 701 | mmio_start, mmio_len); |
| 702 | |
| 703 | memmapped_ioaddr = ioremap(mmio_start, mmio_len); |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 704 | DBG_ERROR("sxg: %s MEMMAPPED_IOADDR [%p]\n", __func__, |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 705 | memmapped_ioaddr); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 706 | if (!memmapped_ioaddr) { |
| 707 | DBG_ERROR("%s cannot remap MMIO region %lx @ %lx\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 708 | __func__, mmio_len, mmio_start); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 709 | goto err_out_free_mmio_region; |
| 710 | } |
| 711 | |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 712 | DBG_ERROR |
| 713 | ("sxg: %s found Alacritech SXG PCI, MMIO at %p, start[%lx] len[%lx], IRQ %d.\n", |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 714 | __func__, memmapped_ioaddr, mmio_start, mmio_len, pcidev->irq); |
| 715 | |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 716 | adapter->HwRegs = (void *)memmapped_ioaddr; |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 717 | adapter->base_addr = memmapped_ioaddr; |
| 718 | |
| 719 | mmio_start = pci_resource_start(pcidev, 2); |
| 720 | mmio_len = pci_resource_len(pcidev, 2); |
| 721 | |
| 722 | DBG_ERROR("sxg: call ioremap(mmio_start[%lx], mmio_len[%lx])\n", |
| 723 | mmio_start, mmio_len); |
| 724 | |
| 725 | memmapped_ioaddr = ioremap(mmio_start, mmio_len); |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 726 | DBG_ERROR("sxg: %s MEMMAPPED_IOADDR [%p]\n", __func__, |
| 727 | memmapped_ioaddr); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 728 | if (!memmapped_ioaddr) { |
| 729 | DBG_ERROR("%s cannot remap MMIO region %lx @ %lx\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 730 | __func__, mmio_len, mmio_start); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 731 | goto err_out_free_mmio_region; |
| 732 | } |
| 733 | |
| 734 | DBG_ERROR("sxg: %s found Alacritech SXG PCI, MMIO at %p, " |
| 735 | "start[%lx] len[%lx], IRQ %d.\n", __func__, |
| 736 | memmapped_ioaddr, mmio_start, mmio_len, pcidev->irq); |
| 737 | |
| 738 | adapter->UcodeRegs = (void *)memmapped_ioaddr; |
| 739 | |
| 740 | adapter->State = SXG_STATE_INITIALIZING; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 741 | /* Maintain a list of all adapters anchored by */ |
| 742 | /* the global SxgDriver structure. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 743 | adapter->Next = SxgDriver.Adapters; |
| 744 | SxgDriver.Adapters = adapter; |
| 745 | adapter->AdapterID = ++SxgDriver.AdapterID; |
| 746 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 747 | /* Initialize CRC table used to determine multicast hash */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 748 | sxg_mcast_init_crc32(); |
| 749 | |
| 750 | adapter->JumboEnabled = FALSE; |
| 751 | adapter->RssEnabled = FALSE; |
| 752 | if (adapter->JumboEnabled) { |
| 753 | adapter->FrameSize = JUMBOMAXFRAME; |
| 754 | adapter->ReceiveBufferSize = SXG_RCV_JUMBO_BUFFER_SIZE; |
| 755 | } else { |
| 756 | adapter->FrameSize = ETHERMAXFRAME; |
| 757 | adapter->ReceiveBufferSize = SXG_RCV_DATA_BUFFER_SIZE; |
| 758 | } |
| 759 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 760 | /* status = SXG_READ_EEPROM(adapter); */ |
| 761 | /* if (!status) { */ |
| 762 | /* goto sxg_init_bad; */ |
| 763 | /* } */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 764 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 765 | DBG_ERROR("sxg: %s ENTER sxg_config_pci\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 766 | sxg_config_pci(pcidev); |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 767 | DBG_ERROR("sxg: %s EXIT sxg_config_pci\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 768 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 769 | DBG_ERROR("sxg: %s ENTER sxg_init_driver\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 770 | sxg_init_driver(); |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 771 | DBG_ERROR("sxg: %s EXIT sxg_init_driver\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 772 | |
| 773 | adapter->vendid = pci_tbl_entry->vendor; |
| 774 | adapter->devid = pci_tbl_entry->device; |
| 775 | adapter->subsysid = pci_tbl_entry->subdevice; |
| 776 | adapter->busnumber = pcidev->bus->number; |
| 777 | adapter->slotnumber = ((pcidev->devfn >> 3) & 0x1F); |
| 778 | adapter->functionnumber = (pcidev->devfn & 0x7); |
| 779 | adapter->memorylength = pci_resource_len(pcidev, 0); |
| 780 | adapter->irq = pcidev->irq; |
| 781 | adapter->next_netdevice = head_netdevice; |
| 782 | head_netdevice = netdev; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 783 | /* adapter->chipid = chip_idx; */ |
| 784 | adapter->port = 0; /*adapter->functionnumber; */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 785 | adapter->cardindex = adapter->port; |
| 786 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 787 | /* Allocate memory and other resources */ |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 788 | DBG_ERROR("sxg: %s ENTER sxg_allocate_resources\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 789 | status = sxg_allocate_resources(adapter); |
| 790 | DBG_ERROR("sxg: %s EXIT sxg_allocate_resources status %x\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 791 | __func__, status); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 792 | if (status != STATUS_SUCCESS) { |
| 793 | goto err_out_unmap; |
| 794 | } |
| 795 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 796 | DBG_ERROR("sxg: %s ENTER sxg_download_microcode\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 797 | if (sxg_download_microcode(adapter, SXG_UCODE_SAHARA)) { |
| 798 | DBG_ERROR("sxg: %s ENTER sxg_adapter_set_hwaddr\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 799 | __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 800 | sxg_adapter_set_hwaddr(adapter); |
| 801 | } else { |
| 802 | adapter->state = ADAPT_FAIL; |
| 803 | adapter->linkstate = LINK_DOWN; |
| 804 | DBG_ERROR("sxg_download_microcode FAILED status[%x]\n", status); |
| 805 | } |
| 806 | |
| 807 | netdev->base_addr = (unsigned long)adapter->base_addr; |
| 808 | netdev->irq = adapter->irq; |
| 809 | netdev->open = sxg_entry_open; |
| 810 | netdev->stop = sxg_entry_halt; |
| 811 | netdev->hard_start_xmit = sxg_send_packets; |
| 812 | netdev->do_ioctl = sxg_ioctl; |
| 813 | #if XXXTODO |
| 814 | netdev->set_mac_address = sxg_mac_set_address; |
| 815 | #if SLIC_GET_STATS_ENABLED |
| 816 | netdev->get_stats = sxg_get_stats; |
| 817 | #endif |
| 818 | netdev->set_multicast_list = sxg_mcast_set_list; |
| 819 | #endif |
| 820 | |
| 821 | strcpy(netdev->name, "eth%d"); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 822 | /* strcpy(netdev->name, pci_name(pcidev)); */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 823 | if ((err = register_netdev(netdev))) { |
| 824 | DBG_ERROR("Cannot register net device, aborting. %s\n", |
| 825 | netdev->name); |
| 826 | goto err_out_unmap; |
| 827 | } |
| 828 | |
| 829 | DBG_ERROR |
| 830 | ("sxg: %s addr 0x%lx, irq %d, MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n", |
| 831 | netdev->name, netdev->base_addr, pcidev->irq, netdev->dev_addr[0], |
| 832 | netdev->dev_addr[1], netdev->dev_addr[2], netdev->dev_addr[3], |
| 833 | netdev->dev_addr[4], netdev->dev_addr[5]); |
| 834 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 835 | /*sxg_init_bad: */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 836 | ASSERT(status == FALSE); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 837 | /* sxg_free_adapter(adapter); */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 838 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 839 | DBG_ERROR("sxg: %s EXIT status[%x] jiffies[%lx] cpu %d\n", __func__, |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 840 | status, jiffies, smp_processor_id()); |
| 841 | return status; |
| 842 | |
| 843 | err_out_unmap: |
| 844 | iounmap((void *)memmapped_ioaddr); |
| 845 | |
| 846 | err_out_free_mmio_region: |
| 847 | release_mem_region(mmio_start, mmio_len); |
| 848 | |
| 849 | err_out_exit_sxg_probe: |
| 850 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 851 | DBG_ERROR("%s EXIT jiffies[%lx] cpu %d\n", __func__, jiffies, |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 852 | smp_processor_id()); |
| 853 | |
| 854 | return -ENODEV; |
| 855 | } |
| 856 | |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 857 | /*********************************************************************** |
| 858 | * LINE BASE Interrupt routines.. |
| 859 | ***********************************************************************/ |
| 860 | /* |
| 861 | * |
| 862 | * sxg_disable_interrupt |
| 863 | * |
| 864 | * DisableInterrupt Handler |
| 865 | * |
| 866 | * Arguments: |
| 867 | * |
| 868 | * adapter: Our adapter structure |
| 869 | * |
| 870 | * Return Value: |
| 871 | * None. |
| 872 | */ |
| 873 | static void sxg_disable_interrupt(p_adapter_t adapter) |
| 874 | { |
| 875 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DisIntr", |
| 876 | adapter, adapter->InterruptsEnabled, 0, 0); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 877 | /* For now, RSS is disabled with line based interrupts */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 878 | ASSERT(adapter->RssEnabled == FALSE); |
| 879 | ASSERT(adapter->MsiEnabled == FALSE); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 880 | /* */ |
| 881 | /* Turn off interrupts by writing to the icr register. */ |
| 882 | /* */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 883 | WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_DISABLE), TRUE); |
| 884 | |
| 885 | adapter->InterruptsEnabled = 0; |
| 886 | |
| 887 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XDisIntr", |
| 888 | adapter, adapter->InterruptsEnabled, 0, 0); |
| 889 | } |
| 890 | |
| 891 | /* |
| 892 | * |
| 893 | * sxg_enable_interrupt |
| 894 | * |
| 895 | * EnableInterrupt Handler |
| 896 | * |
| 897 | * Arguments: |
| 898 | * |
| 899 | * adapter: Our adapter structure |
| 900 | * |
| 901 | * Return Value: |
| 902 | * None. |
| 903 | */ |
| 904 | static void sxg_enable_interrupt(p_adapter_t adapter) |
| 905 | { |
| 906 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "EnIntr", |
| 907 | adapter, adapter->InterruptsEnabled, 0, 0); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 908 | /* For now, RSS is disabled with line based interrupts */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 909 | ASSERT(adapter->RssEnabled == FALSE); |
| 910 | ASSERT(adapter->MsiEnabled == FALSE); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 911 | /* */ |
| 912 | /* Turn on interrupts by writing to the icr register. */ |
| 913 | /* */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 914 | WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_ENABLE), TRUE); |
| 915 | |
| 916 | adapter->InterruptsEnabled = 1; |
| 917 | |
| 918 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XEnIntr", |
| 919 | adapter, 0, 0, 0); |
| 920 | } |
| 921 | |
| 922 | /* |
| 923 | * |
| 924 | * sxg_isr - Process an line-based interrupt |
| 925 | * |
| 926 | * Arguments: |
| 927 | * Context - Our adapter structure |
| 928 | * QueueDefault - Output parameter to queue to default CPU |
| 929 | * TargetCpus - Output bitmap to schedule DPC's |
| 930 | * |
| 931 | * Return Value: |
| 932 | * TRUE if our interrupt |
| 933 | */ |
| 934 | static irqreturn_t sxg_isr(int irq, void *dev_id) |
| 935 | { |
| 936 | p_net_device dev = (p_net_device) dev_id; |
| 937 | p_adapter_t adapter = (p_adapter_t) netdev_priv(dev); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 938 | /* u32 CpuMask = 0, i; */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 939 | |
| 940 | adapter->Stats.NumInts++; |
| 941 | if (adapter->Isr[0] == 0) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 942 | /* The SLIC driver used to experience a number of spurious interrupts */ |
| 943 | /* due to the delay associated with the masking of the interrupt */ |
| 944 | /* (we'd bounce back in here). If we see that again with Sahara, */ |
| 945 | /* add a READ_REG of the Icr register after the WRITE_REG below. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 946 | adapter->Stats.FalseInts++; |
| 947 | return IRQ_NONE; |
| 948 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 949 | /* */ |
| 950 | /* Move the Isr contents and clear the value in */ |
| 951 | /* shared memory, and mask interrupts */ |
| 952 | /* */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 953 | adapter->IsrCopy[0] = adapter->Isr[0]; |
| 954 | adapter->Isr[0] = 0; |
| 955 | WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_MASK), TRUE); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 956 | /* ASSERT(adapter->IsrDpcsPending == 0); */ |
| 957 | #if XXXTODO /* RSS Stuff */ |
| 958 | /* If RSS is enabled and the ISR specifies */ |
| 959 | /* SXG_ISR_EVENT, then schedule DPC's */ |
| 960 | /* based on event queues. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 961 | if (adapter->RssEnabled && (adapter->IsrCopy[0] & SXG_ISR_EVENT)) { |
| 962 | for (i = 0; |
| 963 | i < adapter->RssSystemInfo->ProcessorInfo.RssCpuCount; |
| 964 | i++) { |
| 965 | PSXG_EVENT_RING EventRing = &adapter->EventRings[i]; |
| 966 | PSXG_EVENT Event = |
| 967 | &EventRing->Ring[adapter->NextEvent[i]]; |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 968 | unsigned char Cpu = |
| 969 | adapter->RssSystemInfo->RssIdToCpu[i]; |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 970 | if (Event->Status & EVENT_STATUS_VALID) { |
| 971 | adapter->IsrDpcsPending++; |
| 972 | CpuMask |= (1 << Cpu); |
| 973 | } |
| 974 | } |
| 975 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 976 | /* Now, either schedule the CPUs specified by the CpuMask, */ |
| 977 | /* or queue default */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 978 | if (CpuMask) { |
| 979 | *QueueDefault = FALSE; |
| 980 | } else { |
| 981 | adapter->IsrDpcsPending = 1; |
| 982 | *QueueDefault = TRUE; |
| 983 | } |
| 984 | *TargetCpus = CpuMask; |
| 985 | #endif |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 986 | /* */ |
| 987 | /* There are no DPCs in Linux, so call the handler now */ |
| 988 | /* */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 989 | sxg_handle_interrupt(adapter); |
| 990 | |
| 991 | return IRQ_HANDLED; |
| 992 | } |
| 993 | |
| 994 | static void sxg_handle_interrupt(p_adapter_t adapter) |
| 995 | { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 996 | /* unsigned char RssId = 0; */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 997 | u32 NewIsr; |
| 998 | |
| 999 | if (adapter->Stats.RcvNoBuffer < 5) { |
| 1000 | DBG_ERROR("Enter sxg_handle_interrupt ISR[%x]\n", |
| 1001 | adapter->IsrCopy[0]); |
| 1002 | } |
| 1003 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "HndlIntr", |
| 1004 | adapter, adapter->IsrCopy[0], 0, 0); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1005 | /* For now, RSS is disabled with line based interrupts */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1006 | ASSERT(adapter->RssEnabled == FALSE); |
| 1007 | ASSERT(adapter->MsiEnabled == FALSE); |
| 1008 | ASSERT(adapter->IsrCopy[0]); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1009 | /*/////////////////////////// */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1010 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1011 | /* Always process the event queue. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1012 | sxg_process_event_queue(adapter, |
| 1013 | (adapter->RssEnabled ? /*RssId */ 0 : 0)); |
| 1014 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1015 | #if XXXTODO /* RSS stuff */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1016 | if (--adapter->IsrDpcsPending) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1017 | /* We're done. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1018 | ASSERT(adapter->RssEnabled); |
| 1019 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DPCsPend", |
| 1020 | adapter, 0, 0, 0); |
| 1021 | return; |
| 1022 | } |
| 1023 | #endif |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1024 | /* */ |
| 1025 | /* Last (or only) DPC processes the ISR and clears the interrupt. */ |
| 1026 | /* */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1027 | NewIsr = sxg_process_isr(adapter, 0); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1028 | /* */ |
| 1029 | /* Reenable interrupts */ |
| 1030 | /* */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1031 | adapter->IsrCopy[0] = 0; |
| 1032 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "ClearIsr", |
| 1033 | adapter, NewIsr, 0, 0); |
| 1034 | |
| 1035 | if (adapter->Stats.RcvNoBuffer < 5) { |
| 1036 | DBG_ERROR |
| 1037 | ("Exit sxg_handle_interrupt2 after enabling interrupt\n"); |
| 1038 | } |
| 1039 | |
| 1040 | WRITE_REG(adapter->UcodeRegs[0].Isr, NewIsr, TRUE); |
| 1041 | |
| 1042 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XHndlInt", |
| 1043 | adapter, 0, 0, 0); |
| 1044 | } |
| 1045 | |
| 1046 | /* |
| 1047 | * |
| 1048 | * sxg_process_isr - Process an interrupt. Called from the line-based and |
| 1049 | * message based interrupt DPC routines |
| 1050 | * |
| 1051 | * Arguments: |
| 1052 | * adapter - Our adapter structure |
| 1053 | * Queue - The ISR that needs processing |
| 1054 | * |
| 1055 | * Return Value: |
| 1056 | * None |
| 1057 | */ |
| 1058 | static int sxg_process_isr(p_adapter_t adapter, u32 MessageId) |
| 1059 | { |
| 1060 | u32 Isr = adapter->IsrCopy[MessageId]; |
| 1061 | u32 NewIsr = 0; |
| 1062 | |
| 1063 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "ProcIsr", |
| 1064 | adapter, Isr, 0, 0); |
| 1065 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1066 | /* Error */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1067 | if (Isr & SXG_ISR_ERR) { |
| 1068 | if (Isr & SXG_ISR_PDQF) { |
| 1069 | adapter->Stats.PdqFull++; |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1070 | DBG_ERROR("%s: SXG_ISR_ERR PDQF!!\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1071 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1072 | /* No host buffer */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1073 | if (Isr & SXG_ISR_RMISS) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1074 | /* There is a bunch of code in the SLIC driver which */ |
| 1075 | /* attempts to process more receive events per DPC */ |
| 1076 | /* if we start to fall behind. We'll probably */ |
| 1077 | /* need to do something similar here, but hold */ |
| 1078 | /* off for now. I don't want to make the code more */ |
| 1079 | /* complicated than strictly needed. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1080 | adapter->Stats.RcvNoBuffer++; |
| 1081 | if (adapter->Stats.RcvNoBuffer < 5) { |
| 1082 | DBG_ERROR("%s: SXG_ISR_ERR RMISS!!\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1083 | __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1084 | } |
| 1085 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1086 | /* Card crash */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1087 | if (Isr & SXG_ISR_DEAD) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1088 | /* Set aside the crash info and set the adapter state to RESET */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1089 | adapter->CrashCpu = |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 1090 | (unsigned char)((Isr & SXG_ISR_CPU) >> |
| 1091 | SXG_ISR_CPU_SHIFT); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1092 | adapter->CrashLocation = (ushort) (Isr & SXG_ISR_CRASH); |
| 1093 | adapter->Dead = TRUE; |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1094 | DBG_ERROR("%s: ISR_DEAD %x, CPU: %d\n", __func__, |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1095 | adapter->CrashLocation, adapter->CrashCpu); |
| 1096 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1097 | /* Event ring full */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1098 | if (Isr & SXG_ISR_ERFULL) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1099 | /* Same issue as RMISS, really. This means the */ |
| 1100 | /* host is falling behind the card. Need to increase */ |
| 1101 | /* event ring size, process more events per interrupt, */ |
| 1102 | /* and/or reduce/remove interrupt aggregation. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1103 | adapter->Stats.EventRingFull++; |
| 1104 | DBG_ERROR("%s: SXG_ISR_ERR EVENT RING FULL!!\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1105 | __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1106 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1107 | /* Transmit drop - no DRAM buffers or XMT error */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1108 | if (Isr & SXG_ISR_XDROP) { |
| 1109 | adapter->Stats.XmtDrops++; |
| 1110 | adapter->Stats.XmtErrors++; |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1111 | DBG_ERROR("%s: SXG_ISR_ERR XDROP!!\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1112 | } |
| 1113 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1114 | /* Slowpath send completions */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1115 | if (Isr & SXG_ISR_SPSEND) { |
| 1116 | sxg_complete_slow_send(adapter); |
| 1117 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1118 | /* Dump */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1119 | if (Isr & SXG_ISR_UPC) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1120 | ASSERT(adapter->DumpCmdRunning); /* Maybe change when debug is added.. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1121 | adapter->DumpCmdRunning = FALSE; |
| 1122 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1123 | /* Link event */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1124 | if (Isr & SXG_ISR_LINK) { |
| 1125 | sxg_link_event(adapter); |
| 1126 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1127 | /* Debug - breakpoint hit */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1128 | if (Isr & SXG_ISR_BREAK) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1129 | /* At the moment AGDB isn't written to support interactive */ |
| 1130 | /* debug sessions. When it is, this interrupt will be used */ |
| 1131 | /* to signal AGDB that it has hit a breakpoint. For now, ASSERT. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1132 | ASSERT(0); |
| 1133 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1134 | /* Heartbeat response */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1135 | if (Isr & SXG_ISR_PING) { |
| 1136 | adapter->PingOutstanding = FALSE; |
| 1137 | } |
| 1138 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XProcIsr", |
| 1139 | adapter, Isr, NewIsr, 0); |
| 1140 | |
| 1141 | return (NewIsr); |
| 1142 | } |
| 1143 | |
| 1144 | /* |
| 1145 | * |
| 1146 | * sxg_process_event_queue - Process our event queue |
| 1147 | * |
| 1148 | * Arguments: |
| 1149 | * - adapter - Adapter structure |
| 1150 | * - RssId - The event queue requiring processing |
| 1151 | * |
| 1152 | * Return Value: |
| 1153 | * None. |
| 1154 | */ |
| 1155 | static u32 sxg_process_event_queue(p_adapter_t adapter, u32 RssId) |
| 1156 | { |
| 1157 | PSXG_EVENT_RING EventRing = &adapter->EventRings[RssId]; |
| 1158 | PSXG_EVENT Event = &EventRing->Ring[adapter->NextEvent[RssId]]; |
| 1159 | u32 EventsProcessed = 0, Batches = 0; |
| 1160 | u32 num_skbs = 0; |
| 1161 | struct sk_buff *skb; |
| 1162 | #ifdef LINUX_HANDLES_RCV_INDICATION_LISTS |
| 1163 | struct sk_buff *prev_skb = NULL; |
| 1164 | struct sk_buff *IndicationList[SXG_RCV_ARRAYSIZE]; |
| 1165 | u32 Index; |
| 1166 | PSXG_RCV_DATA_BUFFER_HDR RcvDataBufferHdr; |
| 1167 | #endif |
| 1168 | u32 ReturnStatus = 0; |
| 1169 | |
| 1170 | ASSERT((adapter->State == SXG_STATE_RUNNING) || |
| 1171 | (adapter->State == SXG_STATE_PAUSING) || |
| 1172 | (adapter->State == SXG_STATE_PAUSED) || |
| 1173 | (adapter->State == SXG_STATE_HALTING)); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1174 | /* We may still have unprocessed events on the queue if */ |
| 1175 | /* the card crashed. Don't process them. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1176 | if (adapter->Dead) { |
| 1177 | return (0); |
| 1178 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1179 | /* In theory there should only be a single processor that */ |
| 1180 | /* accesses this queue, and only at interrupt-DPC time. So */ |
| 1181 | /* we shouldn't need a lock for any of this. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1182 | while (Event->Status & EVENT_STATUS_VALID) { |
| 1183 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "Event", |
| 1184 | Event, Event->Code, Event->Status, |
| 1185 | adapter->NextEvent); |
| 1186 | switch (Event->Code) { |
| 1187 | case EVENT_CODE_BUFFERS: |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1188 | ASSERT(!(Event->CommandIndex & 0xFF00)); /* SXG_RING_INFO Head & Tail == unsigned char */ |
| 1189 | /* */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1190 | sxg_complete_descriptor_blocks(adapter, |
| 1191 | Event->CommandIndex); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1192 | /* */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1193 | break; |
| 1194 | case EVENT_CODE_SLOWRCV: |
| 1195 | --adapter->RcvBuffersOnCard; |
| 1196 | if ((skb = sxg_slow_receive(adapter, Event))) { |
| 1197 | u32 rx_bytes; |
| 1198 | #ifdef LINUX_HANDLES_RCV_INDICATION_LISTS |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1199 | /* Add it to our indication list */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1200 | SXG_ADD_RCV_PACKET(adapter, skb, prev_skb, |
| 1201 | IndicationList, num_skbs); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1202 | /* In Linux, we just pass up each skb to the protocol above at this point, */ |
| 1203 | /* there is no capability of an indication list. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1204 | #else |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1205 | /* CHECK skb_pull(skb, INIC_RCVBUF_HEADSIZE); */ |
| 1206 | rx_bytes = Event->Length; /* (rcvbuf->length & IRHDDR_FLEN_MSK); */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1207 | skb_put(skb, rx_bytes); |
| 1208 | adapter->stats.rx_packets++; |
| 1209 | adapter->stats.rx_bytes += rx_bytes; |
| 1210 | #if SXG_OFFLOAD_IP_CHECKSUM |
| 1211 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
| 1212 | #endif |
| 1213 | skb->dev = adapter->netdev; |
| 1214 | skb->protocol = eth_type_trans(skb, skb->dev); |
| 1215 | netif_rx(skb); |
| 1216 | #endif |
| 1217 | } |
| 1218 | break; |
| 1219 | default: |
| 1220 | DBG_ERROR("%s: ERROR Invalid EventCode %d\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1221 | __func__, Event->Code); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1222 | /* ASSERT(0); */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1223 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1224 | /* See if we need to restock card receive buffers. */ |
| 1225 | /* There are two things to note here: */ |
| 1226 | /* First - This test is not SMP safe. The */ |
| 1227 | /* adapter->BuffersOnCard field is protected via atomic interlocked calls, but */ |
| 1228 | /* we do not protect it with respect to these tests. The only way to do that */ |
| 1229 | /* is with a lock, and I don't want to grab a lock every time we adjust the */ |
| 1230 | /* BuffersOnCard count. Instead, we allow the buffer replenishment to be off */ |
| 1231 | /* once in a while. The worst that can happen is the card is given one */ |
| 1232 | /* more-or-less descriptor block than the arbitrary value we've chosen. */ |
| 1233 | /* No big deal */ |
| 1234 | /* In short DO NOT ADD A LOCK HERE, OR WHERE RcvBuffersOnCard is adjusted. */ |
| 1235 | /* Second - We expect this test to rarely evaluate to true. We attempt to */ |
| 1236 | /* refill descriptor blocks as they are returned to us */ |
| 1237 | /* (sxg_complete_descriptor_blocks), so The only time this should evaluate */ |
| 1238 | /* to true is when sxg_complete_descriptor_blocks failed to allocate */ |
| 1239 | /* receive buffers. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1240 | if (adapter->RcvBuffersOnCard < SXG_RCV_DATA_BUFFERS) { |
| 1241 | sxg_stock_rcv_buffers(adapter); |
| 1242 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1243 | /* It's more efficient to just set this to zero. */ |
| 1244 | /* But clearing the top bit saves potential debug info... */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1245 | Event->Status &= ~EVENT_STATUS_VALID; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1246 | /* Advanct to the next event */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1247 | SXG_ADVANCE_INDEX(adapter->NextEvent[RssId], EVENT_RING_SIZE); |
| 1248 | Event = &EventRing->Ring[adapter->NextEvent[RssId]]; |
| 1249 | EventsProcessed++; |
| 1250 | if (EventsProcessed == EVENT_RING_BATCH) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1251 | /* Release a batch of events back to the card */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1252 | WRITE_REG(adapter->UcodeRegs[RssId].EventRelease, |
| 1253 | EVENT_RING_BATCH, FALSE); |
| 1254 | EventsProcessed = 0; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1255 | /* If we've processed our batch limit, break out of the */ |
| 1256 | /* loop and return SXG_ISR_EVENT to arrange for us to */ |
| 1257 | /* be called again */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1258 | if (Batches++ == EVENT_BATCH_LIMIT) { |
| 1259 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, |
| 1260 | TRACE_NOISY, "EvtLimit", Batches, |
| 1261 | adapter->NextEvent, 0, 0); |
| 1262 | ReturnStatus = SXG_ISR_EVENT; |
| 1263 | break; |
| 1264 | } |
| 1265 | } |
| 1266 | } |
| 1267 | #ifdef LINUX_HANDLES_RCV_INDICATION_LISTS |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1268 | /* */ |
| 1269 | /* Indicate any received dumb-nic frames */ |
| 1270 | /* */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1271 | SXG_INDICATE_PACKETS(adapter, IndicationList, num_skbs); |
| 1272 | #endif |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1273 | /* */ |
| 1274 | /* Release events back to the card. */ |
| 1275 | /* */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1276 | if (EventsProcessed) { |
| 1277 | WRITE_REG(adapter->UcodeRegs[RssId].EventRelease, |
| 1278 | EventsProcessed, FALSE); |
| 1279 | } |
| 1280 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XPrcEvnt", |
| 1281 | Batches, EventsProcessed, adapter->NextEvent, num_skbs); |
| 1282 | |
| 1283 | return (ReturnStatus); |
| 1284 | } |
| 1285 | |
| 1286 | /* |
| 1287 | * sxg_complete_slow_send - Complete slowpath or dumb-nic sends |
| 1288 | * |
| 1289 | * Arguments - |
| 1290 | * adapter - A pointer to our adapter structure |
| 1291 | |
| 1292 | * Return |
| 1293 | * None |
| 1294 | */ |
| 1295 | static void sxg_complete_slow_send(p_adapter_t adapter) |
| 1296 | { |
| 1297 | PSXG_XMT_RING XmtRing = &adapter->XmtRings[0]; |
| 1298 | PSXG_RING_INFO XmtRingInfo = &adapter->XmtRingZeroInfo; |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 1299 | u32 *ContextType; |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1300 | PSXG_CMD XmtCmd; |
| 1301 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1302 | /* NOTE - This lock is dropped and regrabbed in this loop. */ |
| 1303 | /* This means two different processors can both be running */ |
| 1304 | /* through this loop. Be *very* careful. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1305 | spin_lock(&adapter->XmtZeroLock); |
| 1306 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpSnds", |
| 1307 | adapter, XmtRingInfo->Head, XmtRingInfo->Tail, 0); |
| 1308 | |
| 1309 | while (XmtRingInfo->Tail != *adapter->XmtRingZeroIndex) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1310 | /* Locate the current Cmd (ring descriptor entry), and */ |
| 1311 | /* associated SGL, and advance the tail */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1312 | SXG_RETURN_CMD(XmtRing, XmtRingInfo, XmtCmd, ContextType); |
| 1313 | ASSERT(ContextType); |
| 1314 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpSnd", |
| 1315 | XmtRingInfo->Head, XmtRingInfo->Tail, XmtCmd, 0); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1316 | /* Clear the SGL field. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1317 | XmtCmd->Sgl = 0; |
| 1318 | |
| 1319 | switch (*ContextType) { |
| 1320 | case SXG_SGL_DUMB: |
| 1321 | { |
| 1322 | struct sk_buff *skb; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1323 | /* Dumb-nic send. Command context is the dumb-nic SGL */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1324 | skb = (struct sk_buff *)ContextType; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1325 | /* Complete the send */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1326 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, |
| 1327 | TRACE_IMPORTANT, "DmSndCmp", skb, 0, |
| 1328 | 0, 0); |
| 1329 | ASSERT(adapter->Stats.XmtQLen); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1330 | adapter->Stats.XmtQLen--; /* within XmtZeroLock */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1331 | adapter->Stats.XmtOk++; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1332 | /* Now drop the lock and complete the send back to */ |
| 1333 | /* Microsoft. We need to drop the lock because */ |
| 1334 | /* Microsoft can come back with a chimney send, which */ |
| 1335 | /* results in a double trip in SxgTcpOuput */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1336 | spin_unlock(&adapter->XmtZeroLock); |
| 1337 | SXG_COMPLETE_DUMB_SEND(adapter, skb); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1338 | /* and reacquire.. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1339 | spin_lock(&adapter->XmtZeroLock); |
| 1340 | } |
| 1341 | break; |
| 1342 | default: |
| 1343 | ASSERT(0); |
| 1344 | } |
| 1345 | } |
| 1346 | spin_unlock(&adapter->XmtZeroLock); |
| 1347 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpSnd", |
| 1348 | adapter, XmtRingInfo->Head, XmtRingInfo->Tail, 0); |
| 1349 | } |
| 1350 | |
| 1351 | /* |
| 1352 | * sxg_slow_receive |
| 1353 | * |
| 1354 | * Arguments - |
| 1355 | * adapter - A pointer to our adapter structure |
| 1356 | * Event - Receive event |
| 1357 | * |
| 1358 | * Return |
| 1359 | * skb |
| 1360 | */ |
| 1361 | static struct sk_buff *sxg_slow_receive(p_adapter_t adapter, PSXG_EVENT Event) |
| 1362 | { |
| 1363 | PSXG_RCV_DATA_BUFFER_HDR RcvDataBufferHdr; |
| 1364 | struct sk_buff *Packet; |
| 1365 | |
| 1366 | RcvDataBufferHdr = (PSXG_RCV_DATA_BUFFER_HDR) Event->HostHandle; |
| 1367 | ASSERT(RcvDataBufferHdr); |
| 1368 | ASSERT(RcvDataBufferHdr->State == SXG_BUFFER_ONCARD); |
| 1369 | ASSERT(SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr) == |
| 1370 | RcvDataBufferHdr->VirtualAddress); |
| 1371 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "SlowRcv", Event, |
| 1372 | RcvDataBufferHdr, RcvDataBufferHdr->State, |
| 1373 | RcvDataBufferHdr->VirtualAddress); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1374 | /* Drop rcv frames in non-running state */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1375 | switch (adapter->State) { |
| 1376 | case SXG_STATE_RUNNING: |
| 1377 | break; |
| 1378 | case SXG_STATE_PAUSING: |
| 1379 | case SXG_STATE_PAUSED: |
| 1380 | case SXG_STATE_HALTING: |
| 1381 | goto drop; |
| 1382 | default: |
| 1383 | ASSERT(0); |
| 1384 | goto drop; |
| 1385 | } |
| 1386 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1387 | /* Change buffer state to UPSTREAM */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1388 | RcvDataBufferHdr->State = SXG_BUFFER_UPSTREAM; |
| 1389 | if (Event->Status & EVENT_STATUS_RCVERR) { |
| 1390 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RcvError", |
| 1391 | Event, Event->Status, Event->HostHandle, 0); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1392 | /* XXXTODO - Remove this print later */ |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 1393 | DBG_ERROR("SXG: Receive error %x\n", *(u32 *) |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1394 | SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr)); |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 1395 | sxg_process_rcv_error(adapter, *(u32 *) |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1396 | SXG_RECEIVE_DATA_LOCATION |
| 1397 | (RcvDataBufferHdr)); |
| 1398 | goto drop; |
| 1399 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1400 | #if XXXTODO /* VLAN stuff */ |
| 1401 | /* If there's a VLAN tag, extract it and validate it */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1402 | if (((p_ether_header) (SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr)))-> |
| 1403 | EtherType == ETHERTYPE_VLAN) { |
| 1404 | if (SxgExtractVlanHeader(adapter, RcvDataBufferHdr, Event) != |
| 1405 | STATUS_SUCCESS) { |
| 1406 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, |
| 1407 | "BadVlan", Event, |
| 1408 | SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr), |
| 1409 | Event->Length, 0); |
| 1410 | goto drop; |
| 1411 | } |
| 1412 | } |
| 1413 | #endif |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1414 | /* */ |
| 1415 | /* Dumb-nic frame. See if it passes our mac filter and update stats */ |
| 1416 | /* */ |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 1417 | if (!sxg_mac_filter(adapter, (p_ether_header) |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1418 | SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr), |
| 1419 | Event->Length)) { |
| 1420 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RcvFiltr", |
| 1421 | Event, SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr), |
| 1422 | Event->Length, 0); |
| 1423 | goto drop; |
| 1424 | } |
| 1425 | |
| 1426 | Packet = RcvDataBufferHdr->SxgDumbRcvPacket; |
| 1427 | |
| 1428 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "DumbRcv", |
| 1429 | RcvDataBufferHdr, Packet, Event->Length, 0); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1430 | /* */ |
| 1431 | /* Lastly adjust the receive packet length. */ |
| 1432 | /* */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1433 | SXG_ADJUST_RCV_PACKET(Packet, RcvDataBufferHdr, Event); |
| 1434 | |
| 1435 | return (Packet); |
| 1436 | |
| 1437 | drop: |
| 1438 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DropRcv", |
| 1439 | RcvDataBufferHdr, Event->Length, 0, 0); |
| 1440 | adapter->Stats.RcvDiscards++; |
| 1441 | spin_lock(&adapter->RcvQLock); |
| 1442 | SXG_FREE_RCV_DATA_BUFFER(adapter, RcvDataBufferHdr); |
| 1443 | spin_unlock(&adapter->RcvQLock); |
| 1444 | return (NULL); |
| 1445 | } |
| 1446 | |
| 1447 | /* |
| 1448 | * sxg_process_rcv_error - process receive error and update |
| 1449 | * stats |
| 1450 | * |
| 1451 | * Arguments: |
| 1452 | * adapter - Adapter structure |
| 1453 | * ErrorStatus - 4-byte receive error status |
| 1454 | * |
| 1455 | * Return Value: |
| 1456 | * None |
| 1457 | */ |
| 1458 | static void sxg_process_rcv_error(p_adapter_t adapter, u32 ErrorStatus) |
| 1459 | { |
| 1460 | u32 Error; |
| 1461 | |
| 1462 | adapter->Stats.RcvErrors++; |
| 1463 | |
| 1464 | if (ErrorStatus & SXG_RCV_STATUS_TRANSPORT_ERROR) { |
| 1465 | Error = ErrorStatus & SXG_RCV_STATUS_TRANSPORT_MASK; |
| 1466 | switch (Error) { |
| 1467 | case SXG_RCV_STATUS_TRANSPORT_CSUM: |
| 1468 | adapter->Stats.TransportCsum++; |
| 1469 | break; |
| 1470 | case SXG_RCV_STATUS_TRANSPORT_UFLOW: |
| 1471 | adapter->Stats.TransportUflow++; |
| 1472 | break; |
| 1473 | case SXG_RCV_STATUS_TRANSPORT_HDRLEN: |
| 1474 | adapter->Stats.TransportHdrLen++; |
| 1475 | break; |
| 1476 | } |
| 1477 | } |
| 1478 | if (ErrorStatus & SXG_RCV_STATUS_NETWORK_ERROR) { |
| 1479 | Error = ErrorStatus & SXG_RCV_STATUS_NETWORK_MASK; |
| 1480 | switch (Error) { |
| 1481 | case SXG_RCV_STATUS_NETWORK_CSUM: |
| 1482 | adapter->Stats.NetworkCsum++; |
| 1483 | break; |
| 1484 | case SXG_RCV_STATUS_NETWORK_UFLOW: |
| 1485 | adapter->Stats.NetworkUflow++; |
| 1486 | break; |
| 1487 | case SXG_RCV_STATUS_NETWORK_HDRLEN: |
| 1488 | adapter->Stats.NetworkHdrLen++; |
| 1489 | break; |
| 1490 | } |
| 1491 | } |
| 1492 | if (ErrorStatus & SXG_RCV_STATUS_PARITY) { |
| 1493 | adapter->Stats.Parity++; |
| 1494 | } |
| 1495 | if (ErrorStatus & SXG_RCV_STATUS_LINK_ERROR) { |
| 1496 | Error = ErrorStatus & SXG_RCV_STATUS_LINK_MASK; |
| 1497 | switch (Error) { |
| 1498 | case SXG_RCV_STATUS_LINK_PARITY: |
| 1499 | adapter->Stats.LinkParity++; |
| 1500 | break; |
| 1501 | case SXG_RCV_STATUS_LINK_EARLY: |
| 1502 | adapter->Stats.LinkEarly++; |
| 1503 | break; |
| 1504 | case SXG_RCV_STATUS_LINK_BUFOFLOW: |
| 1505 | adapter->Stats.LinkBufOflow++; |
| 1506 | break; |
| 1507 | case SXG_RCV_STATUS_LINK_CODE: |
| 1508 | adapter->Stats.LinkCode++; |
| 1509 | break; |
| 1510 | case SXG_RCV_STATUS_LINK_DRIBBLE: |
| 1511 | adapter->Stats.LinkDribble++; |
| 1512 | break; |
| 1513 | case SXG_RCV_STATUS_LINK_CRC: |
| 1514 | adapter->Stats.LinkCrc++; |
| 1515 | break; |
| 1516 | case SXG_RCV_STATUS_LINK_OFLOW: |
| 1517 | adapter->Stats.LinkOflow++; |
| 1518 | break; |
| 1519 | case SXG_RCV_STATUS_LINK_UFLOW: |
| 1520 | adapter->Stats.LinkUflow++; |
| 1521 | break; |
| 1522 | } |
| 1523 | } |
| 1524 | } |
| 1525 | |
| 1526 | /* |
| 1527 | * sxg_mac_filter |
| 1528 | * |
| 1529 | * Arguments: |
| 1530 | * adapter - Adapter structure |
| 1531 | * pether - Ethernet header |
| 1532 | * length - Frame length |
| 1533 | * |
| 1534 | * Return Value: |
| 1535 | * TRUE if the frame is to be allowed |
| 1536 | */ |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 1537 | static bool sxg_mac_filter(p_adapter_t adapter, p_ether_header EtherHdr, |
| 1538 | ushort length) |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1539 | { |
| 1540 | bool EqualAddr; |
| 1541 | |
| 1542 | if (SXG_MULTICAST_PACKET(EtherHdr)) { |
| 1543 | if (SXG_BROADCAST_PACKET(EtherHdr)) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1544 | /* broadcast */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1545 | if (adapter->MacFilter & MAC_BCAST) { |
| 1546 | adapter->Stats.DumbRcvBcastPkts++; |
| 1547 | adapter->Stats.DumbRcvBcastBytes += length; |
| 1548 | adapter->Stats.DumbRcvPkts++; |
| 1549 | adapter->Stats.DumbRcvBytes += length; |
| 1550 | return (TRUE); |
| 1551 | } |
| 1552 | } else { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1553 | /* multicast */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1554 | if (adapter->MacFilter & MAC_ALLMCAST) { |
| 1555 | adapter->Stats.DumbRcvMcastPkts++; |
| 1556 | adapter->Stats.DumbRcvMcastBytes += length; |
| 1557 | adapter->Stats.DumbRcvPkts++; |
| 1558 | adapter->Stats.DumbRcvBytes += length; |
| 1559 | return (TRUE); |
| 1560 | } |
| 1561 | if (adapter->MacFilter & MAC_MCAST) { |
| 1562 | PSXG_MULTICAST_ADDRESS MulticastAddrs = |
| 1563 | adapter->MulticastAddrs; |
| 1564 | while (MulticastAddrs) { |
| 1565 | ETHER_EQ_ADDR(MulticastAddrs->Address, |
| 1566 | EtherHdr->ether_dhost, |
| 1567 | EqualAddr); |
| 1568 | if (EqualAddr) { |
| 1569 | adapter->Stats. |
| 1570 | DumbRcvMcastPkts++; |
| 1571 | adapter->Stats. |
| 1572 | DumbRcvMcastBytes += length; |
| 1573 | adapter->Stats.DumbRcvPkts++; |
| 1574 | adapter->Stats.DumbRcvBytes += |
| 1575 | length; |
| 1576 | return (TRUE); |
| 1577 | } |
| 1578 | MulticastAddrs = MulticastAddrs->Next; |
| 1579 | } |
| 1580 | } |
| 1581 | } |
| 1582 | } else if (adapter->MacFilter & MAC_DIRECTED) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1583 | /* Not broadcast or multicast. Must be directed at us or */ |
| 1584 | /* the card is in promiscuous mode. Either way, consider it */ |
| 1585 | /* ours if MAC_DIRECTED is set */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1586 | adapter->Stats.DumbRcvUcastPkts++; |
| 1587 | adapter->Stats.DumbRcvUcastBytes += length; |
| 1588 | adapter->Stats.DumbRcvPkts++; |
| 1589 | adapter->Stats.DumbRcvBytes += length; |
| 1590 | return (TRUE); |
| 1591 | } |
| 1592 | if (adapter->MacFilter & MAC_PROMISC) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1593 | /* Whatever it is, keep it. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1594 | adapter->Stats.DumbRcvPkts++; |
| 1595 | adapter->Stats.DumbRcvBytes += length; |
| 1596 | return (TRUE); |
| 1597 | } |
| 1598 | adapter->Stats.RcvDiscards++; |
| 1599 | return (FALSE); |
| 1600 | } |
| 1601 | |
| 1602 | static int sxg_register_interrupt(p_adapter_t adapter) |
| 1603 | { |
| 1604 | if (!adapter->intrregistered) { |
| 1605 | int retval; |
| 1606 | |
| 1607 | DBG_ERROR |
| 1608 | ("sxg: %s AllocAdaptRsrcs adapter[%p] dev->irq[%x] %x\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1609 | __func__, adapter, adapter->netdev->irq, NR_IRQS); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1610 | |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 1611 | spin_unlock_irqrestore(&sxg_global.driver_lock, |
| 1612 | sxg_global.flags); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1613 | |
| 1614 | retval = request_irq(adapter->netdev->irq, |
| 1615 | &sxg_isr, |
| 1616 | IRQF_SHARED, |
| 1617 | adapter->netdev->name, adapter->netdev); |
| 1618 | |
| 1619 | spin_lock_irqsave(&sxg_global.driver_lock, sxg_global.flags); |
| 1620 | |
| 1621 | if (retval) { |
| 1622 | DBG_ERROR("sxg: request_irq (%s) FAILED [%x]\n", |
| 1623 | adapter->netdev->name, retval); |
| 1624 | return (retval); |
| 1625 | } |
| 1626 | adapter->intrregistered = 1; |
| 1627 | adapter->IntRegistered = TRUE; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1628 | /* Disable RSS with line-based interrupts */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1629 | adapter->MsiEnabled = FALSE; |
| 1630 | adapter->RssEnabled = FALSE; |
| 1631 | DBG_ERROR("sxg: %s AllocAdaptRsrcs adapter[%p] dev->irq[%x]\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1632 | __func__, adapter, adapter->netdev->irq); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1633 | } |
| 1634 | return (STATUS_SUCCESS); |
| 1635 | } |
| 1636 | |
| 1637 | static void sxg_deregister_interrupt(p_adapter_t adapter) |
| 1638 | { |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1639 | DBG_ERROR("sxg: %s ENTER adapter[%p]\n", __func__, adapter); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1640 | #if XXXTODO |
| 1641 | slic_init_cleanup(adapter); |
| 1642 | #endif |
| 1643 | memset(&adapter->stats, 0, sizeof(struct net_device_stats)); |
| 1644 | adapter->error_interrupts = 0; |
| 1645 | adapter->rcv_interrupts = 0; |
| 1646 | adapter->xmit_interrupts = 0; |
| 1647 | adapter->linkevent_interrupts = 0; |
| 1648 | adapter->upr_interrupts = 0; |
| 1649 | adapter->num_isrs = 0; |
| 1650 | adapter->xmit_completes = 0; |
| 1651 | adapter->rcv_broadcasts = 0; |
| 1652 | adapter->rcv_multicasts = 0; |
| 1653 | adapter->rcv_unicasts = 0; |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1654 | DBG_ERROR("sxg: %s EXIT\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1655 | } |
| 1656 | |
| 1657 | /* |
| 1658 | * sxg_if_init |
| 1659 | * |
| 1660 | * Perform initialization of our slic interface. |
| 1661 | * |
| 1662 | */ |
| 1663 | static int sxg_if_init(p_adapter_t adapter) |
| 1664 | { |
| 1665 | p_net_device dev = adapter->netdev; |
| 1666 | int status = 0; |
| 1667 | |
| 1668 | DBG_ERROR("sxg: %s (%s) ENTER states[%d:%d:%d] flags[%x]\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1669 | __func__, adapter->netdev->name, |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1670 | adapter->queues_initialized, adapter->state, |
| 1671 | adapter->linkstate, dev->flags); |
| 1672 | |
| 1673 | /* adapter should be down at this point */ |
| 1674 | if (adapter->state != ADAPT_DOWN) { |
| 1675 | DBG_ERROR("sxg_if_init adapter->state != ADAPT_DOWN\n"); |
| 1676 | return (-EIO); |
| 1677 | } |
| 1678 | ASSERT(adapter->linkstate == LINK_DOWN); |
| 1679 | |
| 1680 | adapter->devflags_prev = dev->flags; |
| 1681 | adapter->macopts = MAC_DIRECTED; |
| 1682 | if (dev->flags) { |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1683 | DBG_ERROR("sxg: %s (%s) Set MAC options: ", __func__, |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1684 | adapter->netdev->name); |
| 1685 | if (dev->flags & IFF_BROADCAST) { |
| 1686 | adapter->macopts |= MAC_BCAST; |
| 1687 | DBG_ERROR("BCAST "); |
| 1688 | } |
| 1689 | if (dev->flags & IFF_PROMISC) { |
| 1690 | adapter->macopts |= MAC_PROMISC; |
| 1691 | DBG_ERROR("PROMISC "); |
| 1692 | } |
| 1693 | if (dev->flags & IFF_ALLMULTI) { |
| 1694 | adapter->macopts |= MAC_ALLMCAST; |
| 1695 | DBG_ERROR("ALL_MCAST "); |
| 1696 | } |
| 1697 | if (dev->flags & IFF_MULTICAST) { |
| 1698 | adapter->macopts |= MAC_MCAST; |
| 1699 | DBG_ERROR("MCAST "); |
| 1700 | } |
| 1701 | DBG_ERROR("\n"); |
| 1702 | } |
| 1703 | status = sxg_register_interrupt(adapter); |
| 1704 | if (status != STATUS_SUCCESS) { |
| 1705 | DBG_ERROR("sxg_if_init: sxg_register_interrupt FAILED %x\n", |
| 1706 | status); |
| 1707 | sxg_deregister_interrupt(adapter); |
| 1708 | return (status); |
| 1709 | } |
| 1710 | |
| 1711 | adapter->state = ADAPT_UP; |
| 1712 | |
| 1713 | /* |
| 1714 | * clear any pending events, then enable interrupts |
| 1715 | */ |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1716 | DBG_ERROR("sxg: %s ENABLE interrupts(slic)\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1717 | |
| 1718 | return (STATUS_SUCCESS); |
| 1719 | } |
| 1720 | |
| 1721 | static int sxg_entry_open(p_net_device dev) |
| 1722 | { |
| 1723 | p_adapter_t adapter = (p_adapter_t) netdev_priv(dev); |
| 1724 | int status; |
| 1725 | |
| 1726 | ASSERT(adapter); |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1727 | DBG_ERROR("sxg: %s adapter->activated[%d]\n", __func__, |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1728 | adapter->activated); |
| 1729 | DBG_ERROR |
| 1730 | ("sxg: %s (%s): [jiffies[%lx] cpu %d] dev[%p] adapt[%p] port[%d]\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1731 | __func__, adapter->netdev->name, jiffies, smp_processor_id(), |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1732 | adapter->netdev, adapter, adapter->port); |
| 1733 | |
| 1734 | netif_stop_queue(adapter->netdev); |
| 1735 | |
| 1736 | spin_lock_irqsave(&sxg_global.driver_lock, sxg_global.flags); |
| 1737 | if (!adapter->activated) { |
| 1738 | sxg_global.num_sxg_ports_active++; |
| 1739 | adapter->activated = 1; |
| 1740 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1741 | /* Initialize the adapter */ |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1742 | DBG_ERROR("sxg: %s ENTER sxg_initialize_adapter\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1743 | status = sxg_initialize_adapter(adapter); |
| 1744 | DBG_ERROR("sxg: %s EXIT sxg_initialize_adapter status[%x]\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1745 | __func__, status); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1746 | |
| 1747 | if (status == STATUS_SUCCESS) { |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1748 | DBG_ERROR("sxg: %s ENTER sxg_if_init\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1749 | status = sxg_if_init(adapter); |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1750 | DBG_ERROR("sxg: %s EXIT sxg_if_init status[%x]\n", __func__, |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1751 | status); |
| 1752 | } |
| 1753 | |
| 1754 | if (status != STATUS_SUCCESS) { |
| 1755 | if (adapter->activated) { |
| 1756 | sxg_global.num_sxg_ports_active--; |
| 1757 | adapter->activated = 0; |
| 1758 | } |
| 1759 | spin_unlock_irqrestore(&sxg_global.driver_lock, |
| 1760 | sxg_global.flags); |
| 1761 | return (status); |
| 1762 | } |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1763 | DBG_ERROR("sxg: %s ENABLE ALL INTERRUPTS\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1764 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1765 | /* Enable interrupts */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1766 | SXG_ENABLE_ALL_INTERRUPTS(adapter); |
| 1767 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1768 | DBG_ERROR("sxg: %s EXIT\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1769 | |
| 1770 | spin_unlock_irqrestore(&sxg_global.driver_lock, sxg_global.flags); |
| 1771 | return STATUS_SUCCESS; |
| 1772 | } |
| 1773 | |
| 1774 | static void __devexit sxg_entry_remove(struct pci_dev *pcidev) |
| 1775 | { |
| 1776 | p_net_device dev = pci_get_drvdata(pcidev); |
| 1777 | u32 mmio_start = 0; |
| 1778 | unsigned int mmio_len = 0; |
| 1779 | p_adapter_t adapter = (p_adapter_t) netdev_priv(dev); |
| 1780 | |
| 1781 | ASSERT(adapter); |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1782 | DBG_ERROR("sxg: %s ENTER dev[%p] adapter[%p]\n", __func__, dev, |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1783 | adapter); |
| 1784 | sxg_deregister_interrupt(adapter); |
| 1785 | sxg_unmap_mmio_space(adapter); |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1786 | DBG_ERROR("sxg: %s unregister_netdev\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1787 | unregister_netdev(dev); |
| 1788 | |
| 1789 | mmio_start = pci_resource_start(pcidev, 0); |
| 1790 | mmio_len = pci_resource_len(pcidev, 0); |
| 1791 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1792 | DBG_ERROR("sxg: %s rel_region(0) start[%x] len[%x]\n", __func__, |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1793 | mmio_start, mmio_len); |
| 1794 | release_mem_region(mmio_start, mmio_len); |
| 1795 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1796 | DBG_ERROR("sxg: %s iounmap dev->base_addr[%x]\n", __func__, |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 1797 | (unsigned int)dev->base_addr); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1798 | iounmap((char *)dev->base_addr); |
| 1799 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1800 | DBG_ERROR("sxg: %s deallocate device\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1801 | kfree(dev); |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1802 | DBG_ERROR("sxg: %s EXIT\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1803 | } |
| 1804 | |
| 1805 | static int sxg_entry_halt(p_net_device dev) |
| 1806 | { |
| 1807 | p_adapter_t adapter = (p_adapter_t) netdev_priv(dev); |
| 1808 | |
| 1809 | spin_lock_irqsave(&sxg_global.driver_lock, sxg_global.flags); |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1810 | DBG_ERROR("sxg: %s (%s) ENTER\n", __func__, dev->name); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1811 | |
| 1812 | netif_stop_queue(adapter->netdev); |
| 1813 | adapter->state = ADAPT_DOWN; |
| 1814 | adapter->linkstate = LINK_DOWN; |
| 1815 | adapter->devflags_prev = 0; |
| 1816 | DBG_ERROR("sxg: %s (%s) set adapter[%p] state to ADAPT_DOWN(%d)\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1817 | __func__, dev->name, adapter, adapter->state); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1818 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1819 | DBG_ERROR("sxg: %s (%s) EXIT\n", __func__, dev->name); |
| 1820 | DBG_ERROR("sxg: %s EXIT\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1821 | spin_unlock_irqrestore(&sxg_global.driver_lock, sxg_global.flags); |
| 1822 | return (STATUS_SUCCESS); |
| 1823 | } |
| 1824 | |
| 1825 | static int sxg_ioctl(p_net_device dev, struct ifreq *rq, int cmd) |
| 1826 | { |
| 1827 | ASSERT(rq); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1828 | /* DBG_ERROR("sxg: %s cmd[%x] rq[%p] dev[%p]\n", __func__, cmd, rq, dev); */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1829 | switch (cmd) { |
| 1830 | case SIOCSLICSETINTAGG: |
| 1831 | { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1832 | /* p_adapter_t adapter = (p_adapter_t) netdev_priv(dev); */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1833 | u32 data[7]; |
| 1834 | u32 intagg; |
| 1835 | |
| 1836 | if (copy_from_user(data, rq->ifr_data, 28)) { |
| 1837 | DBG_ERROR |
| 1838 | ("copy_from_user FAILED getting initial params\n"); |
| 1839 | return -EFAULT; |
| 1840 | } |
| 1841 | intagg = data[0]; |
| 1842 | printk(KERN_EMERG |
| 1843 | "%s: set interrupt aggregation to %d\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1844 | __func__, intagg); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1845 | return 0; |
| 1846 | } |
| 1847 | |
| 1848 | default: |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1849 | /* DBG_ERROR("sxg: %s UNSUPPORTED[%x]\n", __func__, cmd); */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1850 | return -EOPNOTSUPP; |
| 1851 | } |
| 1852 | return 0; |
| 1853 | } |
| 1854 | |
| 1855 | #define NORMAL_ETHFRAME 0 |
| 1856 | |
| 1857 | /* |
| 1858 | * |
| 1859 | * sxg_send_packets - Send a skb packet |
| 1860 | * |
| 1861 | * Arguments: |
| 1862 | * skb - The packet to send |
| 1863 | * dev - Our linux net device that refs our adapter |
| 1864 | * |
| 1865 | * Return: |
| 1866 | * 0 regardless of outcome XXXTODO refer to e1000 driver |
| 1867 | */ |
| 1868 | static int sxg_send_packets(struct sk_buff *skb, p_net_device dev) |
| 1869 | { |
| 1870 | p_adapter_t adapter = (p_adapter_t) netdev_priv(dev); |
| 1871 | u32 status = STATUS_SUCCESS; |
| 1872 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1873 | DBG_ERROR("sxg: %s ENTER sxg_send_packets skb[%p]\n", __func__, |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1874 | skb); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1875 | /* Check the adapter state */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1876 | switch (adapter->State) { |
| 1877 | case SXG_STATE_INITIALIZING: |
| 1878 | case SXG_STATE_HALTED: |
| 1879 | case SXG_STATE_SHUTDOWN: |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1880 | ASSERT(0); /* unexpected */ |
| 1881 | /* fall through */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1882 | case SXG_STATE_RESETTING: |
| 1883 | case SXG_STATE_SLEEP: |
| 1884 | case SXG_STATE_BOOTDIAG: |
| 1885 | case SXG_STATE_DIAG: |
| 1886 | case SXG_STATE_HALTING: |
| 1887 | status = STATUS_FAILURE; |
| 1888 | break; |
| 1889 | case SXG_STATE_RUNNING: |
| 1890 | if (adapter->LinkState != SXG_LINK_UP) { |
| 1891 | status = STATUS_FAILURE; |
| 1892 | } |
| 1893 | break; |
| 1894 | default: |
| 1895 | ASSERT(0); |
| 1896 | status = STATUS_FAILURE; |
| 1897 | } |
| 1898 | if (status != STATUS_SUCCESS) { |
| 1899 | goto xmit_fail; |
| 1900 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1901 | /* send a packet */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1902 | status = sxg_transmit_packet(adapter, skb); |
| 1903 | if (status == STATUS_SUCCESS) { |
| 1904 | goto xmit_done; |
| 1905 | } |
| 1906 | |
| 1907 | xmit_fail: |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1908 | /* reject & complete all the packets if they cant be sent */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1909 | if (status != STATUS_SUCCESS) { |
| 1910 | #if XXXTODO |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1911 | /* sxg_send_packets_fail(adapter, skb, status); */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1912 | #else |
| 1913 | SXG_DROP_DUMB_SEND(adapter, skb); |
| 1914 | adapter->stats.tx_dropped++; |
| 1915 | #endif |
| 1916 | } |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 1917 | DBG_ERROR("sxg: %s EXIT sxg_send_packets status[%x]\n", __func__, |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1918 | status); |
| 1919 | |
| 1920 | xmit_done: |
| 1921 | return 0; |
| 1922 | } |
| 1923 | |
| 1924 | /* |
| 1925 | * sxg_transmit_packet |
| 1926 | * |
| 1927 | * This function transmits a single packet. |
| 1928 | * |
| 1929 | * Arguments - |
| 1930 | * adapter - Pointer to our adapter structure |
| 1931 | * skb - The packet to be sent |
| 1932 | * |
| 1933 | * Return - |
| 1934 | * STATUS of send |
| 1935 | */ |
| 1936 | static int sxg_transmit_packet(p_adapter_t adapter, struct sk_buff *skb) |
| 1937 | { |
| 1938 | PSCATTER_GATHER_LIST pSgl; |
| 1939 | PSXG_SCATTER_GATHER SxgSgl; |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 1940 | void *SglBuffer; |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1941 | u32 SglBufferLength; |
| 1942 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1943 | /* The vast majority of work is done in the shared */ |
| 1944 | /* sxg_dumb_sgl routine. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1945 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbSend", |
| 1946 | adapter, skb, 0, 0); |
| 1947 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1948 | /* Allocate a SGL buffer */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1949 | SXG_GET_SGL_BUFFER(adapter, SxgSgl); |
| 1950 | if (!SxgSgl) { |
| 1951 | adapter->Stats.NoSglBuf++; |
| 1952 | adapter->Stats.XmtErrors++; |
| 1953 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "SndPktF1", |
| 1954 | adapter, skb, 0, 0); |
| 1955 | return (STATUS_RESOURCES); |
| 1956 | } |
| 1957 | ASSERT(SxgSgl->adapter == adapter); |
| 1958 | SglBuffer = SXG_SGL_BUFFER(SxgSgl); |
| 1959 | SglBufferLength = SXG_SGL_BUF_SIZE; |
| 1960 | SxgSgl->VlanTag.VlanTci = 0; |
| 1961 | SxgSgl->VlanTag.VlanTpid = 0; |
| 1962 | SxgSgl->Type = SXG_SGL_DUMB; |
| 1963 | SxgSgl->DumbPacket = skb; |
| 1964 | pSgl = NULL; |
| 1965 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1966 | /* Call the common sxg_dumb_sgl routine to complete the send. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1967 | sxg_dumb_sgl(pSgl, SxgSgl); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1968 | /* Return success sxg_dumb_sgl (or something later) will complete it. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1969 | return (STATUS_SUCCESS); |
| 1970 | } |
| 1971 | |
| 1972 | /* |
| 1973 | * sxg_dumb_sgl |
| 1974 | * |
| 1975 | * Arguments: |
| 1976 | * pSgl - |
| 1977 | * SxgSgl - SXG_SCATTER_GATHER |
| 1978 | * |
| 1979 | * Return Value: |
| 1980 | * None. |
| 1981 | */ |
| 1982 | static void sxg_dumb_sgl(PSCATTER_GATHER_LIST pSgl, PSXG_SCATTER_GATHER SxgSgl) |
| 1983 | { |
| 1984 | p_adapter_t adapter = SxgSgl->adapter; |
| 1985 | struct sk_buff *skb = SxgSgl->DumbPacket; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1986 | /* For now, all dumb-nic sends go on RSS queue zero */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1987 | PSXG_XMT_RING XmtRing = &adapter->XmtRings[0]; |
| 1988 | PSXG_RING_INFO XmtRingInfo = &adapter->XmtRingZeroInfo; |
| 1989 | PSXG_CMD XmtCmd = NULL; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1990 | /* u32 Index = 0; */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1991 | u32 DataLength = skb->len; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1992 | /* unsigned int BufLen; */ |
| 1993 | /* u32 SglOffset; */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 1994 | u64 phys_addr; |
| 1995 | |
| 1996 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbSgl", |
| 1997 | pSgl, SxgSgl, 0, 0); |
| 1998 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 1999 | /* Set aside a pointer to the sgl */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2000 | SxgSgl->pSgl = pSgl; |
| 2001 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2002 | /* Sanity check that our SGL format is as we expect. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2003 | ASSERT(sizeof(SXG_X64_SGE) == sizeof(SCATTER_GATHER_ELEMENT)); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2004 | /* Shouldn't be a vlan tag on this frame */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2005 | ASSERT(SxgSgl->VlanTag.VlanTci == 0); |
| 2006 | ASSERT(SxgSgl->VlanTag.VlanTpid == 0); |
| 2007 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2008 | /* From here below we work with the SGL placed in our */ |
| 2009 | /* buffer. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2010 | |
| 2011 | SxgSgl->Sgl.NumberOfElements = 1; |
| 2012 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2013 | /* Grab the spinlock and acquire a command */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2014 | spin_lock(&adapter->XmtZeroLock); |
| 2015 | SXG_GET_CMD(XmtRing, XmtRingInfo, XmtCmd, SxgSgl); |
| 2016 | if (XmtCmd == NULL) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2017 | /* Call sxg_complete_slow_send to see if we can */ |
| 2018 | /* free up any XmtRingZero entries and then try again */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2019 | spin_unlock(&adapter->XmtZeroLock); |
| 2020 | sxg_complete_slow_send(adapter); |
| 2021 | spin_lock(&adapter->XmtZeroLock); |
| 2022 | SXG_GET_CMD(XmtRing, XmtRingInfo, XmtCmd, SxgSgl); |
| 2023 | if (XmtCmd == NULL) { |
| 2024 | adapter->Stats.XmtZeroFull++; |
| 2025 | goto abortcmd; |
| 2026 | } |
| 2027 | } |
| 2028 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbCmd", |
| 2029 | XmtCmd, XmtRingInfo->Head, XmtRingInfo->Tail, 0); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2030 | /* Update stats */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2031 | adapter->Stats.DumbXmtPkts++; |
| 2032 | adapter->Stats.DumbXmtBytes += DataLength; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2033 | #if XXXTODO /* Stats stuff */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2034 | if (SXG_MULTICAST_PACKET(EtherHdr)) { |
| 2035 | if (SXG_BROADCAST_PACKET(EtherHdr)) { |
| 2036 | adapter->Stats.DumbXmtBcastPkts++; |
| 2037 | adapter->Stats.DumbXmtBcastBytes += DataLength; |
| 2038 | } else { |
| 2039 | adapter->Stats.DumbXmtMcastPkts++; |
| 2040 | adapter->Stats.DumbXmtMcastBytes += DataLength; |
| 2041 | } |
| 2042 | } else { |
| 2043 | adapter->Stats.DumbXmtUcastPkts++; |
| 2044 | adapter->Stats.DumbXmtUcastBytes += DataLength; |
| 2045 | } |
| 2046 | #endif |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2047 | /* Fill in the command */ |
| 2048 | /* Copy out the first SGE to the command and adjust for offset */ |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 2049 | phys_addr = |
| 2050 | pci_map_single(adapter->pcidev, skb->data, skb->len, |
| 2051 | PCI_DMA_TODEVICE); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2052 | XmtCmd->Buffer.FirstSgeAddress = SXG_GET_ADDR_HIGH(phys_addr); |
| 2053 | XmtCmd->Buffer.FirstSgeAddress = XmtCmd->Buffer.FirstSgeAddress << 32; |
| 2054 | XmtCmd->Buffer.FirstSgeAddress = |
| 2055 | XmtCmd->Buffer.FirstSgeAddress | SXG_GET_ADDR_LOW(phys_addr); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2056 | /* XmtCmd->Buffer.FirstSgeAddress = SxgSgl->Sgl.Elements[Index].Address; */ |
| 2057 | /* XmtCmd->Buffer.FirstSgeAddress.LowPart += MdlOffset; */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2058 | XmtCmd->Buffer.FirstSgeLength = DataLength; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2059 | /* Set a pointer to the remaining SGL entries */ |
| 2060 | /* XmtCmd->Sgl = SxgSgl->PhysicalAddress; */ |
| 2061 | /* Advance the physical address of the SxgSgl structure to */ |
| 2062 | /* the second SGE */ |
| 2063 | /* SglOffset = (u32)((u32 *)(&SxgSgl->Sgl.Elements[Index+1]) - */ |
| 2064 | /* (u32 *)SxgSgl); */ |
| 2065 | /* XmtCmd->Sgl.LowPart += SglOffset; */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2066 | XmtCmd->Buffer.SgeOffset = 0; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2067 | /* Note - TotalLength might be overwritten with MSS below.. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2068 | XmtCmd->Buffer.TotalLength = DataLength; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2069 | XmtCmd->SgEntries = 1; /*(ushort)(SxgSgl->Sgl.NumberOfElements - Index); */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2070 | XmtCmd->Flags = 0; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2071 | /* */ |
| 2072 | /* Advance transmit cmd descripter by 1. */ |
| 2073 | /* NOTE - See comments in SxgTcpOutput where we write */ |
| 2074 | /* to the XmtCmd register regarding CPU ID values and/or */ |
| 2075 | /* multiple commands. */ |
| 2076 | /* */ |
| 2077 | /* */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2078 | WRITE_REG(adapter->UcodeRegs[0].XmtCmd, 1, TRUE); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2079 | /* */ |
| 2080 | /* */ |
| 2081 | adapter->Stats.XmtQLen++; /* Stats within lock */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2082 | spin_unlock(&adapter->XmtZeroLock); |
| 2083 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XDumSgl2", |
| 2084 | XmtCmd, pSgl, SxgSgl, 0); |
| 2085 | return; |
| 2086 | |
| 2087 | abortcmd: |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2088 | /* NOTE - Only jump to this label AFTER grabbing the */ |
| 2089 | /* XmtZeroLock, and DO NOT DROP IT between the */ |
| 2090 | /* command allocation and the following abort. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2091 | if (XmtCmd) { |
| 2092 | SXG_ABORT_CMD(XmtRingInfo); |
| 2093 | } |
| 2094 | spin_unlock(&adapter->XmtZeroLock); |
| 2095 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2096 | /* failsgl: */ |
| 2097 | /* Jump to this label if failure occurs before the */ |
| 2098 | /* XmtZeroLock is grabbed */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2099 | adapter->Stats.XmtErrors++; |
| 2100 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "DumSGFal", |
| 2101 | pSgl, SxgSgl, XmtRingInfo->Head, XmtRingInfo->Tail); |
| 2102 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2103 | SXG_COMPLETE_DUMB_SEND(adapter, SxgSgl->DumbPacket); /* SxgSgl->DumbPacket is the skb */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2104 | } |
| 2105 | |
| 2106 | /*************************************************************** |
| 2107 | * Link management functions |
| 2108 | ***************************************************************/ |
| 2109 | |
| 2110 | /* |
| 2111 | * sxg_initialize_link - Initialize the link stuff |
| 2112 | * |
| 2113 | * Arguments - |
| 2114 | * adapter - A pointer to our adapter structure |
| 2115 | * |
| 2116 | * Return |
| 2117 | * status |
| 2118 | */ |
| 2119 | static int sxg_initialize_link(p_adapter_t adapter) |
| 2120 | { |
| 2121 | PSXG_HW_REGS HwRegs = adapter->HwRegs; |
| 2122 | u32 Value; |
| 2123 | u32 ConfigData; |
| 2124 | u32 MaxFrame; |
| 2125 | int status; |
| 2126 | |
| 2127 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "InitLink", |
| 2128 | adapter, 0, 0, 0); |
| 2129 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2130 | /* Reset PHY and XGXS module */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2131 | WRITE_REG(HwRegs->LinkStatus, LS_SERDES_POWER_DOWN, TRUE); |
| 2132 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2133 | /* Reset transmit configuration register */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2134 | WRITE_REG(HwRegs->XmtConfig, XMT_CONFIG_RESET, TRUE); |
| 2135 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2136 | /* Reset receive configuration register */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2137 | WRITE_REG(HwRegs->RcvConfig, RCV_CONFIG_RESET, TRUE); |
| 2138 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2139 | /* Reset all MAC modules */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2140 | WRITE_REG(HwRegs->MacConfig0, AXGMAC_CFG0_SUB_RESET, TRUE); |
| 2141 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2142 | /* Link address 0 */ |
| 2143 | /* XXXTODO - This assumes the MAC address (0a:0b:0c:0d:0e:0f) */ |
| 2144 | /* is stored with the first nibble (0a) in the byte 0 */ |
| 2145 | /* of the Mac address. Possibly reverse? */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2146 | Value = *(u32 *) adapter->MacAddr; |
| 2147 | WRITE_REG(HwRegs->LinkAddress0Low, Value, TRUE); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2148 | /* also write the MAC address to the MAC. Endian is reversed. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2149 | WRITE_REG(HwRegs->MacAddressLow, ntohl(Value), TRUE); |
| 2150 | Value = (*(u16 *) & adapter->MacAddr[4] & 0x0000FFFF); |
| 2151 | WRITE_REG(HwRegs->LinkAddress0High, Value | LINK_ADDRESS_ENABLE, TRUE); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2152 | /* endian swap for the MAC (put high bytes in bits [31:16], swapped) */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2153 | Value = ntohl(Value); |
| 2154 | WRITE_REG(HwRegs->MacAddressHigh, Value, TRUE); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2155 | /* Link address 1 */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2156 | WRITE_REG(HwRegs->LinkAddress1Low, 0, TRUE); |
| 2157 | WRITE_REG(HwRegs->LinkAddress1High, 0, TRUE); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2158 | /* Link address 2 */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2159 | WRITE_REG(HwRegs->LinkAddress2Low, 0, TRUE); |
| 2160 | WRITE_REG(HwRegs->LinkAddress2High, 0, TRUE); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2161 | /* Link address 3 */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2162 | WRITE_REG(HwRegs->LinkAddress3Low, 0, TRUE); |
| 2163 | WRITE_REG(HwRegs->LinkAddress3High, 0, TRUE); |
| 2164 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2165 | /* Enable MAC modules */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2166 | WRITE_REG(HwRegs->MacConfig0, 0, TRUE); |
| 2167 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2168 | /* Configure MAC */ |
| 2169 | WRITE_REG(HwRegs->MacConfig1, (AXGMAC_CFG1_XMT_PAUSE | /* Allow sending of pause */ |
| 2170 | AXGMAC_CFG1_XMT_EN | /* Enable XMT */ |
| 2171 | AXGMAC_CFG1_RCV_PAUSE | /* Enable detection of pause */ |
| 2172 | AXGMAC_CFG1_RCV_EN | /* Enable receive */ |
| 2173 | AXGMAC_CFG1_SHORT_ASSERT | /* short frame detection */ |
| 2174 | AXGMAC_CFG1_CHECK_LEN | /* Verify frame length */ |
| 2175 | AXGMAC_CFG1_GEN_FCS | /* Generate FCS */ |
| 2176 | AXGMAC_CFG1_PAD_64), /* Pad frames to 64 bytes */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2177 | TRUE); |
| 2178 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2179 | /* Set AXGMAC max frame length if jumbo. Not needed for standard MTU */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2180 | if (adapter->JumboEnabled) { |
| 2181 | WRITE_REG(HwRegs->MacMaxFrameLen, AXGMAC_MAXFRAME_JUMBO, TRUE); |
| 2182 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2183 | /* AMIIM Configuration Register - */ |
| 2184 | /* The value placed in the AXGMAC_AMIIM_CFG_HALF_CLOCK portion */ |
| 2185 | /* (bottom bits) of this register is used to determine the */ |
| 2186 | /* MDC frequency as specified in the A-XGMAC Design Document. */ |
| 2187 | /* This value must not be zero. The following value (62 or 0x3E) */ |
| 2188 | /* is based on our MAC transmit clock frequency (MTCLK) of 312.5 MHz. */ |
| 2189 | /* Given a maximum MDIO clock frequency of 2.5 MHz (see the PHY spec), */ |
| 2190 | /* we get: 312.5/(2*(X+1)) < 2.5 ==> X = 62. */ |
| 2191 | /* This value happens to be the default value for this register, */ |
| 2192 | /* so we really don't have to do this. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2193 | WRITE_REG(HwRegs->MacAmiimConfig, 0x0000003E, TRUE); |
| 2194 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2195 | /* Power up and enable PHY and XAUI/XGXS/Serdes logic */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2196 | WRITE_REG(HwRegs->LinkStatus, |
| 2197 | (LS_PHY_CLR_RESET | |
| 2198 | LS_XGXS_ENABLE | |
| 2199 | LS_XGXS_CTL | LS_PHY_CLK_EN | LS_ATTN_ALARM), TRUE); |
| 2200 | DBG_ERROR("After Power Up and enable PHY in sxg_initialize_link\n"); |
| 2201 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2202 | /* Per information given by Aeluros, wait 100 ms after removing reset. */ |
| 2203 | /* It's not enough to wait for the self-clearing reset bit in reg 0 to clear. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2204 | mdelay(100); |
| 2205 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2206 | /* Verify the PHY has come up by checking that the Reset bit has cleared. */ |
| 2207 | status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */ |
| 2208 | PHY_PMA_CONTROL1, /* PMA/PMD control register */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2209 | &Value); |
| 2210 | if (status != STATUS_SUCCESS) |
| 2211 | return (STATUS_FAILURE); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2212 | if (Value & PMA_CONTROL1_RESET) /* reset complete if bit is 0 */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2213 | return (STATUS_FAILURE); |
| 2214 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2215 | /* The SERDES should be initialized by now - confirm */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2216 | READ_REG(HwRegs->LinkStatus, Value); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2217 | if (Value & LS_SERDES_DOWN) /* verify SERDES is initialized */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2218 | return (STATUS_FAILURE); |
| 2219 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2220 | /* The XAUI link should also be up - confirm */ |
| 2221 | if (!(Value & LS_XAUI_LINK_UP)) /* verify XAUI link is up */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2222 | return (STATUS_FAILURE); |
| 2223 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2224 | /* Initialize the PHY */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2225 | status = sxg_phy_init(adapter); |
| 2226 | if (status != STATUS_SUCCESS) |
| 2227 | return (STATUS_FAILURE); |
| 2228 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2229 | /* Enable the Link Alarm */ |
| 2230 | status = sxg_write_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */ |
| 2231 | LASI_CONTROL, /* LASI control register */ |
| 2232 | LASI_CTL_LS_ALARM_ENABLE); /* enable link alarm bit */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2233 | if (status != STATUS_SUCCESS) |
| 2234 | return (STATUS_FAILURE); |
| 2235 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2236 | /* XXXTODO - temporary - verify bit is set */ |
| 2237 | status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */ |
| 2238 | LASI_CONTROL, /* LASI control register */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2239 | &Value); |
| 2240 | if (status != STATUS_SUCCESS) |
| 2241 | return (STATUS_FAILURE); |
| 2242 | if (!(Value & LASI_CTL_LS_ALARM_ENABLE)) { |
| 2243 | DBG_ERROR("Error! LASI Control Alarm Enable bit not set!\n"); |
| 2244 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2245 | /* Enable receive */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2246 | MaxFrame = adapter->JumboEnabled ? JUMBOMAXFRAME : ETHERMAXFRAME; |
| 2247 | ConfigData = (RCV_CONFIG_ENABLE | |
| 2248 | RCV_CONFIG_ENPARSE | |
| 2249 | RCV_CONFIG_RCVBAD | |
| 2250 | RCV_CONFIG_RCVPAUSE | |
| 2251 | RCV_CONFIG_TZIPV6 | |
| 2252 | RCV_CONFIG_TZIPV4 | |
| 2253 | RCV_CONFIG_HASH_16 | |
| 2254 | RCV_CONFIG_SOCKET | RCV_CONFIG_BUFSIZE(MaxFrame)); |
| 2255 | WRITE_REG(HwRegs->RcvConfig, ConfigData, TRUE); |
| 2256 | |
| 2257 | WRITE_REG(HwRegs->XmtConfig, XMT_CONFIG_ENABLE, TRUE); |
| 2258 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2259 | /* Mark the link as down. We'll get a link event when it comes up. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2260 | sxg_link_state(adapter, SXG_LINK_DOWN); |
| 2261 | |
| 2262 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XInitLnk", |
| 2263 | adapter, 0, 0, 0); |
| 2264 | return (STATUS_SUCCESS); |
| 2265 | } |
| 2266 | |
| 2267 | /* |
| 2268 | * sxg_phy_init - Initialize the PHY |
| 2269 | * |
| 2270 | * Arguments - |
| 2271 | * adapter - A pointer to our adapter structure |
| 2272 | * |
| 2273 | * Return |
| 2274 | * status |
| 2275 | */ |
| 2276 | static int sxg_phy_init(p_adapter_t adapter) |
| 2277 | { |
| 2278 | u32 Value; |
| 2279 | PPHY_UCODE p; |
| 2280 | int status; |
| 2281 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 2282 | DBG_ERROR("ENTER %s\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2283 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2284 | /* Read a register to identify the PHY type */ |
| 2285 | status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */ |
| 2286 | 0xC205, /* PHY ID register (?) */ |
| 2287 | &Value); /* XXXTODO - add def */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2288 | if (status != STATUS_SUCCESS) |
| 2289 | return (STATUS_FAILURE); |
| 2290 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2291 | if (Value == 0x0012) { /* 0x0012 == AEL2005C PHY(?) - XXXTODO - add def */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2292 | DBG_ERROR |
| 2293 | ("AEL2005C PHY detected. Downloading PHY microcode.\n"); |
| 2294 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2295 | /* Initialize AEL2005C PHY and download PHY microcode */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2296 | for (p = PhyUcode; p->Addr != 0xFFFF; p++) { |
| 2297 | if (p->Addr == 0) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2298 | /* if address == 0, data == sleep time in ms */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2299 | mdelay(p->Data); |
| 2300 | } else { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2301 | /* write the given data to the specified address */ |
| 2302 | status = sxg_write_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */ |
| 2303 | p->Addr, /* PHY address */ |
| 2304 | p->Data); /* PHY data */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2305 | if (status != STATUS_SUCCESS) |
| 2306 | return (STATUS_FAILURE); |
| 2307 | } |
| 2308 | } |
| 2309 | } |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 2310 | DBG_ERROR("EXIT %s\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2311 | |
| 2312 | return (STATUS_SUCCESS); |
| 2313 | } |
| 2314 | |
| 2315 | /* |
| 2316 | * sxg_link_event - Process a link event notification from the card |
| 2317 | * |
| 2318 | * Arguments - |
| 2319 | * adapter - A pointer to our adapter structure |
| 2320 | * |
| 2321 | * Return |
| 2322 | * None |
| 2323 | */ |
| 2324 | static void sxg_link_event(p_adapter_t adapter) |
| 2325 | { |
| 2326 | PSXG_HW_REGS HwRegs = adapter->HwRegs; |
| 2327 | SXG_LINK_STATE LinkState; |
| 2328 | int status; |
| 2329 | u32 Value; |
| 2330 | |
| 2331 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "LinkEvnt", |
| 2332 | adapter, 0, 0, 0); |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 2333 | DBG_ERROR("ENTER %s\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2334 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2335 | /* Check the Link Status register. We should have a Link Alarm. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2336 | READ_REG(HwRegs->LinkStatus, Value); |
| 2337 | if (Value & LS_LINK_ALARM) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2338 | /* We got a Link Status alarm. First, pause to let the */ |
| 2339 | /* link state settle (it can bounce a number of times) */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2340 | mdelay(10); |
| 2341 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2342 | /* Now clear the alarm by reading the LASI status register. */ |
| 2343 | status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */ |
| 2344 | LASI_STATUS, /* LASI status register */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2345 | &Value); |
| 2346 | if (status != STATUS_SUCCESS) { |
| 2347 | DBG_ERROR("Error reading LASI Status MDIO register!\n"); |
| 2348 | sxg_link_state(adapter, SXG_LINK_DOWN); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2349 | /* ASSERT(0); */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2350 | } |
| 2351 | ASSERT(Value & LASI_STATUS_LS_ALARM); |
| 2352 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2353 | /* Now get and set the link state */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2354 | LinkState = sxg_get_link_state(adapter); |
| 2355 | sxg_link_state(adapter, LinkState); |
| 2356 | DBG_ERROR("SXG: Link Alarm occurred. Link is %s\n", |
| 2357 | ((LinkState == SXG_LINK_UP) ? "UP" : "DOWN")); |
| 2358 | } else { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2359 | /* XXXTODO - Assuming Link Attention is only being generated for the */ |
| 2360 | /* Link Alarm pin (and not for a XAUI Link Status change), then it's */ |
| 2361 | /* impossible to get here. Yet we've gotten here twice (under extreme */ |
| 2362 | /* conditions - bouncing the link up and down many times a second). */ |
| 2363 | /* Needs further investigation. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2364 | DBG_ERROR("SXG: sxg_link_event: Can't get here!\n"); |
| 2365 | DBG_ERROR("SXG: Link Status == 0x%08X.\n", Value); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2366 | /* ASSERT(0); */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2367 | } |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 2368 | DBG_ERROR("EXIT %s\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2369 | |
| 2370 | } |
| 2371 | |
| 2372 | /* |
| 2373 | * sxg_get_link_state - Determine if the link is up or down |
| 2374 | * |
| 2375 | * Arguments - |
| 2376 | * adapter - A pointer to our adapter structure |
| 2377 | * |
| 2378 | * Return |
| 2379 | * Link State |
| 2380 | */ |
| 2381 | static SXG_LINK_STATE sxg_get_link_state(p_adapter_t adapter) |
| 2382 | { |
| 2383 | int status; |
| 2384 | u32 Value; |
| 2385 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 2386 | DBG_ERROR("ENTER %s\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2387 | |
| 2388 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "GetLink", |
| 2389 | adapter, 0, 0, 0); |
| 2390 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2391 | /* Per the Xenpak spec (and the IEEE 10Gb spec?), the link is up if */ |
| 2392 | /* the following 3 bits (from 3 different MDIO registers) are all true. */ |
| 2393 | status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */ |
| 2394 | PHY_PMA_RCV_DET, /* PMA/PMD Receive Signal Detect register */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2395 | &Value); |
| 2396 | if (status != STATUS_SUCCESS) |
| 2397 | goto bad; |
| 2398 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2399 | /* If PMA/PMD receive signal detect is 0, then the link is down */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2400 | if (!(Value & PMA_RCV_DETECT)) |
| 2401 | return (SXG_LINK_DOWN); |
| 2402 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2403 | status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PCS, /* PHY PCS module */ |
| 2404 | PHY_PCS_10G_STATUS1, /* PCS 10GBASE-R Status 1 register */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2405 | &Value); |
| 2406 | if (status != STATUS_SUCCESS) |
| 2407 | goto bad; |
| 2408 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2409 | /* If PCS is not locked to receive blocks, then the link is down */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2410 | if (!(Value & PCS_10B_BLOCK_LOCK)) |
| 2411 | return (SXG_LINK_DOWN); |
| 2412 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2413 | status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_XS, /* PHY XS module */ |
| 2414 | PHY_XS_LANE_STATUS, /* XS Lane Status register */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2415 | &Value); |
| 2416 | if (status != STATUS_SUCCESS) |
| 2417 | goto bad; |
| 2418 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2419 | /* If XS transmit lanes are not aligned, then the link is down */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2420 | if (!(Value & XS_LANE_ALIGN)) |
| 2421 | return (SXG_LINK_DOWN); |
| 2422 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2423 | /* All 3 bits are true, so the link is up */ |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 2424 | DBG_ERROR("EXIT %s\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2425 | |
| 2426 | return (SXG_LINK_UP); |
| 2427 | |
| 2428 | bad: |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2429 | /* An error occurred reading an MDIO register. This shouldn't happen. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2430 | DBG_ERROR("Error reading an MDIO register!\n"); |
| 2431 | ASSERT(0); |
| 2432 | return (SXG_LINK_DOWN); |
| 2433 | } |
| 2434 | |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 2435 | static void sxg_indicate_link_state(p_adapter_t adapter, |
| 2436 | SXG_LINK_STATE LinkState) |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2437 | { |
| 2438 | if (adapter->LinkState == SXG_LINK_UP) { |
| 2439 | DBG_ERROR("%s: LINK now UP, call netif_start_queue\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 2440 | __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2441 | netif_start_queue(adapter->netdev); |
| 2442 | } else { |
| 2443 | DBG_ERROR("%s: LINK now DOWN, call netif_stop_queue\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 2444 | __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2445 | netif_stop_queue(adapter->netdev); |
| 2446 | } |
| 2447 | } |
| 2448 | |
| 2449 | /* |
| 2450 | * sxg_link_state - Set the link state and if necessary, indicate. |
| 2451 | * This routine the central point of processing for all link state changes. |
| 2452 | * Nothing else in the driver should alter the link state or perform |
| 2453 | * link state indications |
| 2454 | * |
| 2455 | * Arguments - |
| 2456 | * adapter - A pointer to our adapter structure |
| 2457 | * LinkState - The link state |
| 2458 | * |
| 2459 | * Return |
| 2460 | * None |
| 2461 | */ |
| 2462 | static void sxg_link_state(p_adapter_t adapter, SXG_LINK_STATE LinkState) |
| 2463 | { |
| 2464 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "LnkINDCT", |
| 2465 | adapter, LinkState, adapter->LinkState, adapter->State); |
| 2466 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 2467 | DBG_ERROR("ENTER %s\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2468 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2469 | /* Hold the adapter lock during this routine. Maybe move */ |
| 2470 | /* the lock to the caller. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2471 | spin_lock(&adapter->AdapterLock); |
| 2472 | if (LinkState == adapter->LinkState) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2473 | /* Nothing changed.. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2474 | spin_unlock(&adapter->AdapterLock); |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 2475 | DBG_ERROR("EXIT #0 %s\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2476 | return; |
| 2477 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2478 | /* Save the adapter state */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2479 | adapter->LinkState = LinkState; |
| 2480 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2481 | /* Drop the lock and indicate link state */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2482 | spin_unlock(&adapter->AdapterLock); |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 2483 | DBG_ERROR("EXIT #1 %s\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2484 | |
| 2485 | sxg_indicate_link_state(adapter, LinkState); |
| 2486 | } |
| 2487 | |
| 2488 | /* |
| 2489 | * sxg_write_mdio_reg - Write to a register on the MDIO bus |
| 2490 | * |
| 2491 | * Arguments - |
| 2492 | * adapter - A pointer to our adapter structure |
| 2493 | * DevAddr - MDIO device number being addressed |
| 2494 | * RegAddr - register address for the specified MDIO device |
| 2495 | * Value - value to write to the MDIO register |
| 2496 | * |
| 2497 | * Return |
| 2498 | * status |
| 2499 | */ |
| 2500 | static int sxg_write_mdio_reg(p_adapter_t adapter, |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 2501 | u32 DevAddr, u32 RegAddr, u32 Value) |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2502 | { |
| 2503 | PSXG_HW_REGS HwRegs = adapter->HwRegs; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2504 | u32 AddrOp; /* Address operation (written to MIIM field reg) */ |
| 2505 | u32 WriteOp; /* Write operation (written to MIIM field reg) */ |
| 2506 | u32 Cmd; /* Command (written to MIIM command reg) */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2507 | u32 ValueRead; |
| 2508 | u32 Timeout; |
| 2509 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2510 | /* DBG_ERROR("ENTER %s\n", __func__); */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2511 | |
| 2512 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "WrtMDIO", |
| 2513 | adapter, 0, 0, 0); |
| 2514 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2515 | /* Ensure values don't exceed field width */ |
| 2516 | DevAddr &= 0x001F; /* 5-bit field */ |
| 2517 | RegAddr &= 0xFFFF; /* 16-bit field */ |
| 2518 | Value &= 0xFFFF; /* 16-bit field */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2519 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2520 | /* Set MIIM field register bits for an MIIM address operation */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2521 | AddrOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) | |
| 2522 | (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) | |
| 2523 | (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) | |
| 2524 | (MIIM_OP_ADDR << AXGMAC_AMIIM_FIELD_OP_SHIFT) | RegAddr; |
| 2525 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2526 | /* Set MIIM field register bits for an MIIM write operation */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2527 | WriteOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) | |
| 2528 | (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) | |
| 2529 | (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) | |
| 2530 | (MIIM_OP_WRITE << AXGMAC_AMIIM_FIELD_OP_SHIFT) | Value; |
| 2531 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2532 | /* Set MIIM command register bits to execute an MIIM command */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2533 | Cmd = AXGMAC_AMIIM_CMD_START | AXGMAC_AMIIM_CMD_10G_OPERATION; |
| 2534 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2535 | /* Reset the command register command bit (in case it's not 0) */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2536 | WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE); |
| 2537 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2538 | /* MIIM write to set the address of the specified MDIO register */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2539 | WRITE_REG(HwRegs->MacAmiimField, AddrOp, TRUE); |
| 2540 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2541 | /* Write to MIIM Command Register to execute to address operation */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2542 | WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE); |
| 2543 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2544 | /* Poll AMIIM Indicator register to wait for completion */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2545 | Timeout = SXG_LINK_TIMEOUT; |
| 2546 | do { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2547 | udelay(100); /* Timeout in 100us units */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2548 | READ_REG(HwRegs->MacAmiimIndicator, ValueRead); |
| 2549 | if (--Timeout == 0) { |
| 2550 | return (STATUS_FAILURE); |
| 2551 | } |
| 2552 | } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY); |
| 2553 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2554 | /* Reset the command register command bit */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2555 | WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE); |
| 2556 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2557 | /* MIIM write to set up an MDIO write operation */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2558 | WRITE_REG(HwRegs->MacAmiimField, WriteOp, TRUE); |
| 2559 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2560 | /* Write to MIIM Command Register to execute the write operation */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2561 | WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE); |
| 2562 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2563 | /* Poll AMIIM Indicator register to wait for completion */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2564 | Timeout = SXG_LINK_TIMEOUT; |
| 2565 | do { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2566 | udelay(100); /* Timeout in 100us units */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2567 | READ_REG(HwRegs->MacAmiimIndicator, ValueRead); |
| 2568 | if (--Timeout == 0) { |
| 2569 | return (STATUS_FAILURE); |
| 2570 | } |
| 2571 | } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY); |
| 2572 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2573 | /* DBG_ERROR("EXIT %s\n", __func__); */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2574 | |
| 2575 | return (STATUS_SUCCESS); |
| 2576 | } |
| 2577 | |
| 2578 | /* |
| 2579 | * sxg_read_mdio_reg - Read a register on the MDIO bus |
| 2580 | * |
| 2581 | * Arguments - |
| 2582 | * adapter - A pointer to our adapter structure |
| 2583 | * DevAddr - MDIO device number being addressed |
| 2584 | * RegAddr - register address for the specified MDIO device |
| 2585 | * pValue - pointer to where to put data read from the MDIO register |
| 2586 | * |
| 2587 | * Return |
| 2588 | * status |
| 2589 | */ |
| 2590 | static int sxg_read_mdio_reg(p_adapter_t adapter, |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 2591 | u32 DevAddr, u32 RegAddr, u32 *pValue) |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2592 | { |
| 2593 | PSXG_HW_REGS HwRegs = adapter->HwRegs; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2594 | u32 AddrOp; /* Address operation (written to MIIM field reg) */ |
| 2595 | u32 ReadOp; /* Read operation (written to MIIM field reg) */ |
| 2596 | u32 Cmd; /* Command (written to MIIM command reg) */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2597 | u32 ValueRead; |
| 2598 | u32 Timeout; |
| 2599 | |
| 2600 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "WrtMDIO", |
| 2601 | adapter, 0, 0, 0); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2602 | /* DBG_ERROR("ENTER %s\n", __func__); */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2603 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2604 | /* Ensure values don't exceed field width */ |
| 2605 | DevAddr &= 0x001F; /* 5-bit field */ |
| 2606 | RegAddr &= 0xFFFF; /* 16-bit field */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2607 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2608 | /* Set MIIM field register bits for an MIIM address operation */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2609 | AddrOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) | |
| 2610 | (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) | |
| 2611 | (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) | |
| 2612 | (MIIM_OP_ADDR << AXGMAC_AMIIM_FIELD_OP_SHIFT) | RegAddr; |
| 2613 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2614 | /* Set MIIM field register bits for an MIIM read operation */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2615 | ReadOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) | |
| 2616 | (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) | |
| 2617 | (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) | |
| 2618 | (MIIM_OP_READ << AXGMAC_AMIIM_FIELD_OP_SHIFT); |
| 2619 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2620 | /* Set MIIM command register bits to execute an MIIM command */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2621 | Cmd = AXGMAC_AMIIM_CMD_START | AXGMAC_AMIIM_CMD_10G_OPERATION; |
| 2622 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2623 | /* Reset the command register command bit (in case it's not 0) */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2624 | WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE); |
| 2625 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2626 | /* MIIM write to set the address of the specified MDIO register */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2627 | WRITE_REG(HwRegs->MacAmiimField, AddrOp, TRUE); |
| 2628 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2629 | /* Write to MIIM Command Register to execute to address operation */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2630 | WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE); |
| 2631 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2632 | /* Poll AMIIM Indicator register to wait for completion */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2633 | Timeout = SXG_LINK_TIMEOUT; |
| 2634 | do { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2635 | udelay(100); /* Timeout in 100us units */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2636 | READ_REG(HwRegs->MacAmiimIndicator, ValueRead); |
| 2637 | if (--Timeout == 0) { |
| 2638 | return (STATUS_FAILURE); |
| 2639 | } |
| 2640 | } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY); |
| 2641 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2642 | /* Reset the command register command bit */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2643 | WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE); |
| 2644 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2645 | /* MIIM write to set up an MDIO register read operation */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2646 | WRITE_REG(HwRegs->MacAmiimField, ReadOp, TRUE); |
| 2647 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2648 | /* Write to MIIM Command Register to execute the read operation */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2649 | WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE); |
| 2650 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2651 | /* Poll AMIIM Indicator register to wait for completion */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2652 | Timeout = SXG_LINK_TIMEOUT; |
| 2653 | do { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2654 | udelay(100); /* Timeout in 100us units */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2655 | READ_REG(HwRegs->MacAmiimIndicator, ValueRead); |
| 2656 | if (--Timeout == 0) { |
| 2657 | return (STATUS_FAILURE); |
| 2658 | } |
| 2659 | } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY); |
| 2660 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2661 | /* Read the MDIO register data back from the field register */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2662 | READ_REG(HwRegs->MacAmiimField, *pValue); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2663 | *pValue &= 0xFFFF; /* data is in the lower 16 bits */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2664 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2665 | /* DBG_ERROR("EXIT %s\n", __func__); */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2666 | |
| 2667 | return (STATUS_SUCCESS); |
| 2668 | } |
| 2669 | |
| 2670 | /* |
| 2671 | * Allocate a mcast_address structure to hold the multicast address. |
| 2672 | * Link it in. |
| 2673 | */ |
| 2674 | static int sxg_mcast_add_list(p_adapter_t adapter, char *address) |
| 2675 | { |
| 2676 | p_mcast_address_t mcaddr, mlist; |
| 2677 | bool equaladdr; |
| 2678 | |
| 2679 | /* Check to see if it already exists */ |
| 2680 | mlist = adapter->mcastaddrs; |
| 2681 | while (mlist) { |
| 2682 | ETHER_EQ_ADDR(mlist->address, address, equaladdr); |
| 2683 | if (equaladdr) { |
| 2684 | return (STATUS_SUCCESS); |
| 2685 | } |
| 2686 | mlist = mlist->next; |
| 2687 | } |
| 2688 | |
| 2689 | /* Doesn't already exist. Allocate a structure to hold it */ |
| 2690 | mcaddr = kmalloc(sizeof(mcast_address_t), GFP_ATOMIC); |
| 2691 | if (mcaddr == NULL) |
| 2692 | return 1; |
| 2693 | |
| 2694 | memcpy(mcaddr->address, address, 6); |
| 2695 | |
| 2696 | mcaddr->next = adapter->mcastaddrs; |
| 2697 | adapter->mcastaddrs = mcaddr; |
| 2698 | |
| 2699 | return (STATUS_SUCCESS); |
| 2700 | } |
| 2701 | |
| 2702 | /* |
| 2703 | * Functions to obtain the CRC corresponding to the destination mac address. |
| 2704 | * This is a standard ethernet CRC in that it is a 32-bit, reflected CRC using |
| 2705 | * the polynomial: |
| 2706 | * x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1. |
| 2707 | * |
| 2708 | * After the CRC for the 6 bytes is generated (but before the value is complemented), |
| 2709 | * we must then transpose the value and return bits 30-23. |
| 2710 | * |
| 2711 | */ |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 2712 | static u32 sxg_crc_table[256]; /* Table of CRC's for all possible byte values */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2713 | static u32 sxg_crc_init; /* Is table initialized */ |
| 2714 | |
| 2715 | /* |
| 2716 | * Contruct the CRC32 table |
| 2717 | */ |
| 2718 | static void sxg_mcast_init_crc32(void) |
| 2719 | { |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 2720 | u32 c; /* CRC shit reg */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2721 | u32 e = 0; /* Poly X-or pattern */ |
| 2722 | int i; /* counter */ |
| 2723 | int k; /* byte being shifted into crc */ |
| 2724 | |
| 2725 | static int p[] = { 0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, 26 }; |
| 2726 | |
| 2727 | for (i = 0; i < sizeof(p) / sizeof(int); i++) { |
| 2728 | e |= 1L << (31 - p[i]); |
| 2729 | } |
| 2730 | |
| 2731 | for (i = 1; i < 256; i++) { |
| 2732 | c = i; |
| 2733 | for (k = 8; k; k--) { |
| 2734 | c = c & 1 ? (c >> 1) ^ e : c >> 1; |
| 2735 | } |
| 2736 | sxg_crc_table[i] = c; |
| 2737 | } |
| 2738 | } |
| 2739 | |
| 2740 | /* |
| 2741 | * Return the MAC hast as described above. |
| 2742 | */ |
| 2743 | static unsigned char sxg_mcast_get_mac_hash(char *macaddr) |
| 2744 | { |
| 2745 | u32 crc; |
| 2746 | char *p; |
| 2747 | int i; |
| 2748 | unsigned char machash = 0; |
| 2749 | |
| 2750 | if (!sxg_crc_init) { |
| 2751 | sxg_mcast_init_crc32(); |
| 2752 | sxg_crc_init = 1; |
| 2753 | } |
| 2754 | |
| 2755 | crc = 0xFFFFFFFF; /* Preload shift register, per crc-32 spec */ |
| 2756 | for (i = 0, p = macaddr; i < 6; ++p, ++i) { |
| 2757 | crc = (crc >> 8) ^ sxg_crc_table[(crc ^ *p) & 0xFF]; |
| 2758 | } |
| 2759 | |
| 2760 | /* Return bits 1-8, transposed */ |
| 2761 | for (i = 1; i < 9; i++) { |
| 2762 | machash |= (((crc >> i) & 1) << (8 - i)); |
| 2763 | } |
| 2764 | |
| 2765 | return (machash); |
| 2766 | } |
| 2767 | |
| 2768 | static void sxg_mcast_set_bit(p_adapter_t adapter, char *address) |
| 2769 | { |
| 2770 | unsigned char crcpoly; |
| 2771 | |
| 2772 | /* Get the CRC polynomial for the mac address */ |
| 2773 | crcpoly = sxg_mcast_get_mac_hash(address); |
| 2774 | |
| 2775 | /* We only have space on the SLIC for 64 entries. Lop |
| 2776 | * off the top two bits. (2^6 = 64) |
| 2777 | */ |
| 2778 | crcpoly &= 0x3F; |
| 2779 | |
| 2780 | /* OR in the new bit into our 64 bit mask. */ |
| 2781 | adapter->MulticastMask |= (u64) 1 << crcpoly; |
| 2782 | } |
| 2783 | |
| 2784 | static void sxg_mcast_set_list(p_net_device dev) |
| 2785 | { |
| 2786 | #if XXXTODO |
| 2787 | p_adapter_t adapter = (p_adapter_t) netdev_priv(dev); |
| 2788 | int status = STATUS_SUCCESS; |
| 2789 | int i; |
| 2790 | char *addresses; |
| 2791 | struct dev_mc_list *mc_list = dev->mc_list; |
| 2792 | int mc_count = dev->mc_count; |
| 2793 | |
| 2794 | ASSERT(adapter); |
| 2795 | |
| 2796 | for (i = 1; i <= mc_count; i++) { |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 2797 | addresses = (char *)&mc_list->dmi_addr; |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2798 | if (mc_list->dmi_addrlen == 6) { |
| 2799 | status = sxg_mcast_add_list(adapter, addresses); |
| 2800 | if (status != STATUS_SUCCESS) { |
| 2801 | break; |
| 2802 | } |
| 2803 | } else { |
| 2804 | status = -EINVAL; |
| 2805 | break; |
| 2806 | } |
| 2807 | sxg_mcast_set_bit(adapter, addresses); |
| 2808 | mc_list = mc_list->next; |
| 2809 | } |
| 2810 | |
| 2811 | DBG_ERROR("%s a->devflags_prev[%x] dev->flags[%x] status[%x]\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 2812 | __func__, adapter->devflags_prev, dev->flags, status); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2813 | if (adapter->devflags_prev != dev->flags) { |
| 2814 | adapter->macopts = MAC_DIRECTED; |
| 2815 | if (dev->flags) { |
| 2816 | if (dev->flags & IFF_BROADCAST) { |
| 2817 | adapter->macopts |= MAC_BCAST; |
| 2818 | } |
| 2819 | if (dev->flags & IFF_PROMISC) { |
| 2820 | adapter->macopts |= MAC_PROMISC; |
| 2821 | } |
| 2822 | if (dev->flags & IFF_ALLMULTI) { |
| 2823 | adapter->macopts |= MAC_ALLMCAST; |
| 2824 | } |
| 2825 | if (dev->flags & IFF_MULTICAST) { |
| 2826 | adapter->macopts |= MAC_MCAST; |
| 2827 | } |
| 2828 | } |
| 2829 | adapter->devflags_prev = dev->flags; |
| 2830 | DBG_ERROR("%s call sxg_config_set adapter->macopts[%x]\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 2831 | __func__, adapter->macopts); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2832 | sxg_config_set(adapter, TRUE); |
| 2833 | } else { |
| 2834 | if (status == STATUS_SUCCESS) { |
| 2835 | sxg_mcast_set_mask(adapter); |
| 2836 | } |
| 2837 | } |
| 2838 | #endif |
| 2839 | return; |
| 2840 | } |
| 2841 | |
| 2842 | static void sxg_mcast_set_mask(p_adapter_t adapter) |
| 2843 | { |
| 2844 | PSXG_UCODE_REGS sxg_regs = adapter->UcodeRegs; |
| 2845 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 2846 | DBG_ERROR("%s ENTER (%s) macopts[%x] mask[%llx]\n", __func__, |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 2847 | adapter->netdev->name, (unsigned int)adapter->MacFilter, |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2848 | adapter->MulticastMask); |
| 2849 | |
| 2850 | if (adapter->MacFilter & (MAC_ALLMCAST | MAC_PROMISC)) { |
| 2851 | /* Turn on all multicast addresses. We have to do this for promiscuous |
| 2852 | * mode as well as ALLMCAST mode. It saves the Microcode from having |
| 2853 | * to keep state about the MAC configuration. |
| 2854 | */ |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2855 | /* DBG_ERROR("sxg: %s macopts = MAC_ALLMCAST | MAC_PROMISC\n SLUT MODE!!!\n",__func__); */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2856 | WRITE_REG(sxg_regs->McastLow, 0xFFFFFFFF, FLUSH); |
| 2857 | WRITE_REG(sxg_regs->McastHigh, 0xFFFFFFFF, FLUSH); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2858 | /* DBG_ERROR("%s (%s) WRITE to slic_regs slic_mcastlow&high 0xFFFFFFFF\n",__func__, adapter->netdev->name); */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2859 | |
| 2860 | } else { |
| 2861 | /* Commit our multicast mast to the SLIC by writing to the multicast |
| 2862 | * address mask registers |
| 2863 | */ |
| 2864 | DBG_ERROR("%s (%s) WRITE mcastlow[%lx] mcasthigh[%lx]\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 2865 | __func__, adapter->netdev->name, |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2866 | ((ulong) (adapter->MulticastMask & 0xFFFFFFFF)), |
| 2867 | ((ulong) |
| 2868 | ((adapter->MulticastMask >> 32) & 0xFFFFFFFF))); |
| 2869 | |
| 2870 | WRITE_REG(sxg_regs->McastLow, |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 2871 | (u32) (adapter->MulticastMask & 0xFFFFFFFF), FLUSH); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2872 | WRITE_REG(sxg_regs->McastHigh, |
| 2873 | (u32) ((adapter-> |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 2874 | MulticastMask >> 32) & 0xFFFFFFFF), FLUSH); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2875 | } |
| 2876 | } |
| 2877 | |
| 2878 | static void sxg_unmap_mmio_space(p_adapter_t adapter) |
| 2879 | { |
| 2880 | #if LINUX_FREES_ADAPTER_RESOURCES |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2881 | /* if (adapter->Regs) { */ |
| 2882 | /* iounmap(adapter->Regs); */ |
| 2883 | /* } */ |
| 2884 | /* adapter->slic_regs = NULL; */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2885 | #endif |
| 2886 | } |
| 2887 | |
| 2888 | #if XXXTODO |
| 2889 | /* |
| 2890 | * SxgFreeResources - Free everything allocated in SxgAllocateResources |
| 2891 | * |
| 2892 | * Arguments - |
| 2893 | * adapter - A pointer to our adapter structure |
| 2894 | * |
| 2895 | * Return |
| 2896 | * none |
| 2897 | */ |
| 2898 | void SxgFreeResources(p_adapter_t adapter) |
| 2899 | { |
| 2900 | u32 RssIds, IsrCount; |
| 2901 | PTCP_OBJECT TcpObject; |
| 2902 | u32 i; |
| 2903 | BOOLEAN TimerCancelled; |
| 2904 | |
| 2905 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "FreeRes", |
| 2906 | adapter, adapter->MaxTcbs, 0, 0); |
| 2907 | |
| 2908 | RssIds = SXG_RSS_CPU_COUNT(adapter); |
| 2909 | IsrCount = adapter->MsiEnabled ? RssIds : 1; |
| 2910 | |
| 2911 | if (adapter->BasicAllocations == FALSE) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2912 | /* No allocations have been made, including spinlocks, */ |
| 2913 | /* or listhead initializations. Return. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2914 | return; |
| 2915 | } |
| 2916 | |
| 2917 | if (!(IsListEmpty(&adapter->AllRcvBlocks))) { |
| 2918 | SxgFreeRcvBlocks(adapter); |
| 2919 | } |
| 2920 | if (!(IsListEmpty(&adapter->AllSglBuffers))) { |
| 2921 | SxgFreeSglBuffers(adapter); |
| 2922 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2923 | /* Free event queues. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2924 | if (adapter->EventRings) { |
| 2925 | pci_free_consistent(adapter->pcidev, |
| 2926 | sizeof(SXG_EVENT_RING) * RssIds, |
| 2927 | adapter->EventRings, adapter->PEventRings); |
| 2928 | } |
| 2929 | if (adapter->Isr) { |
| 2930 | pci_free_consistent(adapter->pcidev, |
| 2931 | sizeof(u32) * IsrCount, |
| 2932 | adapter->Isr, adapter->PIsr); |
| 2933 | } |
| 2934 | if (adapter->XmtRingZeroIndex) { |
| 2935 | pci_free_consistent(adapter->pcidev, |
| 2936 | sizeof(u32), |
| 2937 | adapter->XmtRingZeroIndex, |
| 2938 | adapter->PXmtRingZeroIndex); |
| 2939 | } |
| 2940 | if (adapter->IndirectionTable) { |
| 2941 | pci_free_consistent(adapter->pcidev, |
| 2942 | SXG_MAX_RSS_TABLE_SIZE, |
| 2943 | adapter->IndirectionTable, |
| 2944 | adapter->PIndirectionTable); |
| 2945 | } |
| 2946 | |
| 2947 | SXG_FREE_PACKET_POOL(adapter->PacketPoolHandle); |
| 2948 | SXG_FREE_BUFFER_POOL(adapter->BufferPoolHandle); |
| 2949 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2950 | /* Unmap register spaces */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2951 | SxgUnmapResources(adapter); |
| 2952 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2953 | /* Deregister DMA */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2954 | if (adapter->DmaHandle) { |
| 2955 | SXG_DEREGISTER_DMA(adapter->DmaHandle); |
| 2956 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2957 | /* Deregister interrupt */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2958 | SxgDeregisterInterrupt(adapter); |
| 2959 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 2960 | /* Possibly free system info (5.2 only) */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 2961 | SXG_RELEASE_SYSTEM_INFO(adapter); |
| 2962 | |
| 2963 | SxgDiagFreeResources(adapter); |
| 2964 | |
| 2965 | SxgFreeMCastAddrs(adapter); |
| 2966 | |
| 2967 | if (SXG_TIMER_ALLOCATED(adapter->ResetTimer)) { |
| 2968 | SXG_CANCEL_TIMER(adapter->ResetTimer, TimerCancelled); |
| 2969 | SXG_FREE_TIMER(adapter->ResetTimer); |
| 2970 | } |
| 2971 | if (SXG_TIMER_ALLOCATED(adapter->RssTimer)) { |
| 2972 | SXG_CANCEL_TIMER(adapter->RssTimer, TimerCancelled); |
| 2973 | SXG_FREE_TIMER(adapter->RssTimer); |
| 2974 | } |
| 2975 | if (SXG_TIMER_ALLOCATED(adapter->OffloadTimer)) { |
| 2976 | SXG_CANCEL_TIMER(adapter->OffloadTimer, TimerCancelled); |
| 2977 | SXG_FREE_TIMER(adapter->OffloadTimer); |
| 2978 | } |
| 2979 | |
| 2980 | adapter->BasicAllocations = FALSE; |
| 2981 | |
| 2982 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XFreeRes", |
| 2983 | adapter, adapter->MaxTcbs, 0, 0); |
| 2984 | } |
| 2985 | #endif |
| 2986 | |
| 2987 | /* |
| 2988 | * sxg_allocate_complete - |
| 2989 | * |
| 2990 | * This routine is called when a memory allocation has completed. |
| 2991 | * |
| 2992 | * Arguments - |
| 2993 | * p_adapter_t - Our adapter structure |
| 2994 | * VirtualAddress - Memory virtual address |
| 2995 | * PhysicalAddress - Memory physical address |
| 2996 | * Length - Length of memory allocated (or 0) |
| 2997 | * Context - The type of buffer allocated |
| 2998 | * |
| 2999 | * Return |
| 3000 | * None. |
| 3001 | */ |
| 3002 | static void sxg_allocate_complete(p_adapter_t adapter, |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 3003 | void *VirtualAddress, |
| 3004 | dma_addr_t PhysicalAddress, |
| 3005 | u32 Length, SXG_BUFFER_TYPE Context) |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3006 | { |
| 3007 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AllocCmp", |
| 3008 | adapter, VirtualAddress, Length, Context); |
| 3009 | ASSERT(adapter->AllocationsPending); |
| 3010 | --adapter->AllocationsPending; |
| 3011 | |
| 3012 | switch (Context) { |
| 3013 | |
| 3014 | case SXG_BUFFER_TYPE_RCV: |
| 3015 | sxg_allocate_rcvblock_complete(adapter, |
| 3016 | VirtualAddress, |
| 3017 | PhysicalAddress, Length); |
| 3018 | break; |
| 3019 | case SXG_BUFFER_TYPE_SGL: |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 3020 | sxg_allocate_sgl_buffer_complete(adapter, (PSXG_SCATTER_GATHER) |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3021 | VirtualAddress, |
| 3022 | PhysicalAddress, Length); |
| 3023 | break; |
| 3024 | } |
| 3025 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlocCmp", |
| 3026 | adapter, VirtualAddress, Length, Context); |
| 3027 | } |
| 3028 | |
| 3029 | /* |
| 3030 | * sxg_allocate_buffer_memory - Shared memory allocation routine used for |
| 3031 | * synchronous and asynchronous buffer allocations |
| 3032 | * |
| 3033 | * Arguments - |
| 3034 | * adapter - A pointer to our adapter structure |
| 3035 | * Size - block size to allocate |
| 3036 | * BufferType - Type of buffer to allocate |
| 3037 | * |
| 3038 | * Return |
| 3039 | * int |
| 3040 | */ |
| 3041 | static int sxg_allocate_buffer_memory(p_adapter_t adapter, |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 3042 | u32 Size, SXG_BUFFER_TYPE BufferType) |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3043 | { |
| 3044 | int status; |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 3045 | void *Buffer; |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3046 | dma_addr_t pBuffer; |
| 3047 | |
| 3048 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AllocMem", |
| 3049 | adapter, Size, BufferType, 0); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3050 | /* Grab the adapter lock and check the state. */ |
| 3051 | /* If we're in anything other than INITIALIZING or */ |
| 3052 | /* RUNNING state, fail. This is to prevent */ |
| 3053 | /* allocations in an improper driver state */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3054 | spin_lock(&adapter->AdapterLock); |
| 3055 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3056 | /* Increment the AllocationsPending count while holding */ |
| 3057 | /* the lock. Pause processing relies on this */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3058 | ++adapter->AllocationsPending; |
| 3059 | spin_unlock(&adapter->AdapterLock); |
| 3060 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3061 | /* At initialization time allocate resources synchronously. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3062 | Buffer = pci_alloc_consistent(adapter->pcidev, Size, &pBuffer); |
| 3063 | if (Buffer == NULL) { |
| 3064 | spin_lock(&adapter->AdapterLock); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3065 | /* Decrement the AllocationsPending count while holding */ |
| 3066 | /* the lock. Pause processing relies on this */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3067 | --adapter->AllocationsPending; |
| 3068 | spin_unlock(&adapter->AdapterLock); |
| 3069 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AlcMemF1", |
| 3070 | adapter, Size, BufferType, 0); |
| 3071 | return (STATUS_RESOURCES); |
| 3072 | } |
| 3073 | sxg_allocate_complete(adapter, Buffer, pBuffer, Size, BufferType); |
| 3074 | status = STATUS_SUCCESS; |
| 3075 | |
| 3076 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlocMem", |
| 3077 | adapter, Size, BufferType, status); |
| 3078 | return (status); |
| 3079 | } |
| 3080 | |
| 3081 | /* |
| 3082 | * sxg_allocate_rcvblock_complete - Complete a receive descriptor block allocation |
| 3083 | * |
| 3084 | * Arguments - |
| 3085 | * adapter - A pointer to our adapter structure |
| 3086 | * RcvBlock - receive block virtual address |
| 3087 | * PhysicalAddress - Physical address |
| 3088 | * Length - Memory length |
| 3089 | * |
| 3090 | * Return |
| 3091 | * |
| 3092 | */ |
| 3093 | static void sxg_allocate_rcvblock_complete(p_adapter_t adapter, |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 3094 | void *RcvBlock, |
| 3095 | dma_addr_t PhysicalAddress, |
| 3096 | u32 Length) |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3097 | { |
| 3098 | u32 i; |
| 3099 | u32 BufferSize = adapter->ReceiveBufferSize; |
| 3100 | u64 Paddr; |
| 3101 | PSXG_RCV_BLOCK_HDR RcvBlockHdr; |
| 3102 | unsigned char *RcvDataBuffer; |
| 3103 | PSXG_RCV_DATA_BUFFER_HDR RcvDataBufferHdr; |
| 3104 | PSXG_RCV_DESCRIPTOR_BLOCK RcvDescriptorBlock; |
| 3105 | PSXG_RCV_DESCRIPTOR_BLOCK_HDR RcvDescriptorBlockHdr; |
| 3106 | |
| 3107 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AlRcvBlk", |
| 3108 | adapter, RcvBlock, Length, 0); |
| 3109 | if (RcvBlock == NULL) { |
| 3110 | goto fail; |
| 3111 | } |
| 3112 | memset(RcvBlock, 0, Length); |
| 3113 | ASSERT((BufferSize == SXG_RCV_DATA_BUFFER_SIZE) || |
| 3114 | (BufferSize == SXG_RCV_JUMBO_BUFFER_SIZE)); |
| 3115 | ASSERT(Length == SXG_RCV_BLOCK_SIZE(BufferSize)); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3116 | /* First, initialize the contained pool of receive data */ |
| 3117 | /* buffers. This initialization requires NBL/NB/MDL allocations, */ |
| 3118 | /* If any of them fail, free the block and return without */ |
| 3119 | /* queueing the shared memory */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3120 | RcvDataBuffer = RcvBlock; |
| 3121 | #if 0 |
| 3122 | for (i = 0, Paddr = *PhysicalAddress; |
| 3123 | i < SXG_RCV_DESCRIPTORS_PER_BLOCK; |
| 3124 | i++, Paddr.LowPart += BufferSize, RcvDataBuffer += BufferSize) |
| 3125 | #endif |
| 3126 | for (i = 0, Paddr = PhysicalAddress; |
| 3127 | i < SXG_RCV_DESCRIPTORS_PER_BLOCK; |
| 3128 | i++, Paddr += BufferSize, RcvDataBuffer += BufferSize) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3129 | /* */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3130 | RcvDataBufferHdr = |
| 3131 | (PSXG_RCV_DATA_BUFFER_HDR) (RcvDataBuffer + |
| 3132 | SXG_RCV_DATA_BUFFER_HDR_OFFSET |
| 3133 | (BufferSize)); |
| 3134 | RcvDataBufferHdr->VirtualAddress = RcvDataBuffer; |
| 3135 | RcvDataBufferHdr->PhysicalAddress = Paddr; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3136 | RcvDataBufferHdr->State = SXG_BUFFER_UPSTREAM; /* For FREE macro assertion */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3137 | RcvDataBufferHdr->Size = |
| 3138 | SXG_RCV_BUFFER_DATA_SIZE(BufferSize); |
| 3139 | |
| 3140 | SXG_ALLOCATE_RCV_PACKET(adapter, RcvDataBufferHdr); |
| 3141 | if (RcvDataBufferHdr->SxgDumbRcvPacket == NULL) |
| 3142 | goto fail; |
| 3143 | |
| 3144 | } |
| 3145 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3146 | /* Place this entire block of memory on the AllRcvBlocks queue so it can be */ |
| 3147 | /* free later */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3148 | RcvBlockHdr = |
| 3149 | (PSXG_RCV_BLOCK_HDR) ((unsigned char *)RcvBlock + |
| 3150 | SXG_RCV_BLOCK_HDR_OFFSET(BufferSize)); |
| 3151 | RcvBlockHdr->VirtualAddress = RcvBlock; |
| 3152 | RcvBlockHdr->PhysicalAddress = PhysicalAddress; |
| 3153 | spin_lock(&adapter->RcvQLock); |
| 3154 | adapter->AllRcvBlockCount++; |
| 3155 | InsertTailList(&adapter->AllRcvBlocks, &RcvBlockHdr->AllList); |
| 3156 | spin_unlock(&adapter->RcvQLock); |
| 3157 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3158 | /* Now free the contained receive data buffers that we initialized above */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3159 | RcvDataBuffer = RcvBlock; |
| 3160 | for (i = 0, Paddr = PhysicalAddress; |
| 3161 | i < SXG_RCV_DESCRIPTORS_PER_BLOCK; |
| 3162 | i++, Paddr += BufferSize, RcvDataBuffer += BufferSize) { |
| 3163 | RcvDataBufferHdr = (PSXG_RCV_DATA_BUFFER_HDR) (RcvDataBuffer + |
| 3164 | SXG_RCV_DATA_BUFFER_HDR_OFFSET |
| 3165 | (BufferSize)); |
| 3166 | spin_lock(&adapter->RcvQLock); |
| 3167 | SXG_FREE_RCV_DATA_BUFFER(adapter, RcvDataBufferHdr); |
| 3168 | spin_unlock(&adapter->RcvQLock); |
| 3169 | } |
| 3170 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3171 | /* Locate the descriptor block and put it on a separate free queue */ |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 3172 | RcvDescriptorBlock = |
| 3173 | (PSXG_RCV_DESCRIPTOR_BLOCK) ((unsigned char *)RcvBlock + |
| 3174 | SXG_RCV_DESCRIPTOR_BLOCK_OFFSET |
| 3175 | (BufferSize)); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3176 | RcvDescriptorBlockHdr = |
| 3177 | (PSXG_RCV_DESCRIPTOR_BLOCK_HDR) ((unsigned char *)RcvBlock + |
| 3178 | SXG_RCV_DESCRIPTOR_BLOCK_HDR_OFFSET |
| 3179 | (BufferSize)); |
| 3180 | RcvDescriptorBlockHdr->VirtualAddress = RcvDescriptorBlock; |
| 3181 | RcvDescriptorBlockHdr->PhysicalAddress = Paddr; |
| 3182 | spin_lock(&adapter->RcvQLock); |
| 3183 | SXG_FREE_RCV_DESCRIPTOR_BLOCK(adapter, RcvDescriptorBlockHdr); |
| 3184 | spin_unlock(&adapter->RcvQLock); |
| 3185 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlRBlk", |
| 3186 | adapter, RcvBlock, Length, 0); |
| 3187 | return; |
| 3188 | fail: |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3189 | /* Free any allocated resources */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3190 | if (RcvBlock) { |
| 3191 | RcvDataBuffer = RcvBlock; |
| 3192 | for (i = 0; i < SXG_RCV_DESCRIPTORS_PER_BLOCK; |
| 3193 | i++, RcvDataBuffer += BufferSize) { |
| 3194 | RcvDataBufferHdr = |
| 3195 | (PSXG_RCV_DATA_BUFFER_HDR) (RcvDataBuffer + |
| 3196 | SXG_RCV_DATA_BUFFER_HDR_OFFSET |
| 3197 | (BufferSize)); |
| 3198 | SXG_FREE_RCV_PACKET(RcvDataBufferHdr); |
| 3199 | } |
| 3200 | pci_free_consistent(adapter->pcidev, |
| 3201 | Length, RcvBlock, PhysicalAddress); |
| 3202 | } |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 3203 | DBG_ERROR("%s: OUT OF RESOURCES\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3204 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "RcvAFail", |
| 3205 | adapter, adapter->FreeRcvBufferCount, |
| 3206 | adapter->FreeRcvBlockCount, adapter->AllRcvBlockCount); |
| 3207 | adapter->Stats.NoMem++; |
| 3208 | } |
| 3209 | |
| 3210 | /* |
| 3211 | * sxg_allocate_sgl_buffer_complete - Complete a SGL buffer allocation |
| 3212 | * |
| 3213 | * Arguments - |
| 3214 | * adapter - A pointer to our adapter structure |
| 3215 | * SxgSgl - SXG_SCATTER_GATHER buffer |
| 3216 | * PhysicalAddress - Physical address |
| 3217 | * Length - Memory length |
| 3218 | * |
| 3219 | * Return |
| 3220 | * |
| 3221 | */ |
| 3222 | static void sxg_allocate_sgl_buffer_complete(p_adapter_t adapter, |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 3223 | PSXG_SCATTER_GATHER SxgSgl, |
| 3224 | dma_addr_t PhysicalAddress, |
| 3225 | u32 Length) |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3226 | { |
| 3227 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AlSglCmp", |
| 3228 | adapter, SxgSgl, Length, 0); |
| 3229 | spin_lock(&adapter->SglQLock); |
| 3230 | adapter->AllSglBufferCount++; |
| 3231 | memset(SxgSgl, 0, sizeof(SXG_SCATTER_GATHER)); |
| 3232 | SxgSgl->PhysicalAddress = PhysicalAddress; /* *PhysicalAddress; */ |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3233 | SxgSgl->adapter = adapter; /* Initialize backpointer once */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3234 | InsertTailList(&adapter->AllSglBuffers, &SxgSgl->AllList); |
| 3235 | spin_unlock(&adapter->SglQLock); |
| 3236 | SxgSgl->State = SXG_BUFFER_BUSY; |
| 3237 | SXG_FREE_SGL_BUFFER(adapter, SxgSgl, NULL); |
| 3238 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlSgl", |
| 3239 | adapter, SxgSgl, Length, 0); |
| 3240 | } |
| 3241 | |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 3242 | static unsigned char temp_mac_address[6] = |
| 3243 | { 0x00, 0xab, 0xcd, 0xef, 0x12, 0x69 }; |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3244 | |
| 3245 | static void sxg_adapter_set_hwaddr(p_adapter_t adapter) |
| 3246 | { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3247 | /* DBG_ERROR ("%s ENTER card->config_set[%x] port[%d] physport[%d] funct#[%d]\n", __func__, */ |
| 3248 | /* card->config_set, adapter->port, adapter->physport, adapter->functionnumber); */ |
| 3249 | /* */ |
| 3250 | /* sxg_dbg_macaddrs(adapter); */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3251 | |
| 3252 | memcpy(adapter->macaddr, temp_mac_address, sizeof(SXG_CONFIG_MAC)); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3253 | /* DBG_ERROR ("%s AFTER copying from config.macinfo into currmacaddr\n", __func__); */ |
| 3254 | /* sxg_dbg_macaddrs(adapter); */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3255 | if (!(adapter->currmacaddr[0] || |
| 3256 | adapter->currmacaddr[1] || |
| 3257 | adapter->currmacaddr[2] || |
| 3258 | adapter->currmacaddr[3] || |
| 3259 | adapter->currmacaddr[4] || adapter->currmacaddr[5])) { |
| 3260 | memcpy(adapter->currmacaddr, adapter->macaddr, 6); |
| 3261 | } |
| 3262 | if (adapter->netdev) { |
| 3263 | memcpy(adapter->netdev->dev_addr, adapter->currmacaddr, 6); |
| 3264 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3265 | /* DBG_ERROR ("%s EXIT port %d\n", __func__, adapter->port); */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3266 | sxg_dbg_macaddrs(adapter); |
| 3267 | |
| 3268 | } |
| 3269 | |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 3270 | static int sxg_mac_set_address(p_net_device dev, void *ptr) |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3271 | { |
| 3272 | #if XXXTODO |
| 3273 | p_adapter_t adapter = (p_adapter_t) netdev_priv(dev); |
| 3274 | struct sockaddr *addr = ptr; |
| 3275 | |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 3276 | DBG_ERROR("%s ENTER (%s)\n", __func__, adapter->netdev->name); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3277 | |
| 3278 | if (netif_running(dev)) { |
| 3279 | return -EBUSY; |
| 3280 | } |
| 3281 | if (!adapter) { |
| 3282 | return -EBUSY; |
| 3283 | } |
| 3284 | DBG_ERROR("sxg: %s (%s) curr %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 3285 | __func__, adapter->netdev->name, adapter->currmacaddr[0], |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3286 | adapter->currmacaddr[1], adapter->currmacaddr[2], |
| 3287 | adapter->currmacaddr[3], adapter->currmacaddr[4], |
| 3288 | adapter->currmacaddr[5]); |
| 3289 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
| 3290 | memcpy(adapter->currmacaddr, addr->sa_data, dev->addr_len); |
| 3291 | DBG_ERROR("sxg: %s (%s) new %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n", |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 3292 | __func__, adapter->netdev->name, adapter->currmacaddr[0], |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3293 | adapter->currmacaddr[1], adapter->currmacaddr[2], |
| 3294 | adapter->currmacaddr[3], adapter->currmacaddr[4], |
| 3295 | adapter->currmacaddr[5]); |
| 3296 | |
| 3297 | sxg_config_set(adapter, TRUE); |
| 3298 | #endif |
| 3299 | return 0; |
| 3300 | } |
| 3301 | |
| 3302 | /*****************************************************************************/ |
| 3303 | /************* SXG DRIVER FUNCTIONS (below) ********************************/ |
| 3304 | /*****************************************************************************/ |
| 3305 | |
| 3306 | /* |
| 3307 | * sxg_initialize_adapter - Initialize adapter |
| 3308 | * |
| 3309 | * Arguments - |
| 3310 | * adapter - A pointer to our adapter structure |
| 3311 | * |
| 3312 | * Return |
| 3313 | * int |
| 3314 | */ |
| 3315 | static int sxg_initialize_adapter(p_adapter_t adapter) |
| 3316 | { |
| 3317 | u32 RssIds, IsrCount; |
| 3318 | u32 i; |
| 3319 | int status; |
| 3320 | |
| 3321 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "InitAdpt", |
| 3322 | adapter, 0, 0, 0); |
| 3323 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3324 | RssIds = 1; /* XXXTODO SXG_RSS_CPU_COUNT(adapter); */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3325 | IsrCount = adapter->MsiEnabled ? RssIds : 1; |
| 3326 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3327 | /* Sanity check SXG_UCODE_REGS structure definition to */ |
| 3328 | /* make sure the length is correct */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3329 | ASSERT(sizeof(SXG_UCODE_REGS) == SXG_REGISTER_SIZE_PER_CPU); |
| 3330 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3331 | /* Disable interrupts */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3332 | SXG_DISABLE_ALL_INTERRUPTS(adapter); |
| 3333 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3334 | /* Set MTU */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3335 | ASSERT((adapter->FrameSize == ETHERMAXFRAME) || |
| 3336 | (adapter->FrameSize == JUMBOMAXFRAME)); |
| 3337 | WRITE_REG(adapter->UcodeRegs[0].LinkMtu, adapter->FrameSize, TRUE); |
| 3338 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3339 | /* Set event ring base address and size */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3340 | WRITE_REG64(adapter, |
| 3341 | adapter->UcodeRegs[0].EventBase, adapter->PEventRings, 0); |
| 3342 | WRITE_REG(adapter->UcodeRegs[0].EventSize, EVENT_RING_SIZE, TRUE); |
| 3343 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3344 | /* Per-ISR initialization */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3345 | for (i = 0; i < IsrCount; i++) { |
| 3346 | u64 Addr; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3347 | /* Set interrupt status pointer */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3348 | Addr = adapter->PIsr + (i * sizeof(u32)); |
| 3349 | WRITE_REG64(adapter, adapter->UcodeRegs[i].Isp, Addr, i); |
| 3350 | } |
| 3351 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3352 | /* XMT ring zero index */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3353 | WRITE_REG64(adapter, |
| 3354 | adapter->UcodeRegs[0].SPSendIndex, |
| 3355 | adapter->PXmtRingZeroIndex, 0); |
| 3356 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3357 | /* Per-RSS initialization */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3358 | for (i = 0; i < RssIds; i++) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3359 | /* Release all event ring entries to the Microcode */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3360 | WRITE_REG(adapter->UcodeRegs[i].EventRelease, EVENT_RING_SIZE, |
| 3361 | TRUE); |
| 3362 | } |
| 3363 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3364 | /* Transmit ring base and size */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3365 | WRITE_REG64(adapter, |
| 3366 | adapter->UcodeRegs[0].XmtBase, adapter->PXmtRings, 0); |
| 3367 | WRITE_REG(adapter->UcodeRegs[0].XmtSize, SXG_XMT_RING_SIZE, TRUE); |
| 3368 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3369 | /* Receive ring base and size */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3370 | WRITE_REG64(adapter, |
| 3371 | adapter->UcodeRegs[0].RcvBase, adapter->PRcvRings, 0); |
| 3372 | WRITE_REG(adapter->UcodeRegs[0].RcvSize, SXG_RCV_RING_SIZE, TRUE); |
| 3373 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3374 | /* Populate the card with receive buffers */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3375 | sxg_stock_rcv_buffers(adapter); |
| 3376 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3377 | /* Initialize checksum offload capabilities. At the moment */ |
| 3378 | /* we always enable IP and TCP receive checksums on the card. */ |
| 3379 | /* Depending on the checksum configuration specified by the */ |
| 3380 | /* user, we can choose to report or ignore the checksum */ |
| 3381 | /* information provided by the card. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3382 | WRITE_REG(adapter->UcodeRegs[0].ReceiveChecksum, |
| 3383 | SXG_RCV_TCP_CSUM_ENABLED | SXG_RCV_IP_CSUM_ENABLED, TRUE); |
| 3384 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3385 | /* Initialize the MAC, XAUI */ |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 3386 | DBG_ERROR("sxg: %s ENTER sxg_initialize_link\n", __func__); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3387 | status = sxg_initialize_link(adapter); |
Harvey Harrison | e88bd23 | 2008-10-17 14:46:10 -0700 | [diff] [blame] | 3388 | DBG_ERROR("sxg: %s EXIT sxg_initialize_link status[%x]\n", __func__, |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3389 | status); |
| 3390 | if (status != STATUS_SUCCESS) { |
| 3391 | return (status); |
| 3392 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3393 | /* Initialize Dead to FALSE. */ |
| 3394 | /* SlicCheckForHang or SlicDumpThread will take it from here. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3395 | adapter->Dead = FALSE; |
| 3396 | adapter->PingOutstanding = FALSE; |
| 3397 | |
| 3398 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XInit", |
| 3399 | adapter, 0, 0, 0); |
| 3400 | return (STATUS_SUCCESS); |
| 3401 | } |
| 3402 | |
| 3403 | /* |
| 3404 | * sxg_fill_descriptor_block - Populate a descriptor block and give it to |
| 3405 | * the card. The caller should hold the RcvQLock |
| 3406 | * |
| 3407 | * Arguments - |
| 3408 | * adapter - A pointer to our adapter structure |
| 3409 | * RcvDescriptorBlockHdr - Descriptor block to fill |
| 3410 | * |
| 3411 | * Return |
| 3412 | * status |
| 3413 | */ |
| 3414 | static int sxg_fill_descriptor_block(p_adapter_t adapter, |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 3415 | PSXG_RCV_DESCRIPTOR_BLOCK_HDR |
| 3416 | RcvDescriptorBlockHdr) |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3417 | { |
| 3418 | u32 i; |
| 3419 | PSXG_RING_INFO RcvRingInfo = &adapter->RcvRingZeroInfo; |
| 3420 | PSXG_RCV_DATA_BUFFER_HDR RcvDataBufferHdr; |
| 3421 | PSXG_RCV_DESCRIPTOR_BLOCK RcvDescriptorBlock; |
| 3422 | PSXG_CMD RingDescriptorCmd; |
| 3423 | PSXG_RCV_RING RingZero = &adapter->RcvRings[0]; |
| 3424 | |
| 3425 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "FilBlk", |
| 3426 | adapter, adapter->RcvBuffersOnCard, |
| 3427 | adapter->FreeRcvBufferCount, adapter->AllRcvBlockCount); |
| 3428 | |
| 3429 | ASSERT(RcvDescriptorBlockHdr); |
| 3430 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3431 | /* If we don't have the resources to fill the descriptor block, */ |
| 3432 | /* return failure */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3433 | if ((adapter->FreeRcvBufferCount < SXG_RCV_DESCRIPTORS_PER_BLOCK) || |
| 3434 | SXG_RING_FULL(RcvRingInfo)) { |
| 3435 | adapter->Stats.NoMem++; |
| 3436 | return (STATUS_FAILURE); |
| 3437 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3438 | /* Get a ring descriptor command */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3439 | SXG_GET_CMD(RingZero, |
| 3440 | RcvRingInfo, RingDescriptorCmd, RcvDescriptorBlockHdr); |
| 3441 | ASSERT(RingDescriptorCmd); |
| 3442 | RcvDescriptorBlockHdr->State = SXG_BUFFER_ONCARD; |
| 3443 | RcvDescriptorBlock = |
| 3444 | (PSXG_RCV_DESCRIPTOR_BLOCK) RcvDescriptorBlockHdr->VirtualAddress; |
| 3445 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3446 | /* Fill in the descriptor block */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3447 | for (i = 0; i < SXG_RCV_DESCRIPTORS_PER_BLOCK; i++) { |
| 3448 | SXG_GET_RCV_DATA_BUFFER(adapter, RcvDataBufferHdr); |
| 3449 | ASSERT(RcvDataBufferHdr); |
| 3450 | SXG_REINIATIALIZE_PACKET(RcvDataBufferHdr->SxgDumbRcvPacket); |
| 3451 | RcvDataBufferHdr->State = SXG_BUFFER_ONCARD; |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 3452 | RcvDescriptorBlock->Descriptors[i].VirtualAddress = |
| 3453 | (void *)RcvDataBufferHdr; |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3454 | RcvDescriptorBlock->Descriptors[i].PhysicalAddress = |
| 3455 | RcvDataBufferHdr->PhysicalAddress; |
| 3456 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3457 | /* Add the descriptor block to receive descriptor ring 0 */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3458 | RingDescriptorCmd->Sgl = RcvDescriptorBlockHdr->PhysicalAddress; |
| 3459 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3460 | /* RcvBuffersOnCard is not protected via the receive lock (see */ |
| 3461 | /* sxg_process_event_queue) We don't want to grap a lock every time a */ |
| 3462 | /* buffer is returned to us, so we use atomic interlocked functions */ |
| 3463 | /* instead. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3464 | adapter->RcvBuffersOnCard += SXG_RCV_DESCRIPTORS_PER_BLOCK; |
| 3465 | |
| 3466 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DscBlk", |
| 3467 | RcvDescriptorBlockHdr, |
| 3468 | RingDescriptorCmd, RcvRingInfo->Head, RcvRingInfo->Tail); |
| 3469 | |
| 3470 | WRITE_REG(adapter->UcodeRegs[0].RcvCmd, 1, true); |
| 3471 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XFilBlk", |
| 3472 | adapter, adapter->RcvBuffersOnCard, |
| 3473 | adapter->FreeRcvBufferCount, adapter->AllRcvBlockCount); |
| 3474 | return (STATUS_SUCCESS); |
| 3475 | } |
| 3476 | |
| 3477 | /* |
| 3478 | * sxg_stock_rcv_buffers - Stock the card with receive buffers |
| 3479 | * |
| 3480 | * Arguments - |
| 3481 | * adapter - A pointer to our adapter structure |
| 3482 | * |
| 3483 | * Return |
| 3484 | * None |
| 3485 | */ |
| 3486 | static void sxg_stock_rcv_buffers(p_adapter_t adapter) |
| 3487 | { |
| 3488 | PSXG_RCV_DESCRIPTOR_BLOCK_HDR RcvDescriptorBlockHdr; |
| 3489 | |
| 3490 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "StockBuf", |
| 3491 | adapter, adapter->RcvBuffersOnCard, |
| 3492 | adapter->FreeRcvBufferCount, adapter->AllRcvBlockCount); |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3493 | /* First, see if we've got less than our minimum threshold of */ |
| 3494 | /* receive buffers, there isn't an allocation in progress, and */ |
| 3495 | /* we haven't exceeded our maximum.. get another block of buffers */ |
| 3496 | /* None of this needs to be SMP safe. It's round numbers. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3497 | if ((adapter->FreeRcvBufferCount < SXG_MIN_RCV_DATA_BUFFERS) && |
| 3498 | (adapter->AllRcvBlockCount < SXG_MAX_RCV_BLOCKS) && |
| 3499 | (adapter->AllocationsPending == 0)) { |
| 3500 | sxg_allocate_buffer_memory(adapter, |
| 3501 | SXG_RCV_BLOCK_SIZE(adapter-> |
| 3502 | ReceiveBufferSize), |
| 3503 | SXG_BUFFER_TYPE_RCV); |
| 3504 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3505 | /* Now grab the RcvQLock lock and proceed */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3506 | spin_lock(&adapter->RcvQLock); |
| 3507 | while (adapter->RcvBuffersOnCard < SXG_RCV_DATA_BUFFERS) { |
| 3508 | PLIST_ENTRY _ple; |
| 3509 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3510 | /* Get a descriptor block */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3511 | RcvDescriptorBlockHdr = NULL; |
| 3512 | if (adapter->FreeRcvBlockCount) { |
| 3513 | _ple = RemoveHeadList(&adapter->FreeRcvBlocks); |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 3514 | RcvDescriptorBlockHdr = |
| 3515 | container_of(_ple, SXG_RCV_DESCRIPTOR_BLOCK_HDR, |
| 3516 | FreeList); |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3517 | adapter->FreeRcvBlockCount--; |
| 3518 | RcvDescriptorBlockHdr->State = SXG_BUFFER_BUSY; |
| 3519 | } |
| 3520 | |
| 3521 | if (RcvDescriptorBlockHdr == NULL) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3522 | /* Bail out.. */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3523 | adapter->Stats.NoMem++; |
| 3524 | break; |
| 3525 | } |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3526 | /* Fill in the descriptor block and give it to the card */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3527 | if (sxg_fill_descriptor_block(adapter, RcvDescriptorBlockHdr) == |
| 3528 | STATUS_FAILURE) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3529 | /* Free the descriptor block */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3530 | SXG_FREE_RCV_DESCRIPTOR_BLOCK(adapter, |
| 3531 | RcvDescriptorBlockHdr); |
| 3532 | break; |
| 3533 | } |
| 3534 | } |
| 3535 | spin_unlock(&adapter->RcvQLock); |
| 3536 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XFilBlks", |
| 3537 | adapter, adapter->RcvBuffersOnCard, |
| 3538 | adapter->FreeRcvBufferCount, adapter->AllRcvBlockCount); |
| 3539 | } |
| 3540 | |
| 3541 | /* |
| 3542 | * sxg_complete_descriptor_blocks - Return descriptor blocks that have been |
| 3543 | * completed by the microcode |
| 3544 | * |
| 3545 | * Arguments - |
| 3546 | * adapter - A pointer to our adapter structure |
| 3547 | * Index - Where the microcode is up to |
| 3548 | * |
| 3549 | * Return |
| 3550 | * None |
| 3551 | */ |
J.R. Mauro | 5c7514e | 2008-10-05 20:38:52 -0400 | [diff] [blame] | 3552 | static void sxg_complete_descriptor_blocks(p_adapter_t adapter, |
| 3553 | unsigned char Index) |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3554 | { |
| 3555 | PSXG_RCV_RING RingZero = &adapter->RcvRings[0]; |
| 3556 | PSXG_RING_INFO RcvRingInfo = &adapter->RcvRingZeroInfo; |
| 3557 | PSXG_RCV_DESCRIPTOR_BLOCK_HDR RcvDescriptorBlockHdr; |
| 3558 | PSXG_CMD RingDescriptorCmd; |
| 3559 | |
| 3560 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpRBlks", |
| 3561 | adapter, Index, RcvRingInfo->Head, RcvRingInfo->Tail); |
| 3562 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3563 | /* Now grab the RcvQLock lock and proceed */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3564 | spin_lock(&adapter->RcvQLock); |
| 3565 | ASSERT(Index != RcvRingInfo->Tail); |
| 3566 | while (RcvRingInfo->Tail != Index) { |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3567 | /* */ |
| 3568 | /* Locate the current Cmd (ring descriptor entry), and */ |
| 3569 | /* associated receive descriptor block, and advance */ |
| 3570 | /* the tail */ |
| 3571 | /* */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3572 | SXG_RETURN_CMD(RingZero, |
| 3573 | RcvRingInfo, |
| 3574 | RingDescriptorCmd, RcvDescriptorBlockHdr); |
| 3575 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpRBlk", |
| 3576 | RcvRingInfo->Head, RcvRingInfo->Tail, |
| 3577 | RingDescriptorCmd, RcvDescriptorBlockHdr); |
| 3578 | |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3579 | /* Clear the SGL field */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3580 | RingDescriptorCmd->Sgl = 0; |
J.R. Mauro | b243c4a | 2008-10-20 19:28:58 -0400 | [diff] [blame^] | 3581 | /* Attempt to refill it and hand it right back to the */ |
| 3582 | /* card. If we fail to refill it, free the descriptor block */ |
| 3583 | /* header. The card will be restocked later via the */ |
| 3584 | /* RcvBuffersOnCard test */ |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3585 | if (sxg_fill_descriptor_block(adapter, RcvDescriptorBlockHdr) == |
| 3586 | STATUS_FAILURE) { |
| 3587 | SXG_FREE_RCV_DESCRIPTOR_BLOCK(adapter, |
| 3588 | RcvDescriptorBlockHdr); |
| 3589 | } |
| 3590 | } |
| 3591 | spin_unlock(&adapter->RcvQLock); |
| 3592 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XCRBlks", |
| 3593 | adapter, Index, RcvRingInfo->Head, RcvRingInfo->Tail); |
| 3594 | } |
| 3595 | |
Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame] | 3596 | static struct pci_driver sxg_driver = { |
| 3597 | .name = DRV_NAME, |
| 3598 | .id_table = sxg_pci_tbl, |
| 3599 | .probe = sxg_entry_probe, |
| 3600 | .remove = sxg_entry_remove, |
| 3601 | #if SXG_POWER_MANAGEMENT_ENABLED |
| 3602 | .suspend = sxgpm_suspend, |
| 3603 | .resume = sxgpm_resume, |
| 3604 | #endif |
| 3605 | /* .shutdown = slic_shutdown, MOOK_INVESTIGATE */ |
| 3606 | }; |
| 3607 | |
| 3608 | static int __init sxg_module_init(void) |
| 3609 | { |
| 3610 | sxg_init_driver(); |
| 3611 | |
| 3612 | if (debug >= 0) |
| 3613 | sxg_debug = debug; |
| 3614 | |
| 3615 | return pci_register_driver(&sxg_driver); |
| 3616 | } |
| 3617 | |
| 3618 | static void __exit sxg_module_cleanup(void) |
| 3619 | { |
| 3620 | pci_unregister_driver(&sxg_driver); |
| 3621 | } |
| 3622 | |
| 3623 | module_init(sxg_module_init); |
| 3624 | module_exit(sxg_module_cleanup); |