Chanwoo Choi | 1a21dfe | 2015-02-03 08:47:11 +0900 | [diff] [blame] | 1 | * Samsung Exynos5433 CMU (Clock Management Units) |
| 2 | |
| 3 | The Exynos5433 clock controller generates and supplies clock to various |
| 4 | controllers within the Exynos5433 SoC. |
| 5 | |
| 6 | Required Properties: |
| 7 | |
| 8 | - compatible: should be one of the following. |
| 9 | - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP |
| 10 | which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS |
| 11 | domains and bus clocks. |
| 12 | - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF |
| 13 | which generates clocks for LLI (Low Latency Interface) IP. |
| 14 | - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF |
| 15 | which generates clocks for DRAM Memory Controller domain. |
| 16 | - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC |
| 17 | which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs. |
| 18 | - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS |
| 19 | which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs. |
| 20 | - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS |
| 21 | which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs. |
| 22 | - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D |
| 23 | which generates clocks for G2D/MDMA IPs. |
| 24 | - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP |
| 25 | which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs. |
| 26 | - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD |
| 27 | which generates clocks for Cortex-A5/BUS/AUDIO clocks. |
| 28 | - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1" |
| 29 | and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS |
| 30 | which generates global data buses clock and global peripheral buses clock. |
| 31 | - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D |
| 32 | which generates clocks for 3D Graphics Engine IP. |
| 33 | - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL |
| 34 | which generates clocks for GSCALER IPs. |
Chanwoo Choi | df40a13 | 2015-02-03 09:13:49 +0900 | [diff] [blame] | 35 | - "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO |
| 36 | which generates clocks for Cortex-A53 Quad-core processor. |
Chanwoo Choi | 6c5d76d | 2015-02-03 09:13:50 +0900 | [diff] [blame] | 37 | - "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS |
| 38 | which generates clocks for Cortex-A57 Quad-core processor, CoreSight and |
| 39 | L2 cache controller. |
Chanwoo Choi | b274bbf | 2015-02-03 09:13:51 +0900 | [diff] [blame^] | 40 | - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL |
| 41 | which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs. |
Chanwoo Choi | 1a21dfe | 2015-02-03 08:47:11 +0900 | [diff] [blame] | 42 | |
| 43 | - reg: physical base address of the controller and length of memory mapped |
| 44 | region. |
| 45 | |
| 46 | - #clock-cells: should be 1. |
| 47 | |
| 48 | - clocks: list of the clock controller input clock identifiers, |
| 49 | from common clock bindings. Please refer the next section |
| 50 | to find the input clocks for a given controller. |
| 51 | |
| 52 | - clock-names: list of the clock controller input clock names, |
| 53 | as described in clock-bindings.txt. |
| 54 | |
| 55 | Input clocks for top clock controller: |
| 56 | - oscclk |
| 57 | - sclk_mphy_pll |
| 58 | - sclk_mfc_pll |
| 59 | - sclk_bus_pll |
| 60 | |
| 61 | Input clocks for cpif clock controller: |
| 62 | - oscclk |
| 63 | |
| 64 | Input clocks for mif clock controller: |
| 65 | - oscclk |
| 66 | - sclk_mphy_pll |
| 67 | |
| 68 | Input clocks for fsys clock controller: |
| 69 | - oscclk |
| 70 | - sclk_ufs_mphy |
| 71 | - div_aclk_fsys_200 |
| 72 | - sclk_pcie_100_fsys |
| 73 | - sclk_ufsunipro_fsys |
| 74 | - sclk_mmc2_fsys |
| 75 | - sclk_mmc1_fsys |
| 76 | - sclk_mmc0_fsys |
| 77 | - sclk_usbhost30_fsys |
| 78 | - sclk_usbdrd30_fsys |
| 79 | |
| 80 | Input clocks for g2d clock controller: |
| 81 | - oscclk |
| 82 | - aclk_g2d_266 |
| 83 | - aclk_g2d_400 |
| 84 | |
| 85 | Input clocks for disp clock controller: |
| 86 | - oscclk |
| 87 | - sclk_dsim1_disp |
| 88 | - sclk_dsim0_disp |
| 89 | - sclk_dsd_disp |
| 90 | - sclk_decon_tv_eclk_disp |
| 91 | - sclk_decon_vclk_disp |
| 92 | - sclk_decon_eclk_disp |
| 93 | - sclk_decon_tv_vclk_disp |
| 94 | - aclk_disp_333 |
| 95 | |
| 96 | Input clocks for bus0 clock controller: |
| 97 | - aclk_bus0_400 |
| 98 | |
| 99 | Input clocks for bus1 clock controller: |
| 100 | - aclk_bus1_400 |
| 101 | |
| 102 | Input clocks for bus2 clock controller: |
| 103 | - oscclk |
| 104 | - aclk_bus2_400 |
| 105 | |
| 106 | Input clocks for g3d clock controller: |
| 107 | - oscclk |
| 108 | - aclk_g3d_400 |
| 109 | |
| 110 | Input clocks for gscl clock controller: |
| 111 | - oscclk |
| 112 | - aclk_gscl_111 |
| 113 | - aclk_gscl_333 |
| 114 | |
Chanwoo Choi | df40a13 | 2015-02-03 09:13:49 +0900 | [diff] [blame] | 115 | Input clocks for apollo clock controller: |
| 116 | - oscclk |
| 117 | - sclk_bus_pll_apollo |
| 118 | |
Chanwoo Choi | 6c5d76d | 2015-02-03 09:13:50 +0900 | [diff] [blame] | 119 | Input clocks for atlas clock controller: |
| 120 | - oscclk |
| 121 | - sclk_bus_pll_atlas |
| 122 | |
Chanwoo Choi | b274bbf | 2015-02-03 09:13:51 +0900 | [diff] [blame^] | 123 | Input clocks for mscl clock controller: |
| 124 | - oscclk |
| 125 | - sclk_jpeg_mscl |
| 126 | - aclk_mscl_400 |
| 127 | |
Chanwoo Choi | 1a21dfe | 2015-02-03 08:47:11 +0900 | [diff] [blame] | 128 | Each clock is assigned an identifier and client nodes can use this identifier |
| 129 | to specify the clock which they consume. |
| 130 | |
| 131 | All available clocks are defined as preprocessor macros in |
| 132 | dt-bindings/clock/exynos5433.h header and can be used in device |
| 133 | tree sources. |
| 134 | |
| 135 | Example 1: Examples of 'oscclk' source clock node are listed below. |
| 136 | |
| 137 | xxti: xxti { |
| 138 | compatible = "fixed-clock"; |
| 139 | clock-output-names = "oscclk"; |
| 140 | #clock-cells = <0>; |
| 141 | }; |
| 142 | |
| 143 | Example 2: Examples of clock controller nodes are listed below. |
| 144 | |
| 145 | cmu_top: clock-controller@10030000 { |
| 146 | compatible = "samsung,exynos5433-cmu-top"; |
| 147 | reg = <0x10030000 0x0c04>; |
| 148 | #clock-cells = <1>; |
| 149 | |
| 150 | clock-names = "oscclk", |
| 151 | "sclk_mphy_pll", |
| 152 | "sclk_mfc_pll", |
| 153 | "sclk_bus_pll"; |
| 154 | clocks = <&xxti>, |
| 155 | <&cmu_cpif CLK_SCLK_MPHY_PLL>, |
| 156 | <&cmu_mif CLK_SCLK_MFC_PLL>, |
| 157 | <&cmu_mif CLK_SCLK_BUS_PLL>; |
| 158 | }; |
| 159 | |
| 160 | cmu_cpif: clock-controller@10fc0000 { |
| 161 | compatible = "samsung,exynos5433-cmu-cpif"; |
| 162 | reg = <0x10fc0000 0x0c04>; |
| 163 | #clock-cells = <1>; |
| 164 | |
| 165 | clock-names = "oscclk"; |
| 166 | clocks = <&xxti>; |
| 167 | }; |
| 168 | |
| 169 | cmu_mif: clock-controller@105b0000 { |
| 170 | compatible = "samsung,exynos5433-cmu-mif"; |
| 171 | reg = <0x105b0000 0x100c>; |
| 172 | #clock-cells = <1>; |
| 173 | |
| 174 | clock-names = "oscclk", |
| 175 | "sclk_mphy_pll"; |
| 176 | clocks = <&xxti>, |
| 177 | <&cmu_cpif CLK_SCLK_MPHY_PLL>; |
| 178 | }; |
| 179 | |
| 180 | cmu_peric: clock-controller@14c80000 { |
| 181 | compatible = "samsung,exynos5433-cmu-peric"; |
| 182 | reg = <0x14c80000 0x0b08>; |
| 183 | #clock-cells = <1>; |
| 184 | }; |
| 185 | |
| 186 | cmu_peris: clock-controller@10040000 { |
| 187 | compatible = "samsung,exynos5433-cmu-peris"; |
| 188 | reg = <0x10040000 0x0b20>; |
| 189 | #clock-cells = <1>; |
| 190 | }; |
| 191 | |
| 192 | cmu_fsys: clock-controller@156e0000 { |
| 193 | compatible = "samsung,exynos5433-cmu-fsys"; |
| 194 | reg = <0x156e0000 0x0b04>; |
| 195 | #clock-cells = <1>; |
| 196 | |
| 197 | clock-names = "oscclk", |
| 198 | "sclk_ufs_mphy", |
| 199 | "div_aclk_fsys_200", |
| 200 | "sclk_pcie_100_fsys", |
| 201 | "sclk_ufsunipro_fsys", |
| 202 | "sclk_mmc2_fsys", |
| 203 | "sclk_mmc1_fsys", |
| 204 | "sclk_mmc0_fsys", |
| 205 | "sclk_usbhost30_fsys", |
| 206 | "sclk_usbdrd30_fsys"; |
| 207 | clocks = <&xxti>, |
| 208 | <&cmu_cpif CLK_SCLK_UFS_MPHY>, |
| 209 | <&cmu_top CLK_DIV_ACLK_FSYS_200>, |
| 210 | <&cmu_top CLK_SCLK_PCIE_100_FSYS>, |
| 211 | <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, |
| 212 | <&cmu_top CLK_SCLK_MMC2_FSYS>, |
| 213 | <&cmu_top CLK_SCLK_MMC1_FSYS>, |
| 214 | <&cmu_top CLK_SCLK_MMC0_FSYS>, |
| 215 | <&cmu_top CLK_SCLK_USBHOST30_FSYS>, |
| 216 | <&cmu_top CLK_SCLK_USBDRD30_FSYS>; |
| 217 | }; |
| 218 | |
| 219 | cmu_g2d: clock-controller@12460000 { |
| 220 | compatible = "samsung,exynos5433-cmu-g2d"; |
| 221 | reg = <0x12460000 0x0b08>; |
| 222 | #clock-cells = <1>; |
| 223 | |
| 224 | clock-names = "oscclk", |
| 225 | "aclk_g2d_266", |
| 226 | "aclk_g2d_400"; |
| 227 | clocks = <&xxti>, |
| 228 | <&cmu_top CLK_ACLK_G2D_266>, |
| 229 | <&cmu_top CLK_ACLK_G2D_400>; |
| 230 | }; |
| 231 | |
| 232 | cmu_disp: clock-controller@13b90000 { |
| 233 | compatible = "samsung,exynos5433-cmu-disp"; |
| 234 | reg = <0x13b90000 0x0c04>; |
| 235 | #clock-cells = <1>; |
| 236 | |
| 237 | clock-names = "oscclk", |
| 238 | "sclk_dsim1_disp", |
| 239 | "sclk_dsim0_disp", |
| 240 | "sclk_dsd_disp", |
| 241 | "sclk_decon_tv_eclk_disp", |
| 242 | "sclk_decon_vclk_disp", |
| 243 | "sclk_decon_eclk_disp", |
| 244 | "sclk_decon_tv_vclk_disp", |
| 245 | "aclk_disp_333"; |
| 246 | clocks = <&xxti>, |
| 247 | <&cmu_mif CLK_SCLK_DSIM1_DISP>, |
| 248 | <&cmu_mif CLK_SCLK_DSIM0_DISP>, |
| 249 | <&cmu_mif CLK_SCLK_DSD_DISP>, |
| 250 | <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, |
| 251 | <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>, |
| 252 | <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, |
| 253 | <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, |
| 254 | <&cmu_mif CLK_ACLK_DISP_333>; |
| 255 | }; |
| 256 | |
| 257 | cmu_aud: clock-controller@114c0000 { |
| 258 | compatible = "samsung,exynos5433-cmu-aud"; |
| 259 | reg = <0x114c0000 0x0b04>; |
| 260 | #clock-cells = <1>; |
| 261 | }; |
| 262 | |
| 263 | cmu_bus0: clock-controller@13600000 { |
| 264 | compatible = "samsung,exynos5433-cmu-bus0"; |
| 265 | reg = <0x13600000 0x0b04>; |
| 266 | #clock-cells = <1>; |
| 267 | |
| 268 | clock-names = "aclk_bus0_400"; |
| 269 | clocks = <&cmu_top CLK_ACLK_BUS0_400>; |
| 270 | }; |
| 271 | |
| 272 | cmu_bus1: clock-controller@14800000 { |
| 273 | compatible = "samsung,exynos5433-cmu-bus1"; |
| 274 | reg = <0x14800000 0x0b04>; |
| 275 | #clock-cells = <1>; |
| 276 | |
| 277 | clock-names = "aclk_bus1_400"; |
| 278 | clocks = <&cmu_top CLK_ACLK_BUS1_400>; |
| 279 | }; |
| 280 | |
| 281 | cmu_bus2: clock-controller@13400000 { |
| 282 | compatible = "samsung,exynos5433-cmu-bus2"; |
| 283 | reg = <0x13400000 0x0b04>; |
| 284 | #clock-cells = <1>; |
| 285 | |
| 286 | clock-names = "oscclk", "aclk_bus2_400"; |
| 287 | clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>; |
| 288 | }; |
| 289 | |
| 290 | cmu_g3d: clock-controller@14aa0000 { |
| 291 | compatible = "samsung,exynos5433-cmu-g3d"; |
| 292 | reg = <0x14aa0000 0x1000>; |
| 293 | #clock-cells = <1>; |
| 294 | |
| 295 | clock-names = "oscclk", "aclk_g3d_400"; |
| 296 | clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; |
| 297 | }; |
| 298 | |
| 299 | cmu_gscl: clock-controller@13cf0000 { |
| 300 | compatible = "samsung,exynos5433-cmu-gscl"; |
| 301 | reg = <0x13cf0000 0x0b10>; |
| 302 | #clock-cells = <1>; |
| 303 | |
| 304 | clock-names = "oscclk", |
| 305 | "aclk_gscl_111", |
| 306 | "aclk_gscl_333"; |
| 307 | clocks = <&xxti>, |
| 308 | <&cmu_top CLK_ACLK_GSCL_111>, |
| 309 | <&cmu_top CLK_ACLK_GSCL_333>; |
| 310 | }; |
| 311 | |
Chanwoo Choi | df40a13 | 2015-02-03 09:13:49 +0900 | [diff] [blame] | 312 | cmu_apollo: clock-controller@11900000 { |
| 313 | compatible = "samsung,exynos5433-cmu-apollo"; |
| 314 | reg = <0x11900000 0x1088>; |
| 315 | #clock-cells = <1>; |
| 316 | |
| 317 | clock-names = "oscclk", "sclk_bus_pll_apollo"; |
| 318 | clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>; |
| 319 | }; |
| 320 | |
Chanwoo Choi | 6c5d76d | 2015-02-03 09:13:50 +0900 | [diff] [blame] | 321 | cmu_atlas: clock-controller@11800000 { |
| 322 | compatible = "samsung,exynos5433-cmu-atlas"; |
| 323 | reg = <0x11800000 0x1088>; |
| 324 | #clock-cells = <1>; |
| 325 | |
| 326 | clock-names = "oscclk", "sclk_bus_pll_atlas"; |
| 327 | clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>; |
| 328 | }; |
| 329 | |
Chanwoo Choi | b274bbf | 2015-02-03 09:13:51 +0900 | [diff] [blame^] | 330 | cmu_mscl: clock-controller@105d0000 { |
| 331 | compatible = "samsung,exynos5433-cmu-mscl"; |
| 332 | reg = <0x105d0000 0x0b10>; |
| 333 | #clock-cells = <1>; |
| 334 | |
| 335 | clock-names = "oscclk", |
| 336 | "sclk_jpeg_mscl", |
| 337 | "aclk_mscl_400"; |
| 338 | clocks = <&xxti>, |
| 339 | <&cmu_top CLK_SCLK_JPEG_MSCL>, |
| 340 | <&cmu_top CLK_ACLK_MSCL_400>; |
| 341 | }; |
| 342 | |
Chanwoo Choi | 1a21dfe | 2015-02-03 08:47:11 +0900 | [diff] [blame] | 343 | Example 3: UART controller node that consumes the clock generated by the clock |
| 344 | controller. |
| 345 | |
| 346 | serial_0: serial@14C10000 { |
| 347 | compatible = "samsung,exynos5433-uart"; |
| 348 | reg = <0x14C10000 0x100>; |
| 349 | interrupts = <0 421 0>; |
| 350 | clocks = <&cmu_peric CLK_PCLK_UART0>, |
| 351 | <&cmu_peric CLK_SCLK_UART0>; |
| 352 | clock-names = "uart", "clk_uart_baud0"; |
| 353 | pinctrl-names = "default"; |
| 354 | pinctrl-0 = <&uart0_bus>; |
| 355 | status = "disabled"; |
| 356 | }; |