Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 1 | #ifndef MDP4_XML |
| 2 | #define MDP4_XML |
| 3 | |
| 4 | /* Autogenerated file, DO NOT EDIT manually! |
| 5 | |
| 6 | This file was generated by the rules-ng-ng headergen tool in this git repository: |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 7 | http://github.com/freedreno/envytools/ |
| 8 | git clone https://github.com/freedreno/envytools.git |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 9 | |
| 10 | The rules-ng-ng source files this header was generated from are: |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 11 | - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 12 | - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) |
Rob Clark | f9a1ca5 | 2014-08-01 08:26:56 -0400 | [diff] [blame] | 13 | - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20457 bytes, from 2014-08-01 12:22:48) |
| 14 | - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2014-07-17 15:34:33) |
| 15 | - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2014-07-17 15:34:33) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 16 | - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) |
| 17 | - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) |
Rob Clark | f9a1ca5 | 2014-08-01 08:26:56 -0400 | [diff] [blame] | 18 | - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-08-01 12:23:53) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 19 | - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) |
Rob Clark | f9a1ca5 | 2014-08-01 08:26:56 -0400 | [diff] [blame] | 20 | - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 23613 bytes, from 2014-07-17 15:33:30) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 21 | |
Rob Clark | f9a1ca5 | 2014-08-01 08:26:56 -0400 | [diff] [blame] | 22 | Copyright (C) 2013-2014 by the following authors: |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 23 | - Rob Clark <robdclark@gmail.com> (robclark) |
| 24 | |
| 25 | Permission is hereby granted, free of charge, to any person obtaining |
| 26 | a copy of this software and associated documentation files (the |
| 27 | "Software"), to deal in the Software without restriction, including |
| 28 | without limitation the rights to use, copy, modify, merge, publish, |
| 29 | distribute, sublicense, and/or sell copies of the Software, and to |
| 30 | permit persons to whom the Software is furnished to do so, subject to |
| 31 | the following conditions: |
| 32 | |
| 33 | The above copyright notice and this permission notice (including the |
| 34 | next paragraph) shall be included in all copies or substantial |
| 35 | portions of the Software. |
| 36 | |
| 37 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 38 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 39 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 40 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
| 41 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
| 42 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
| 43 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 44 | */ |
| 45 | |
| 46 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 47 | enum mdp4_pipe { |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 48 | VG1 = 0, |
| 49 | VG2 = 1, |
| 50 | RGB1 = 2, |
| 51 | RGB2 = 3, |
| 52 | RGB3 = 4, |
| 53 | VG3 = 5, |
| 54 | VG4 = 6, |
| 55 | }; |
| 56 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 57 | enum mdp4_mixer { |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 58 | MIXER0 = 0, |
| 59 | MIXER1 = 1, |
| 60 | MIXER2 = 2, |
| 61 | }; |
| 62 | |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 63 | enum mdp4_intf { |
| 64 | INTF_LCDC_DTV = 0, |
| 65 | INTF_DSI_VIDEO = 1, |
| 66 | INTF_DSI_CMD = 2, |
| 67 | INTF_EBI2_TV = 3, |
| 68 | }; |
| 69 | |
| 70 | enum mdp4_cursor_format { |
| 71 | CURSOR_ARGB = 1, |
| 72 | CURSOR_XRGB = 2, |
| 73 | }; |
| 74 | |
| 75 | enum mdp4_dma { |
| 76 | DMA_P = 0, |
| 77 | DMA_S = 1, |
| 78 | DMA_E = 2, |
| 79 | }; |
| 80 | |
| 81 | #define MDP4_IRQ_OVERLAY0_DONE 0x00000001 |
| 82 | #define MDP4_IRQ_OVERLAY1_DONE 0x00000002 |
| 83 | #define MDP4_IRQ_DMA_S_DONE 0x00000004 |
| 84 | #define MDP4_IRQ_DMA_E_DONE 0x00000008 |
| 85 | #define MDP4_IRQ_DMA_P_DONE 0x00000010 |
| 86 | #define MDP4_IRQ_VG1_HISTOGRAM 0x00000020 |
| 87 | #define MDP4_IRQ_VG2_HISTOGRAM 0x00000040 |
| 88 | #define MDP4_IRQ_PRIMARY_VSYNC 0x00000080 |
| 89 | #define MDP4_IRQ_PRIMARY_INTF_UDERRUN 0x00000100 |
| 90 | #define MDP4_IRQ_EXTERNAL_VSYNC 0x00000200 |
| 91 | #define MDP4_IRQ_EXTERNAL_INTF_UDERRUN 0x00000400 |
| 92 | #define MDP4_IRQ_PRIMARY_RDPTR 0x00000800 |
| 93 | #define MDP4_IRQ_DMA_P_HISTOGRAM 0x00020000 |
| 94 | #define MDP4_IRQ_DMA_S_HISTOGRAM 0x04000000 |
| 95 | #define MDP4_IRQ_OVERLAY2_DONE 0x40000000 |
| 96 | #define REG_MDP4_VERSION 0x00000000 |
| 97 | #define MDP4_VERSION_MINOR__MASK 0x00ff0000 |
| 98 | #define MDP4_VERSION_MINOR__SHIFT 16 |
| 99 | static inline uint32_t MDP4_VERSION_MINOR(uint32_t val) |
| 100 | { |
| 101 | return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK; |
| 102 | } |
| 103 | #define MDP4_VERSION_MAJOR__MASK 0xff000000 |
| 104 | #define MDP4_VERSION_MAJOR__SHIFT 24 |
| 105 | static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val) |
| 106 | { |
| 107 | return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK; |
| 108 | } |
| 109 | |
| 110 | #define REG_MDP4_OVLP0_KICK 0x00000004 |
| 111 | |
| 112 | #define REG_MDP4_OVLP1_KICK 0x00000008 |
| 113 | |
| 114 | #define REG_MDP4_OVLP2_KICK 0x000000d0 |
| 115 | |
| 116 | #define REG_MDP4_DMA_P_KICK 0x0000000c |
| 117 | |
| 118 | #define REG_MDP4_DMA_S_KICK 0x00000010 |
| 119 | |
| 120 | #define REG_MDP4_DMA_E_KICK 0x00000014 |
| 121 | |
| 122 | #define REG_MDP4_DISP_STATUS 0x00000018 |
| 123 | |
| 124 | #define REG_MDP4_DISP_INTF_SEL 0x00000038 |
| 125 | #define MDP4_DISP_INTF_SEL_PRIM__MASK 0x00000003 |
| 126 | #define MDP4_DISP_INTF_SEL_PRIM__SHIFT 0 |
| 127 | static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val) |
| 128 | { |
| 129 | return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK; |
| 130 | } |
| 131 | #define MDP4_DISP_INTF_SEL_SEC__MASK 0x0000000c |
| 132 | #define MDP4_DISP_INTF_SEL_SEC__SHIFT 2 |
| 133 | static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val) |
| 134 | { |
| 135 | return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK; |
| 136 | } |
| 137 | #define MDP4_DISP_INTF_SEL_EXT__MASK 0x00000030 |
| 138 | #define MDP4_DISP_INTF_SEL_EXT__SHIFT 4 |
| 139 | static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val) |
| 140 | { |
| 141 | return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIFT) & MDP4_DISP_INTF_SEL_EXT__MASK; |
| 142 | } |
| 143 | #define MDP4_DISP_INTF_SEL_DSI_VIDEO 0x00000040 |
| 144 | #define MDP4_DISP_INTF_SEL_DSI_CMD 0x00000080 |
| 145 | |
| 146 | #define REG_MDP4_RESET_STATUS 0x0000003c |
| 147 | |
| 148 | #define REG_MDP4_READ_CNFG 0x0000004c |
| 149 | |
| 150 | #define REG_MDP4_INTR_ENABLE 0x00000050 |
| 151 | |
| 152 | #define REG_MDP4_INTR_STATUS 0x00000054 |
| 153 | |
| 154 | #define REG_MDP4_INTR_CLEAR 0x00000058 |
| 155 | |
| 156 | #define REG_MDP4_EBI2_LCD0 0x00000060 |
| 157 | |
| 158 | #define REG_MDP4_EBI2_LCD1 0x00000064 |
| 159 | |
| 160 | #define REG_MDP4_PORTMAP_MODE 0x00000070 |
| 161 | |
| 162 | #define REG_MDP4_CS_CONTROLLER0 0x000000c0 |
| 163 | |
| 164 | #define REG_MDP4_CS_CONTROLLER1 0x000000c4 |
| 165 | |
| 166 | #define REG_MDP4_LAYERMIXER2_IN_CFG 0x000100f0 |
| 167 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK 0x00000007 |
| 168 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT 0 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 169 | static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 170 | { |
| 171 | return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK; |
| 172 | } |
| 173 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1 0x00000008 |
| 174 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK 0x00000070 |
| 175 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT 4 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 176 | static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 177 | { |
| 178 | return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK; |
| 179 | } |
| 180 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1 0x00000080 |
| 181 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK 0x00000700 |
| 182 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT 8 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 183 | static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 184 | { |
| 185 | return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK; |
| 186 | } |
| 187 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1 0x00000800 |
| 188 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK 0x00007000 |
| 189 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT 12 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 190 | static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 191 | { |
| 192 | return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK; |
| 193 | } |
| 194 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1 0x00008000 |
| 195 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK 0x00070000 |
| 196 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT 16 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 197 | static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 198 | { |
| 199 | return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK; |
| 200 | } |
| 201 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1 0x00080000 |
| 202 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK 0x00700000 |
| 203 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT 20 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 204 | static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 205 | { |
| 206 | return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK; |
| 207 | } |
| 208 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1 0x00800000 |
| 209 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK 0x07000000 |
| 210 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT 24 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 211 | static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 212 | { |
| 213 | return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK; |
| 214 | } |
| 215 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1 0x08000000 |
| 216 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK 0x70000000 |
| 217 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT 28 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 218 | static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 219 | { |
| 220 | return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK; |
| 221 | } |
| 222 | #define MDP4_LAYERMIXER2_IN_CFG_PIPE7_MIXER1 0x80000000 |
| 223 | |
| 224 | #define REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD 0x000100fc |
| 225 | |
| 226 | #define REG_MDP4_LAYERMIXER_IN_CFG 0x00010100 |
| 227 | #define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK 0x00000007 |
| 228 | #define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT 0 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 229 | static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 230 | { |
| 231 | return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK; |
| 232 | } |
| 233 | #define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1 0x00000008 |
| 234 | #define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK 0x00000070 |
| 235 | #define MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT 4 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 236 | static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 237 | { |
| 238 | return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK; |
| 239 | } |
| 240 | #define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1 0x00000080 |
| 241 | #define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK 0x00000700 |
| 242 | #define MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT 8 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 243 | static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 244 | { |
| 245 | return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK; |
| 246 | } |
| 247 | #define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1 0x00000800 |
| 248 | #define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK 0x00007000 |
| 249 | #define MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT 12 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 250 | static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 251 | { |
| 252 | return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK; |
| 253 | } |
| 254 | #define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1 0x00008000 |
| 255 | #define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK 0x00070000 |
| 256 | #define MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT 16 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 257 | static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 258 | { |
| 259 | return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK; |
| 260 | } |
| 261 | #define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1 0x00080000 |
| 262 | #define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK 0x00700000 |
| 263 | #define MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT 20 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 264 | static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 265 | { |
| 266 | return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK; |
| 267 | } |
| 268 | #define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1 0x00800000 |
| 269 | #define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK 0x07000000 |
| 270 | #define MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT 24 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 271 | static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 272 | { |
| 273 | return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK; |
| 274 | } |
| 275 | #define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1 0x08000000 |
| 276 | #define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK 0x70000000 |
| 277 | #define MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT 28 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 278 | static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 279 | { |
| 280 | return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK; |
| 281 | } |
| 282 | #define MDP4_LAYERMIXER_IN_CFG_PIPE7_MIXER1 0x80000000 |
| 283 | |
| 284 | #define REG_MDP4_VG2_SRC_FORMAT 0x00030050 |
| 285 | |
| 286 | #define REG_MDP4_VG2_CONST_COLOR 0x00031008 |
| 287 | |
| 288 | #define REG_MDP4_OVERLAY_FLUSH 0x00018000 |
| 289 | #define MDP4_OVERLAY_FLUSH_OVLP0 0x00000001 |
| 290 | #define MDP4_OVERLAY_FLUSH_OVLP1 0x00000002 |
| 291 | #define MDP4_OVERLAY_FLUSH_VG1 0x00000004 |
| 292 | #define MDP4_OVERLAY_FLUSH_VG2 0x00000008 |
| 293 | #define MDP4_OVERLAY_FLUSH_RGB1 0x00000010 |
| 294 | #define MDP4_OVERLAY_FLUSH_RGB2 0x00000020 |
| 295 | |
| 296 | static inline uint32_t __offset_OVLP(uint32_t idx) |
| 297 | { |
| 298 | switch (idx) { |
| 299 | case 0: return 0x00010000; |
| 300 | case 1: return 0x00018000; |
| 301 | case 2: return 0x00088000; |
| 302 | default: return INVALID_IDX(idx); |
| 303 | } |
| 304 | } |
| 305 | static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); } |
| 306 | |
| 307 | static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); } |
| 308 | |
| 309 | static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); } |
| 310 | #define MDP4_OVLP_SIZE_HEIGHT__MASK 0xffff0000 |
| 311 | #define MDP4_OVLP_SIZE_HEIGHT__SHIFT 16 |
| 312 | static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val) |
| 313 | { |
| 314 | return ((val) << MDP4_OVLP_SIZE_HEIGHT__SHIFT) & MDP4_OVLP_SIZE_HEIGHT__MASK; |
| 315 | } |
| 316 | #define MDP4_OVLP_SIZE_WIDTH__MASK 0x0000ffff |
| 317 | #define MDP4_OVLP_SIZE_WIDTH__SHIFT 0 |
| 318 | static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val) |
| 319 | { |
| 320 | return ((val) << MDP4_OVLP_SIZE_WIDTH__SHIFT) & MDP4_OVLP_SIZE_WIDTH__MASK; |
| 321 | } |
| 322 | |
| 323 | static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); } |
| 324 | |
| 325 | static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); } |
| 326 | |
| 327 | static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); } |
| 328 | |
| 329 | static inline uint32_t __offset_STAGE(uint32_t idx) |
| 330 | { |
| 331 | switch (idx) { |
| 332 | case 0: return 0x00000104; |
| 333 | case 1: return 0x00000124; |
| 334 | case 2: return 0x00000144; |
| 335 | case 3: return 0x00000160; |
| 336 | default: return INVALID_IDX(idx); |
| 337 | } |
| 338 | } |
| 339 | static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } |
| 340 | |
| 341 | static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } |
| 342 | #define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK 0x00000003 |
| 343 | #define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT 0 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 344 | static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 345 | { |
| 346 | return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK; |
| 347 | } |
| 348 | #define MDP4_OVLP_STAGE_OP_FG_INV_ALPHA 0x00000004 |
| 349 | #define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA 0x00000008 |
| 350 | #define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK 0x00000030 |
| 351 | #define MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT 4 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 352 | static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 353 | { |
| 354 | return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK; |
| 355 | } |
| 356 | #define MDP4_OVLP_STAGE_OP_BG_INV_ALPHA 0x00000040 |
| 357 | #define MDP4_OVLP_STAGE_OP_BG_MOD_ALPHA 0x00000080 |
| 358 | #define MDP4_OVLP_STAGE_OP_FG_TRANSP 0x00000100 |
| 359 | #define MDP4_OVLP_STAGE_OP_BG_TRANSP 0x00000200 |
| 360 | |
| 361 | static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); } |
| 362 | |
| 363 | static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); } |
| 364 | |
| 365 | static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); } |
| 366 | |
| 367 | static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offset_STAGE(i1); } |
| 368 | |
| 369 | static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offset_STAGE(i1); } |
| 370 | |
| 371 | static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offset_STAGE(i1); } |
| 372 | |
| 373 | static inline uint32_t __offset_STAGE_CO3(uint32_t idx) |
| 374 | { |
| 375 | switch (idx) { |
| 376 | case 0: return 0x00001004; |
| 377 | case 1: return 0x00001404; |
| 378 | case 2: return 0x00001804; |
| 379 | case 3: return 0x00001b84; |
| 380 | default: return INVALID_IDX(idx); |
| 381 | } |
| 382 | } |
| 383 | static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); } |
| 384 | |
| 385 | static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); } |
| 386 | #define MDP4_OVLP_STAGE_CO3_SEL_FG_ALPHA 0x00000001 |
| 387 | |
| 388 | static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i0); } |
| 389 | |
| 390 | static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i0); } |
| 391 | |
| 392 | static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(i0); } |
| 393 | |
| 394 | static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(i0); } |
| 395 | |
| 396 | static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0); } |
| 397 | |
| 398 | static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); } |
| 399 | |
| 400 | |
| 401 | static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; } |
| 402 | |
| 403 | static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; } |
| 404 | |
| 405 | static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; } |
| 406 | |
| 407 | static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; } |
| 408 | |
| 409 | static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; } |
| 410 | |
| 411 | static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; } |
| 412 | |
| 413 | static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; } |
| 414 | |
| 415 | static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; } |
| 416 | |
| 417 | static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; } |
| 418 | |
| 419 | static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; } |
| 420 | |
| 421 | #define REG_MDP4_DMA_P_OP_MODE 0x00090070 |
| 422 | |
| 423 | static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; } |
| 424 | |
| 425 | static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } |
| 426 | |
| 427 | static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } |
| 428 | |
| 429 | #define REG_MDP4_DMA_S_OP_MODE 0x000a0028 |
| 430 | |
| 431 | static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; } |
| 432 | |
| 433 | static inline uint32_t __offset_DMA(enum mdp4_dma idx) |
| 434 | { |
| 435 | switch (idx) { |
| 436 | case DMA_P: return 0x00090000; |
| 437 | case DMA_S: return 0x000a0000; |
| 438 | case DMA_E: return 0x000b0000; |
| 439 | default: return INVALID_IDX(idx); |
| 440 | } |
| 441 | } |
| 442 | static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } |
| 443 | |
| 444 | static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } |
| 445 | #define MDP4_DMA_CONFIG_G_BPC__MASK 0x00000003 |
| 446 | #define MDP4_DMA_CONFIG_G_BPC__SHIFT 0 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 447 | static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 448 | { |
| 449 | return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK; |
| 450 | } |
| 451 | #define MDP4_DMA_CONFIG_B_BPC__MASK 0x0000000c |
| 452 | #define MDP4_DMA_CONFIG_B_BPC__SHIFT 2 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 453 | static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 454 | { |
| 455 | return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK; |
| 456 | } |
| 457 | #define MDP4_DMA_CONFIG_R_BPC__MASK 0x00000030 |
| 458 | #define MDP4_DMA_CONFIG_R_BPC__SHIFT 4 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 459 | static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 460 | { |
| 461 | return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK; |
| 462 | } |
| 463 | #define MDP4_DMA_CONFIG_PACK_ALIGN_MSB 0x00000080 |
| 464 | #define MDP4_DMA_CONFIG_PACK__MASK 0x0000ff00 |
| 465 | #define MDP4_DMA_CONFIG_PACK__SHIFT 8 |
| 466 | static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val) |
| 467 | { |
| 468 | return ((val) << MDP4_DMA_CONFIG_PACK__SHIFT) & MDP4_DMA_CONFIG_PACK__MASK; |
| 469 | } |
| 470 | #define MDP4_DMA_CONFIG_DEFLKR_EN 0x01000000 |
| 471 | #define MDP4_DMA_CONFIG_DITHER_EN 0x01000000 |
| 472 | |
| 473 | static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i0); } |
| 474 | #define MDP4_DMA_SRC_SIZE_HEIGHT__MASK 0xffff0000 |
| 475 | #define MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT 16 |
| 476 | static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val) |
| 477 | { |
| 478 | return ((val) << MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT) & MDP4_DMA_SRC_SIZE_HEIGHT__MASK; |
| 479 | } |
| 480 | #define MDP4_DMA_SRC_SIZE_WIDTH__MASK 0x0000ffff |
| 481 | #define MDP4_DMA_SRC_SIZE_WIDTH__SHIFT 0 |
| 482 | static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val) |
| 483 | { |
| 484 | return ((val) << MDP4_DMA_SRC_SIZE_WIDTH__SHIFT) & MDP4_DMA_SRC_SIZE_WIDTH__MASK; |
| 485 | } |
| 486 | |
| 487 | static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i0); } |
| 488 | |
| 489 | static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA(i0); } |
| 490 | |
| 491 | static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i0); } |
| 492 | #define MDP4_DMA_DST_SIZE_HEIGHT__MASK 0xffff0000 |
| 493 | #define MDP4_DMA_DST_SIZE_HEIGHT__SHIFT 16 |
| 494 | static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val) |
| 495 | { |
| 496 | return ((val) << MDP4_DMA_DST_SIZE_HEIGHT__SHIFT) & MDP4_DMA_DST_SIZE_HEIGHT__MASK; |
| 497 | } |
| 498 | #define MDP4_DMA_DST_SIZE_WIDTH__MASK 0x0000ffff |
| 499 | #define MDP4_DMA_DST_SIZE_WIDTH__SHIFT 0 |
| 500 | static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val) |
| 501 | { |
| 502 | return ((val) << MDP4_DMA_DST_SIZE_WIDTH__SHIFT) & MDP4_DMA_DST_SIZE_WIDTH__MASK; |
| 503 | } |
| 504 | |
| 505 | static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DMA(i0); } |
| 506 | #define MDP4_DMA_CURSOR_SIZE_WIDTH__MASK 0x0000007f |
| 507 | #define MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT 0 |
| 508 | static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val) |
| 509 | { |
| 510 | return ((val) << MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT) & MDP4_DMA_CURSOR_SIZE_WIDTH__MASK; |
| 511 | } |
| 512 | #define MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK 0x007f0000 |
| 513 | #define MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT 16 |
| 514 | static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val) |
| 515 | { |
| 516 | return ((val) << MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT) & MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK; |
| 517 | } |
| 518 | |
| 519 | static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DMA(i0); } |
| 520 | |
| 521 | static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA(i0); } |
| 522 | #define MDP4_DMA_CURSOR_POS_X__MASK 0x0000ffff |
| 523 | #define MDP4_DMA_CURSOR_POS_X__SHIFT 0 |
| 524 | static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val) |
| 525 | { |
| 526 | return ((val) << MDP4_DMA_CURSOR_POS_X__SHIFT) & MDP4_DMA_CURSOR_POS_X__MASK; |
| 527 | } |
| 528 | #define MDP4_DMA_CURSOR_POS_Y__MASK 0xffff0000 |
| 529 | #define MDP4_DMA_CURSOR_POS_Y__SHIFT 16 |
| 530 | static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val) |
| 531 | { |
| 532 | return ((val) << MDP4_DMA_CURSOR_POS_Y__SHIFT) & MDP4_DMA_CURSOR_POS_Y__MASK; |
| 533 | } |
| 534 | |
| 535 | static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __offset_DMA(i0); } |
| 536 | #define MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN 0x00000001 |
| 537 | #define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK 0x00000006 |
| 538 | #define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT 1 |
| 539 | static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val) |
| 540 | { |
| 541 | return ((val) << MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT) & MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK; |
| 542 | } |
| 543 | #define MDP4_DMA_CURSOR_BLEND_CONFIG_TRANSP_EN 0x00000008 |
| 544 | |
| 545 | static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __offset_DMA(i0); } |
| 546 | |
| 547 | static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offset_DMA(i0); } |
| 548 | |
| 549 | static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offset_DMA(i0); } |
| 550 | |
| 551 | static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_DMA(i0); } |
| 552 | |
| 553 | static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); } |
| 554 | |
| 555 | |
| 556 | static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; } |
| 557 | |
| 558 | static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; } |
| 559 | |
| 560 | static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; } |
| 561 | |
| 562 | static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; } |
| 563 | |
| 564 | static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; } |
| 565 | |
| 566 | static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; } |
| 567 | |
| 568 | static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; } |
| 569 | |
| 570 | static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; } |
| 571 | |
| 572 | static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; } |
| 573 | |
| 574 | static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; } |
| 575 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 576 | static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 577 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 578 | static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 579 | #define MDP4_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000 |
| 580 | #define MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT 16 |
| 581 | static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val) |
| 582 | { |
| 583 | return ((val) << MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SRC_SIZE_HEIGHT__MASK; |
| 584 | } |
| 585 | #define MDP4_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff |
| 586 | #define MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT 0 |
| 587 | static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val) |
| 588 | { |
| 589 | return ((val) << MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SRC_SIZE_WIDTH__MASK; |
| 590 | } |
| 591 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 592 | static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 593 | #define MDP4_PIPE_SRC_XY_Y__MASK 0xffff0000 |
| 594 | #define MDP4_PIPE_SRC_XY_Y__SHIFT 16 |
| 595 | static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val) |
| 596 | { |
| 597 | return ((val) << MDP4_PIPE_SRC_XY_Y__SHIFT) & MDP4_PIPE_SRC_XY_Y__MASK; |
| 598 | } |
| 599 | #define MDP4_PIPE_SRC_XY_X__MASK 0x0000ffff |
| 600 | #define MDP4_PIPE_SRC_XY_X__SHIFT 0 |
| 601 | static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val) |
| 602 | { |
| 603 | return ((val) << MDP4_PIPE_SRC_XY_X__SHIFT) & MDP4_PIPE_SRC_XY_X__MASK; |
| 604 | } |
| 605 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 606 | static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 607 | #define MDP4_PIPE_DST_SIZE_HEIGHT__MASK 0xffff0000 |
| 608 | #define MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT 16 |
| 609 | static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val) |
| 610 | { |
| 611 | return ((val) << MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_DST_SIZE_HEIGHT__MASK; |
| 612 | } |
| 613 | #define MDP4_PIPE_DST_SIZE_WIDTH__MASK 0x0000ffff |
| 614 | #define MDP4_PIPE_DST_SIZE_WIDTH__SHIFT 0 |
| 615 | static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val) |
| 616 | { |
| 617 | return ((val) << MDP4_PIPE_DST_SIZE_WIDTH__SHIFT) & MDP4_PIPE_DST_SIZE_WIDTH__MASK; |
| 618 | } |
| 619 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 620 | static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 621 | #define MDP4_PIPE_DST_XY_Y__MASK 0xffff0000 |
| 622 | #define MDP4_PIPE_DST_XY_Y__SHIFT 16 |
| 623 | static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val) |
| 624 | { |
| 625 | return ((val) << MDP4_PIPE_DST_XY_Y__SHIFT) & MDP4_PIPE_DST_XY_Y__MASK; |
| 626 | } |
| 627 | #define MDP4_PIPE_DST_XY_X__MASK 0x0000ffff |
| 628 | #define MDP4_PIPE_DST_XY_X__SHIFT 0 |
| 629 | static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val) |
| 630 | { |
| 631 | return ((val) << MDP4_PIPE_DST_XY_X__SHIFT) & MDP4_PIPE_DST_XY_X__MASK; |
| 632 | } |
| 633 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 634 | static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 635 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 636 | static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 637 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 638 | static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 639 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 640 | static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*i0; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 641 | #define MDP4_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff |
| 642 | #define MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT 0 |
| 643 | static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val) |
| 644 | { |
| 645 | return ((val) << MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P0__MASK; |
| 646 | } |
| 647 | #define MDP4_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000 |
| 648 | #define MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT 16 |
| 649 | static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val) |
| 650 | { |
| 651 | return ((val) << MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P1__MASK; |
| 652 | } |
| 653 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 654 | static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*i0; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 655 | #define MDP4_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff |
| 656 | #define MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT 0 |
| 657 | static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val) |
| 658 | { |
| 659 | return ((val) << MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P2__MASK; |
| 660 | } |
| 661 | #define MDP4_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000 |
| 662 | #define MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT 16 |
| 663 | static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val) |
| 664 | { |
| 665 | return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK; |
| 666 | } |
| 667 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 668 | static inline uint32_t REG_MDP4_PIPE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 669 | #define MDP4_PIPE_FRAME_SIZE_HEIGHT__MASK 0xffff0000 |
| 670 | #define MDP4_PIPE_FRAME_SIZE_HEIGHT__SHIFT 16 |
| 671 | static inline uint32_t MDP4_PIPE_FRAME_SIZE_HEIGHT(uint32_t val) |
| 672 | { |
| 673 | return ((val) << MDP4_PIPE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_FRAME_SIZE_HEIGHT__MASK; |
| 674 | } |
| 675 | #define MDP4_PIPE_FRAME_SIZE_WIDTH__MASK 0x0000ffff |
| 676 | #define MDP4_PIPE_FRAME_SIZE_WIDTH__SHIFT 0 |
| 677 | static inline uint32_t MDP4_PIPE_FRAME_SIZE_WIDTH(uint32_t val) |
| 678 | { |
| 679 | return ((val) << MDP4_PIPE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_FRAME_SIZE_WIDTH__MASK; |
| 680 | } |
| 681 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 682 | static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 683 | #define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003 |
| 684 | #define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT 0 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 685 | static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 686 | { |
| 687 | return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK; |
| 688 | } |
| 689 | #define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c |
| 690 | #define MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT 2 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 691 | static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 692 | { |
| 693 | return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK; |
| 694 | } |
| 695 | #define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030 |
| 696 | #define MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT 4 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 697 | static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 698 | { |
| 699 | return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK; |
| 700 | } |
| 701 | #define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0 |
| 702 | #define MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT 6 |
Rob Clark | facb4f4 | 2013-11-30 12:45:48 -0500 | [diff] [blame] | 703 | static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val) |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 704 | { |
| 705 | return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK; |
| 706 | } |
| 707 | #define MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100 |
| 708 | #define MDP4_PIPE_SRC_FORMAT_CPP__MASK 0x00000600 |
| 709 | #define MDP4_PIPE_SRC_FORMAT_CPP__SHIFT 9 |
| 710 | static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val) |
| 711 | { |
| 712 | return ((val) << MDP4_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CPP__MASK; |
| 713 | } |
| 714 | #define MDP4_PIPE_SRC_FORMAT_ROTATED_90 0x00001000 |
| 715 | #define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00006000 |
| 716 | #define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 13 |
| 717 | static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val) |
| 718 | { |
| 719 | return ((val) << MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK; |
| 720 | } |
| 721 | #define MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000 |
| 722 | #define MDP4_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000 |
| 723 | #define MDP4_PIPE_SRC_FORMAT_SOLID_FILL 0x00400000 |
| 724 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 725 | static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 726 | #define MDP4_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff |
| 727 | #define MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT 0 |
| 728 | static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val) |
| 729 | { |
| 730 | return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM0__MASK; |
| 731 | } |
| 732 | #define MDP4_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00 |
| 733 | #define MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT 8 |
| 734 | static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val) |
| 735 | { |
| 736 | return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM1__MASK; |
| 737 | } |
| 738 | #define MDP4_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000 |
| 739 | #define MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT 16 |
| 740 | static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val) |
| 741 | { |
| 742 | return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM2__MASK; |
| 743 | } |
| 744 | #define MDP4_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000 |
| 745 | #define MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT 24 |
| 746 | static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val) |
| 747 | { |
| 748 | return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM3__MASK; |
| 749 | } |
| 750 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 751 | static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 752 | #define MDP4_PIPE_OP_MODE_SCALEX_EN 0x00000001 |
| 753 | #define MDP4_PIPE_OP_MODE_SCALEY_EN 0x00000002 |
| 754 | #define MDP4_PIPE_OP_MODE_SRC_YCBCR 0x00000200 |
| 755 | #define MDP4_PIPE_OP_MODE_DST_YCBCR 0x00000400 |
| 756 | #define MDP4_PIPE_OP_MODE_CSC_EN 0x00000800 |
| 757 | #define MDP4_PIPE_OP_MODE_FLIP_LR 0x00002000 |
| 758 | #define MDP4_PIPE_OP_MODE_FLIP_UD 0x00004000 |
| 759 | #define MDP4_PIPE_OP_MODE_DITHER_EN 0x00008000 |
| 760 | #define MDP4_PIPE_OP_MODE_IGC_LUT_EN 0x00010000 |
| 761 | #define MDP4_PIPE_OP_MODE_DEINT_EN 0x00040000 |
| 762 | #define MDP4_PIPE_OP_MODE_DEINT_ODD_REF 0x00080000 |
| 763 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 764 | static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i0; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 765 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 766 | static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i0; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 767 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 768 | static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*i0; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 769 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 770 | static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i0; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 771 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 772 | static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 773 | |
| 774 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 775 | static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 776 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 777 | static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 778 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 779 | static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 780 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 781 | static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 782 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 783 | static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 784 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 785 | static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 786 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 787 | static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 788 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 789 | static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 790 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 791 | static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 792 | |
Rob Clark | 22ba8b6 | 2013-10-07 12:42:27 -0400 | [diff] [blame] | 793 | static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 794 | |
| 795 | #define REG_MDP4_LCDC 0x000c0000 |
| 796 | |
| 797 | #define REG_MDP4_LCDC_ENABLE 0x000c0000 |
| 798 | |
| 799 | #define REG_MDP4_LCDC_HSYNC_CTRL 0x000c0004 |
| 800 | #define MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK 0x0000ffff |
| 801 | #define MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT 0 |
| 802 | static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val) |
| 803 | { |
| 804 | return ((val) << MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK; |
| 805 | } |
| 806 | #define MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK 0xffff0000 |
| 807 | #define MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT 16 |
| 808 | static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val) |
| 809 | { |
| 810 | return ((val) << MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK; |
| 811 | } |
| 812 | |
| 813 | #define REG_MDP4_LCDC_VSYNC_PERIOD 0x000c0008 |
| 814 | |
| 815 | #define REG_MDP4_LCDC_VSYNC_LEN 0x000c000c |
| 816 | |
| 817 | #define REG_MDP4_LCDC_DISPLAY_HCTRL 0x000c0010 |
| 818 | #define MDP4_LCDC_DISPLAY_HCTRL_START__MASK 0x0000ffff |
| 819 | #define MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT 0 |
| 820 | static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val) |
| 821 | { |
| 822 | return ((val) << MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_START__MASK; |
| 823 | } |
| 824 | #define MDP4_LCDC_DISPLAY_HCTRL_END__MASK 0xffff0000 |
| 825 | #define MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT 16 |
| 826 | static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val) |
| 827 | { |
| 828 | return ((val) << MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_END__MASK; |
| 829 | } |
| 830 | |
| 831 | #define REG_MDP4_LCDC_DISPLAY_VSTART 0x000c0014 |
| 832 | |
| 833 | #define REG_MDP4_LCDC_DISPLAY_VEND 0x000c0018 |
| 834 | |
| 835 | #define REG_MDP4_LCDC_ACTIVE_HCTL 0x000c001c |
| 836 | #define MDP4_LCDC_ACTIVE_HCTL_START__MASK 0x00007fff |
| 837 | #define MDP4_LCDC_ACTIVE_HCTL_START__SHIFT 0 |
| 838 | static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val) |
| 839 | { |
| 840 | return ((val) << MDP4_LCDC_ACTIVE_HCTL_START__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_START__MASK; |
| 841 | } |
| 842 | #define MDP4_LCDC_ACTIVE_HCTL_END__MASK 0x7fff0000 |
| 843 | #define MDP4_LCDC_ACTIVE_HCTL_END__SHIFT 16 |
| 844 | static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val) |
| 845 | { |
| 846 | return ((val) << MDP4_LCDC_ACTIVE_HCTL_END__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_END__MASK; |
| 847 | } |
| 848 | #define MDP4_LCDC_ACTIVE_HCTL_ACTIVE_START_X 0x80000000 |
| 849 | |
| 850 | #define REG_MDP4_LCDC_ACTIVE_VSTART 0x000c0020 |
| 851 | |
| 852 | #define REG_MDP4_LCDC_ACTIVE_VEND 0x000c0024 |
| 853 | |
| 854 | #define REG_MDP4_LCDC_BORDER_CLR 0x000c0028 |
| 855 | |
| 856 | #define REG_MDP4_LCDC_UNDERFLOW_CLR 0x000c002c |
| 857 | #define MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff |
| 858 | #define MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT 0 |
| 859 | static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val) |
| 860 | { |
| 861 | return ((val) << MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK; |
| 862 | } |
| 863 | #define MDP4_LCDC_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000 |
| 864 | |
| 865 | #define REG_MDP4_LCDC_HSYNC_SKEW 0x000c0030 |
| 866 | |
| 867 | #define REG_MDP4_LCDC_TEST_CNTL 0x000c0034 |
| 868 | |
| 869 | #define REG_MDP4_LCDC_CTRL_POLARITY 0x000c0038 |
| 870 | #define MDP4_LCDC_CTRL_POLARITY_HSYNC_LOW 0x00000001 |
| 871 | #define MDP4_LCDC_CTRL_POLARITY_VSYNC_LOW 0x00000002 |
| 872 | #define MDP4_LCDC_CTRL_POLARITY_DATA_EN_LOW 0x00000004 |
| 873 | |
Rob Clark | f9a1ca5 | 2014-08-01 08:26:56 -0400 | [diff] [blame] | 874 | #define REG_MDP4_LCDC_LVDS_INTF_CTL 0x000c2000 |
| 875 | #define MDP4_LCDC_LVDS_INTF_CTL_MODE_SEL 0x00000004 |
| 876 | #define MDP4_LCDC_LVDS_INTF_CTL_RGB_OUT 0x00000008 |
| 877 | #define MDP4_LCDC_LVDS_INTF_CTL_CH_SWAP 0x00000010 |
| 878 | #define MDP4_LCDC_LVDS_INTF_CTL_CH1_RES_BIT 0x00000020 |
| 879 | #define MDP4_LCDC_LVDS_INTF_CTL_CH2_RES_BIT 0x00000040 |
| 880 | #define MDP4_LCDC_LVDS_INTF_CTL_ENABLE 0x00000080 |
| 881 | #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN 0x00000100 |
| 882 | #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN 0x00000200 |
| 883 | #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN 0x00000400 |
| 884 | #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE3_EN 0x00000800 |
| 885 | #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE0_EN 0x00001000 |
| 886 | #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE1_EN 0x00002000 |
| 887 | #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE2_EN 0x00004000 |
| 888 | #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE3_EN 0x00008000 |
| 889 | #define MDP4_LCDC_LVDS_INTF_CTL_CH1_CLK_LANE_EN 0x00010000 |
| 890 | #define MDP4_LCDC_LVDS_INTF_CTL_CH2_CLK_LANE_EN 0x00020000 |
| 891 | |
| 892 | static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) { return 0x000c2014 + 0x8*i0; } |
| 893 | |
| 894 | static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) { return 0x000c2014 + 0x8*i0; } |
| 895 | #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK 0x000000ff |
| 896 | #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT 0 |
| 897 | static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val) |
| 898 | { |
| 899 | return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK; |
| 900 | } |
| 901 | #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK 0x0000ff00 |
| 902 | #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT 8 |
| 903 | static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val) |
| 904 | { |
| 905 | return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK; |
| 906 | } |
| 907 | #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK 0x00ff0000 |
| 908 | #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT 16 |
| 909 | static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val) |
| 910 | { |
| 911 | return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK; |
| 912 | } |
| 913 | #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK 0xff000000 |
| 914 | #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT 24 |
| 915 | static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val) |
| 916 | { |
| 917 | return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK; |
| 918 | } |
| 919 | |
| 920 | static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) { return 0x000c2018 + 0x8*i0; } |
| 921 | #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK 0x000000ff |
| 922 | #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT 0 |
| 923 | static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val) |
| 924 | { |
| 925 | return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK; |
| 926 | } |
| 927 | #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK 0x0000ff00 |
| 928 | #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT 8 |
| 929 | static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val) |
| 930 | { |
| 931 | return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK; |
| 932 | } |
| 933 | #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK 0x00ff0000 |
| 934 | #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT 16 |
| 935 | static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val) |
| 936 | { |
| 937 | return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK; |
| 938 | } |
| 939 | |
| 940 | #define REG_MDP4_LCDC_LVDS_PHY_RESET 0x000c2034 |
| 941 | |
| 942 | #define REG_MDP4_LVDS_PHY_PLL_CTRL_0 0x000c3000 |
| 943 | |
| 944 | #define REG_MDP4_LVDS_PHY_PLL_CTRL_1 0x000c3004 |
| 945 | |
| 946 | #define REG_MDP4_LVDS_PHY_PLL_CTRL_2 0x000c3008 |
| 947 | |
| 948 | #define REG_MDP4_LVDS_PHY_PLL_CTRL_3 0x000c300c |
| 949 | |
| 950 | #define REG_MDP4_LVDS_PHY_PLL_CTRL_5 0x000c3014 |
| 951 | |
| 952 | #define REG_MDP4_LVDS_PHY_PLL_CTRL_6 0x000c3018 |
| 953 | |
| 954 | #define REG_MDP4_LVDS_PHY_PLL_CTRL_7 0x000c301c |
| 955 | |
| 956 | #define REG_MDP4_LVDS_PHY_PLL_CTRL_8 0x000c3020 |
| 957 | |
| 958 | #define REG_MDP4_LVDS_PHY_PLL_CTRL_9 0x000c3024 |
| 959 | |
| 960 | #define REG_MDP4_LVDS_PHY_PLL_LOCKED 0x000c3080 |
| 961 | |
| 962 | #define REG_MDP4_LVDS_PHY_CFG2 0x000c3108 |
| 963 | |
| 964 | #define REG_MDP4_LVDS_PHY_CFG0 0x000c3100 |
| 965 | #define MDP4_LVDS_PHY_CFG0_SERIALIZATION_ENBLE 0x00000010 |
| 966 | #define MDP4_LVDS_PHY_CFG0_CHANNEL0 0x00000040 |
| 967 | #define MDP4_LVDS_PHY_CFG0_CHANNEL1 0x00000080 |
| 968 | |
Rob Clark | 0cf6c71 | 2013-06-24 17:12:04 -0400 | [diff] [blame] | 969 | #define REG_MDP4_DTV 0x000d0000 |
| 970 | |
| 971 | #define REG_MDP4_DTV_ENABLE 0x000d0000 |
| 972 | |
| 973 | #define REG_MDP4_DTV_HSYNC_CTRL 0x000d0004 |
| 974 | #define MDP4_DTV_HSYNC_CTRL_PULSEW__MASK 0x0000ffff |
| 975 | #define MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT 0 |
| 976 | static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val) |
| 977 | { |
| 978 | return ((val) << MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DTV_HSYNC_CTRL_PULSEW__MASK; |
| 979 | } |
| 980 | #define MDP4_DTV_HSYNC_CTRL_PERIOD__MASK 0xffff0000 |
| 981 | #define MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT 16 |
| 982 | static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val) |
| 983 | { |
| 984 | return ((val) << MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DTV_HSYNC_CTRL_PERIOD__MASK; |
| 985 | } |
| 986 | |
| 987 | #define REG_MDP4_DTV_VSYNC_PERIOD 0x000d0008 |
| 988 | |
| 989 | #define REG_MDP4_DTV_VSYNC_LEN 0x000d000c |
| 990 | |
| 991 | #define REG_MDP4_DTV_DISPLAY_HCTRL 0x000d0018 |
| 992 | #define MDP4_DTV_DISPLAY_HCTRL_START__MASK 0x0000ffff |
| 993 | #define MDP4_DTV_DISPLAY_HCTRL_START__SHIFT 0 |
| 994 | static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val) |
| 995 | { |
| 996 | return ((val) << MDP4_DTV_DISPLAY_HCTRL_START__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_START__MASK; |
| 997 | } |
| 998 | #define MDP4_DTV_DISPLAY_HCTRL_END__MASK 0xffff0000 |
| 999 | #define MDP4_DTV_DISPLAY_HCTRL_END__SHIFT 16 |
| 1000 | static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val) |
| 1001 | { |
| 1002 | return ((val) << MDP4_DTV_DISPLAY_HCTRL_END__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_END__MASK; |
| 1003 | } |
| 1004 | |
| 1005 | #define REG_MDP4_DTV_DISPLAY_VSTART 0x000d001c |
| 1006 | |
| 1007 | #define REG_MDP4_DTV_DISPLAY_VEND 0x000d0020 |
| 1008 | |
| 1009 | #define REG_MDP4_DTV_ACTIVE_HCTL 0x000d002c |
| 1010 | #define MDP4_DTV_ACTIVE_HCTL_START__MASK 0x00007fff |
| 1011 | #define MDP4_DTV_ACTIVE_HCTL_START__SHIFT 0 |
| 1012 | static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val) |
| 1013 | { |
| 1014 | return ((val) << MDP4_DTV_ACTIVE_HCTL_START__SHIFT) & MDP4_DTV_ACTIVE_HCTL_START__MASK; |
| 1015 | } |
| 1016 | #define MDP4_DTV_ACTIVE_HCTL_END__MASK 0x7fff0000 |
| 1017 | #define MDP4_DTV_ACTIVE_HCTL_END__SHIFT 16 |
| 1018 | static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val) |
| 1019 | { |
| 1020 | return ((val) << MDP4_DTV_ACTIVE_HCTL_END__SHIFT) & MDP4_DTV_ACTIVE_HCTL_END__MASK; |
| 1021 | } |
| 1022 | #define MDP4_DTV_ACTIVE_HCTL_ACTIVE_START_X 0x80000000 |
| 1023 | |
| 1024 | #define REG_MDP4_DTV_ACTIVE_VSTART 0x000d0030 |
| 1025 | |
| 1026 | #define REG_MDP4_DTV_ACTIVE_VEND 0x000d0038 |
| 1027 | |
| 1028 | #define REG_MDP4_DTV_BORDER_CLR 0x000d0040 |
| 1029 | |
| 1030 | #define REG_MDP4_DTV_UNDERFLOW_CLR 0x000d0044 |
| 1031 | #define MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff |
| 1032 | #define MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT 0 |
| 1033 | static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val) |
| 1034 | { |
| 1035 | return ((val) << MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK; |
| 1036 | } |
| 1037 | #define MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000 |
| 1038 | |
| 1039 | #define REG_MDP4_DTV_HSYNC_SKEW 0x000d0048 |
| 1040 | |
| 1041 | #define REG_MDP4_DTV_TEST_CNTL 0x000d004c |
| 1042 | |
| 1043 | #define REG_MDP4_DTV_CTRL_POLARITY 0x000d0050 |
| 1044 | #define MDP4_DTV_CTRL_POLARITY_HSYNC_LOW 0x00000001 |
| 1045 | #define MDP4_DTV_CTRL_POLARITY_VSYNC_LOW 0x00000002 |
| 1046 | #define MDP4_DTV_CTRL_POLARITY_DATA_EN_LOW 0x00000004 |
| 1047 | |
| 1048 | #define REG_MDP4_DSI 0x000e0000 |
| 1049 | |
| 1050 | #define REG_MDP4_DSI_ENABLE 0x000e0000 |
| 1051 | |
| 1052 | #define REG_MDP4_DSI_HSYNC_CTRL 0x000e0004 |
| 1053 | #define MDP4_DSI_HSYNC_CTRL_PULSEW__MASK 0x0000ffff |
| 1054 | #define MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT 0 |
| 1055 | static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val) |
| 1056 | { |
| 1057 | return ((val) << MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DSI_HSYNC_CTRL_PULSEW__MASK; |
| 1058 | } |
| 1059 | #define MDP4_DSI_HSYNC_CTRL_PERIOD__MASK 0xffff0000 |
| 1060 | #define MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT 16 |
| 1061 | static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val) |
| 1062 | { |
| 1063 | return ((val) << MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DSI_HSYNC_CTRL_PERIOD__MASK; |
| 1064 | } |
| 1065 | |
| 1066 | #define REG_MDP4_DSI_VSYNC_PERIOD 0x000e0008 |
| 1067 | |
| 1068 | #define REG_MDP4_DSI_VSYNC_LEN 0x000e000c |
| 1069 | |
| 1070 | #define REG_MDP4_DSI_DISPLAY_HCTRL 0x000e0010 |
| 1071 | #define MDP4_DSI_DISPLAY_HCTRL_START__MASK 0x0000ffff |
| 1072 | #define MDP4_DSI_DISPLAY_HCTRL_START__SHIFT 0 |
| 1073 | static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val) |
| 1074 | { |
| 1075 | return ((val) << MDP4_DSI_DISPLAY_HCTRL_START__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_START__MASK; |
| 1076 | } |
| 1077 | #define MDP4_DSI_DISPLAY_HCTRL_END__MASK 0xffff0000 |
| 1078 | #define MDP4_DSI_DISPLAY_HCTRL_END__SHIFT 16 |
| 1079 | static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val) |
| 1080 | { |
| 1081 | return ((val) << MDP4_DSI_DISPLAY_HCTRL_END__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_END__MASK; |
| 1082 | } |
| 1083 | |
| 1084 | #define REG_MDP4_DSI_DISPLAY_VSTART 0x000e0014 |
| 1085 | |
| 1086 | #define REG_MDP4_DSI_DISPLAY_VEND 0x000e0018 |
| 1087 | |
| 1088 | #define REG_MDP4_DSI_ACTIVE_HCTL 0x000e001c |
| 1089 | #define MDP4_DSI_ACTIVE_HCTL_START__MASK 0x00007fff |
| 1090 | #define MDP4_DSI_ACTIVE_HCTL_START__SHIFT 0 |
| 1091 | static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val) |
| 1092 | { |
| 1093 | return ((val) << MDP4_DSI_ACTIVE_HCTL_START__SHIFT) & MDP4_DSI_ACTIVE_HCTL_START__MASK; |
| 1094 | } |
| 1095 | #define MDP4_DSI_ACTIVE_HCTL_END__MASK 0x7fff0000 |
| 1096 | #define MDP4_DSI_ACTIVE_HCTL_END__SHIFT 16 |
| 1097 | static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val) |
| 1098 | { |
| 1099 | return ((val) << MDP4_DSI_ACTIVE_HCTL_END__SHIFT) & MDP4_DSI_ACTIVE_HCTL_END__MASK; |
| 1100 | } |
| 1101 | #define MDP4_DSI_ACTIVE_HCTL_ACTIVE_START_X 0x80000000 |
| 1102 | |
| 1103 | #define REG_MDP4_DSI_ACTIVE_VSTART 0x000e0020 |
| 1104 | |
| 1105 | #define REG_MDP4_DSI_ACTIVE_VEND 0x000e0024 |
| 1106 | |
| 1107 | #define REG_MDP4_DSI_BORDER_CLR 0x000e0028 |
| 1108 | |
| 1109 | #define REG_MDP4_DSI_UNDERFLOW_CLR 0x000e002c |
| 1110 | #define MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff |
| 1111 | #define MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT 0 |
| 1112 | static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val) |
| 1113 | { |
| 1114 | return ((val) << MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK; |
| 1115 | } |
| 1116 | #define MDP4_DSI_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000 |
| 1117 | |
| 1118 | #define REG_MDP4_DSI_HSYNC_SKEW 0x000e0030 |
| 1119 | |
| 1120 | #define REG_MDP4_DSI_TEST_CNTL 0x000e0034 |
| 1121 | |
| 1122 | #define REG_MDP4_DSI_CTRL_POLARITY 0x000e0038 |
| 1123 | #define MDP4_DSI_CTRL_POLARITY_HSYNC_LOW 0x00000001 |
| 1124 | #define MDP4_DSI_CTRL_POLARITY_VSYNC_LOW 0x00000002 |
| 1125 | #define MDP4_DSI_CTRL_POLARITY_DATA_EN_LOW 0x00000004 |
| 1126 | |
| 1127 | |
| 1128 | #endif /* MDP4_XML */ |