Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / b2abb271a5705bc80478e79d95fc9f3babc2605c / . / arch / arm / mach-omap2 / sram34xx.S
blob: 35131e5bc7d165f9ca5cc8c139149c4eb0565f3c [file] [log] [blame]
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]1/*
2 * linux/arch/arm/mach-omap3/sram.S
3 *
4 * Omap3 specific functions that need to be run in internal SRAM
5 *
6 * (C) Copyright 2007
7 * Texas Instruments Inc.
8 * Rajendra Nayak <rnayak@ti.com>
9 *
10 * (C) Copyright 2004
11 * Texas Instruments, <www.ti.com>
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29#include <linux/linkage.h>
30#include <asm/assembler.h>
31#include <mach/hardware.h>
32
33#include <mach/io.h>
34
35#include "sdrc.h"
36#include "cm.h"
37
38 .text
39
40/*
41 * Change frequency of core dpll
42 * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
43 */
44ENTRY(omap3_sram_configure_core_dpll)
45 stmfd sp!, {r1-r12, lr} @ store regs to stack
Paul Walmsley69d42552009-05-12 17:27:09 -0600[diff] [blame]46 dsb @ flush buffered writes to interconnect
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]47 cmp r3, #0x2
48 blne configure_sdrc
49 cmp r3, #0x2
50 blne lock_dll
51 cmp r3, #0x1
52 blne unlock_dll
53 bl sdram_in_selfrefresh @ put the SDRAM in self refresh
54 bl configure_core_dpll
55 bl enable_sdrc
56 cmp r3, #0x1
57 blne wait_dll_unlock
58 cmp r3, #0x2
59 blne wait_dll_lock
60 cmp r3, #0x1
61 blne configure_sdrc
Paul Walmsley69d42552009-05-12 17:27:09 -0600[diff] [blame]62 isb @ prevent speculative exec past here
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]63 mov r0, #0 @ return value
64 ldmfd sp!, {r1-r12, pc} @ restore regs and return
65unlock_dll:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame^]66 ldr r11, omap3_sdrc_dlla_ctrl
67 ldr r12, [r11]
68 orr r12, r12, #0x4
69 str r12, [r11] @ (no OCP barrier needed)
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]70 bx lr
71lock_dll:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame^]72 ldr r11, omap3_sdrc_dlla_ctrl
73 ldr r12, [r11]
74 bic r12, r12, #0x4
75 str r12, [r11] @ (no OCP barrier needed)
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]76 bx lr
77sdram_in_selfrefresh:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame^]78 ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
79 ldr r12, [r11] @ read the contents of SDRC_POWER
80 mov r9, r12 @ keep a copy of SDRC_POWER bits
81 orr r12, r12, #0x40 @ enable self refresh on idle req
82 bic r12, r12, #0x4 @ clear PWDENA
83 str r12, [r11] @ write back to SDRC_POWER register
84 ldr r12, [r11] @ posted-write barrier for SDRC
85 ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
86 ldr r12, [r11]
87 bic r12, r12, #0x2 @ disable iclk bit for SDRC
88 str r12, [r11]
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]89wait_sdrc_idle:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame^]90 ldr r11, omap3_cm_idlest1_core
91 ldr r12, [r11]
92 and r12, r12, #0x2 @ check for SDRC idle
93 cmp r12, #2
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]94 bne wait_sdrc_idle
95 bx lr
96configure_core_dpll:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame^]97 ldr r11, omap3_cm_clksel1_pll
98 ldr r12, [r11]
99 ldr r10, core_m2_mask_val @ modify m2 for core dpll
100 and r12, r12, r10
101 orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val
102 str r12, [r11]
103 ldr r12, [r11] @ posted-write barrier for CM
104 mov r12, #0x800 @ wait for the clock to stabilise
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]105 cmp r3, #2
106 bne wait_clk_stable
107 bx lr
108wait_clk_stable:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame^]109 subs r12, r12, #1
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]110 bne wait_clk_stable
111 nop
112 nop
113 nop
114 nop
115 nop
116 nop
117 nop
118 nop
119 nop
120 nop
121 bx lr
122enable_sdrc:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame^]123 ldr r11, omap3_cm_iclken1_core
124 ldr r12, [r11]
125 orr r12, r12, #0x2 @ enable iclk bit for SDRC
126 str r12, [r11]
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]127wait_sdrc_idle1:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame^]128 ldr r11, omap3_cm_idlest1_core
129 ldr r12, [r11]
130 and r12, r12, #0x2
131 cmp r12, #0
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]132 bne wait_sdrc_idle1
Paul Walmsleyfa0406a2009-05-12 17:27:09 -0600[diff] [blame]133restore_sdrc_power_val:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame^]134 ldr r11, omap3_sdrc_power
135 str r9, [r11] @ restore SDRC_POWER, no barrier needed
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]136 bx lr
137wait_dll_lock:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame^]138 ldr r11, omap3_sdrc_dlla_status
139 ldr r12, [r11]
140 and r12, r12, #0x4
141 cmp r12, #0x4
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]142 bne wait_dll_lock
143 bx lr
144wait_dll_unlock:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame^]145 ldr r11, omap3_sdrc_dlla_status
146 ldr r12, [r11]
147 and r12, r12, #0x4
148 cmp r12, #0x0
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]149 bne wait_dll_unlock
150 bx lr
151configure_sdrc:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame^]152 ldr r11, omap3_sdrc_rfr_ctrl
153 str r0, [r11]
154 ldr r11, omap3_sdrc_actim_ctrla
155 str r1, [r11]
156 ldr r11, omap3_sdrc_actim_ctrlb
157 str r2, [r11]
158 ldr r2, [r11] @ posted-write barrier for SDRC
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]159 bx lr
160
161omap3_sdrc_power:
162 .word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
163omap3_cm_clksel1_pll:
164 .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
165omap3_cm_idlest1_core:
166 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
167omap3_cm_iclken1_core:
168 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
169omap3_sdrc_rfr_ctrl:
170 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
171omap3_sdrc_actim_ctrla:
172 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
173omap3_sdrc_actim_ctrlb:
174 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
175omap3_sdrc_dlla_status:
176 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
177omap3_sdrc_dlla_ctrl:
178 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
179core_m2_mask_val:
180 .word 0x07FFFFFF
181
182ENTRY(omap3_sram_configure_core_dpll_sz)
183 .word . - omap3_sram_configure_core_dpll