Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * |
| 4 | * Refer to drivers/dma/imx-sdma.c |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/init.h> |
| 12 | #include <linux/types.h> |
| 13 | #include <linux/mm.h> |
| 14 | #include <linux/interrupt.h> |
| 15 | #include <linux/clk.h> |
| 16 | #include <linux/wait.h> |
| 17 | #include <linux/sched.h> |
| 18 | #include <linux/semaphore.h> |
| 19 | #include <linux/device.h> |
| 20 | #include <linux/dma-mapping.h> |
| 21 | #include <linux/slab.h> |
| 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/dmaengine.h> |
| 24 | #include <linux/delay.h> |
Dong Aisheng | 90c9abc | 2012-05-04 20:12:17 +0800 | [diff] [blame] | 25 | #include <linux/module.h> |
Dong Aisheng | f5b7efc | 2012-05-04 20:12:15 +0800 | [diff] [blame] | 26 | #include <linux/stmp_device.h> |
Dong Aisheng | 90c9abc | 2012-05-04 20:12:17 +0800 | [diff] [blame] | 27 | #include <linux/of.h> |
| 28 | #include <linux/of_device.h> |
Shawn Guo | d84f638 | 2013-02-26 09:42:09 +0800 | [diff] [blame] | 29 | #include <linux/of_dma.h> |
Markus Pargmann | b2d6398 | 2013-10-29 08:47:45 +0100 | [diff] [blame^] | 30 | #include <linux/list.h> |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 31 | |
| 32 | #include <asm/irq.h> |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 33 | |
Russell King - ARM Linux | d2ebfb3 | 2012-03-06 22:34:26 +0000 | [diff] [blame] | 34 | #include "dmaengine.h" |
| 35 | |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 36 | /* |
| 37 | * NOTE: The term "PIO" throughout the mxs-dma implementation means |
| 38 | * PIO mode of mxs apbh-dma and apbx-dma. With this working mode, |
| 39 | * dma can program the controller registers of peripheral devices. |
| 40 | */ |
| 41 | |
Shawn Guo | 8c92013 | 2012-05-10 06:23:26 +0800 | [diff] [blame] | 42 | #define dma_is_apbh(mxs_dma) ((mxs_dma)->type == MXS_DMA_APBH) |
| 43 | #define apbh_is_old(mxs_dma) ((mxs_dma)->dev_id == IMX23_DMA) |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 44 | |
| 45 | #define HW_APBHX_CTRL0 0x000 |
| 46 | #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29) |
| 47 | #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28) |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 48 | #define BP_APBH_CTRL0_RESET_CHANNEL 16 |
| 49 | #define HW_APBHX_CTRL1 0x010 |
| 50 | #define HW_APBHX_CTRL2 0x020 |
| 51 | #define HW_APBHX_CHANNEL_CTRL 0x030 |
| 52 | #define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16 |
Shawn Guo | bb11fb6 | 2012-05-07 14:14:08 +0800 | [diff] [blame] | 53 | /* |
| 54 | * The offset of NXTCMDAR register is different per both dma type and version, |
| 55 | * while stride for each channel is all the same 0x70. |
| 56 | */ |
| 57 | #define HW_APBHX_CHn_NXTCMDAR(d, n) \ |
| 58 | (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x050 : 0x110) + (n) * 0x70) |
| 59 | #define HW_APBHX_CHn_SEMA(d, n) \ |
| 60 | (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x080 : 0x140) + (n) * 0x70) |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 61 | |
| 62 | /* |
| 63 | * ccw bits definitions |
| 64 | * |
| 65 | * COMMAND: 0..1 (2) |
| 66 | * CHAIN: 2 (1) |
| 67 | * IRQ: 3 (1) |
| 68 | * NAND_LOCK: 4 (1) - not implemented |
| 69 | * NAND_WAIT4READY: 5 (1) - not implemented |
| 70 | * DEC_SEM: 6 (1) |
| 71 | * WAIT4END: 7 (1) |
| 72 | * HALT_ON_TERMINATE: 8 (1) |
| 73 | * TERMINATE_FLUSH: 9 (1) |
| 74 | * RESERVED: 10..11 (2) |
| 75 | * PIO_NUM: 12..15 (4) |
| 76 | */ |
| 77 | #define BP_CCW_COMMAND 0 |
| 78 | #define BM_CCW_COMMAND (3 << 0) |
| 79 | #define CCW_CHAIN (1 << 2) |
| 80 | #define CCW_IRQ (1 << 3) |
| 81 | #define CCW_DEC_SEM (1 << 6) |
| 82 | #define CCW_WAIT4END (1 << 7) |
| 83 | #define CCW_HALT_ON_TERM (1 << 8) |
| 84 | #define CCW_TERM_FLUSH (1 << 9) |
| 85 | #define BP_CCW_PIO_NUM 12 |
| 86 | #define BM_CCW_PIO_NUM (0xf << 12) |
| 87 | |
| 88 | #define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field) |
| 89 | |
| 90 | #define MXS_DMA_CMD_NO_XFER 0 |
| 91 | #define MXS_DMA_CMD_WRITE 1 |
| 92 | #define MXS_DMA_CMD_READ 2 |
| 93 | #define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */ |
| 94 | |
| 95 | struct mxs_dma_ccw { |
| 96 | u32 next; |
| 97 | u16 bits; |
| 98 | u16 xfer_bytes; |
| 99 | #define MAX_XFER_BYTES 0xff00 |
| 100 | u32 bufaddr; |
| 101 | #define MXS_PIO_WORDS 16 |
| 102 | u32 pio_words[MXS_PIO_WORDS]; |
| 103 | }; |
| 104 | |
Marek Vasut | 5e97fa9 | 2012-09-04 06:04:25 +0200 | [diff] [blame] | 105 | #define CCW_BLOCK_SIZE (4 * PAGE_SIZE) |
| 106 | #define NUM_CCW (int)(CCW_BLOCK_SIZE / sizeof(struct mxs_dma_ccw)) |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 107 | |
| 108 | struct mxs_dma_chan { |
| 109 | struct mxs_dma_engine *mxs_dma; |
| 110 | struct dma_chan chan; |
| 111 | struct dma_async_tx_descriptor desc; |
| 112 | struct tasklet_struct tasklet; |
Fabio Estevam | f2ad699 | 2013-01-07 23:48:39 -0200 | [diff] [blame] | 113 | unsigned int chan_irq; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 114 | struct mxs_dma_ccw *ccw; |
| 115 | dma_addr_t ccw_phys; |
Lothar Waßmann | 6d23ea4 | 2011-12-08 09:15:43 +0100 | [diff] [blame] | 116 | int desc_count; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 117 | enum dma_status status; |
| 118 | unsigned int flags; |
| 119 | #define MXS_DMA_SG_LOOP (1 << 0) |
| 120 | }; |
| 121 | |
| 122 | #define MXS_DMA_CHANNELS 16 |
| 123 | #define MXS_DMA_CHANNELS_MASK 0xffff |
| 124 | |
Shawn Guo | 8c92013 | 2012-05-10 06:23:26 +0800 | [diff] [blame] | 125 | enum mxs_dma_devtype { |
| 126 | MXS_DMA_APBH, |
| 127 | MXS_DMA_APBX, |
| 128 | }; |
| 129 | |
| 130 | enum mxs_dma_id { |
| 131 | IMX23_DMA, |
| 132 | IMX28_DMA, |
| 133 | }; |
| 134 | |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 135 | struct mxs_dma_engine { |
Shawn Guo | 8c92013 | 2012-05-10 06:23:26 +0800 | [diff] [blame] | 136 | enum mxs_dma_id dev_id; |
| 137 | enum mxs_dma_devtype type; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 138 | void __iomem *base; |
| 139 | struct clk *clk; |
| 140 | struct dma_device dma_device; |
| 141 | struct device_dma_parameters dma_parms; |
| 142 | struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS]; |
Shawn Guo | d84f638 | 2013-02-26 09:42:09 +0800 | [diff] [blame] | 143 | struct platform_device *pdev; |
| 144 | unsigned int nr_channels; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 145 | }; |
| 146 | |
Shawn Guo | 8c92013 | 2012-05-10 06:23:26 +0800 | [diff] [blame] | 147 | struct mxs_dma_type { |
| 148 | enum mxs_dma_id id; |
| 149 | enum mxs_dma_devtype type; |
| 150 | }; |
| 151 | |
| 152 | static struct mxs_dma_type mxs_dma_types[] = { |
| 153 | { |
| 154 | .id = IMX23_DMA, |
| 155 | .type = MXS_DMA_APBH, |
| 156 | }, { |
| 157 | .id = IMX23_DMA, |
| 158 | .type = MXS_DMA_APBX, |
| 159 | }, { |
| 160 | .id = IMX28_DMA, |
| 161 | .type = MXS_DMA_APBH, |
| 162 | }, { |
| 163 | .id = IMX28_DMA, |
| 164 | .type = MXS_DMA_APBX, |
| 165 | } |
| 166 | }; |
| 167 | |
| 168 | static struct platform_device_id mxs_dma_ids[] = { |
| 169 | { |
| 170 | .name = "imx23-dma-apbh", |
| 171 | .driver_data = (kernel_ulong_t) &mxs_dma_types[0], |
| 172 | }, { |
| 173 | .name = "imx23-dma-apbx", |
| 174 | .driver_data = (kernel_ulong_t) &mxs_dma_types[1], |
| 175 | }, { |
| 176 | .name = "imx28-dma-apbh", |
| 177 | .driver_data = (kernel_ulong_t) &mxs_dma_types[2], |
| 178 | }, { |
| 179 | .name = "imx28-dma-apbx", |
| 180 | .driver_data = (kernel_ulong_t) &mxs_dma_types[3], |
| 181 | }, { |
| 182 | /* end of list */ |
| 183 | } |
| 184 | }; |
| 185 | |
Dong Aisheng | 90c9abc | 2012-05-04 20:12:17 +0800 | [diff] [blame] | 186 | static const struct of_device_id mxs_dma_dt_ids[] = { |
| 187 | { .compatible = "fsl,imx23-dma-apbh", .data = &mxs_dma_ids[0], }, |
| 188 | { .compatible = "fsl,imx23-dma-apbx", .data = &mxs_dma_ids[1], }, |
| 189 | { .compatible = "fsl,imx28-dma-apbh", .data = &mxs_dma_ids[2], }, |
| 190 | { .compatible = "fsl,imx28-dma-apbx", .data = &mxs_dma_ids[3], }, |
| 191 | { /* sentinel */ } |
| 192 | }; |
| 193 | MODULE_DEVICE_TABLE(of, mxs_dma_dt_ids); |
| 194 | |
Shawn Guo | 8c92013 | 2012-05-10 06:23:26 +0800 | [diff] [blame] | 195 | static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan) |
| 196 | { |
| 197 | return container_of(chan, struct mxs_dma_chan, chan); |
| 198 | } |
| 199 | |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 200 | static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan) |
| 201 | { |
| 202 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; |
| 203 | int chan_id = mxs_chan->chan.chan_id; |
| 204 | |
Shawn Guo | bb11fb6 | 2012-05-07 14:14:08 +0800 | [diff] [blame] | 205 | if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 206 | writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL), |
Dong Aisheng | f5b7efc | 2012-05-04 20:12:15 +0800 | [diff] [blame] | 207 | mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 208 | else |
| 209 | writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL), |
Dong Aisheng | f5b7efc | 2012-05-04 20:12:15 +0800 | [diff] [blame] | 210 | mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 211 | } |
| 212 | |
| 213 | static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan) |
| 214 | { |
| 215 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; |
| 216 | int chan_id = mxs_chan->chan.chan_id; |
| 217 | |
| 218 | /* set cmd_addr up */ |
| 219 | writel(mxs_chan->ccw_phys, |
Shawn Guo | bb11fb6 | 2012-05-07 14:14:08 +0800 | [diff] [blame] | 220 | mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(mxs_dma, chan_id)); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 221 | |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 222 | /* write 1 to SEMA to kick off the channel */ |
Shawn Guo | bb11fb6 | 2012-05-07 14:14:08 +0800 | [diff] [blame] | 223 | writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id)); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 224 | } |
| 225 | |
| 226 | static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan) |
| 227 | { |
Vinod Koul | 2737583 | 2013-10-16 20:51:30 +0530 | [diff] [blame] | 228 | mxs_chan->status = DMA_COMPLETE; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 229 | } |
| 230 | |
| 231 | static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan) |
| 232 | { |
| 233 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; |
| 234 | int chan_id = mxs_chan->chan.chan_id; |
| 235 | |
| 236 | /* freeze the channel */ |
Shawn Guo | bb11fb6 | 2012-05-07 14:14:08 +0800 | [diff] [blame] | 237 | if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 238 | writel(1 << chan_id, |
Dong Aisheng | f5b7efc | 2012-05-04 20:12:15 +0800 | [diff] [blame] | 239 | mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 240 | else |
| 241 | writel(1 << chan_id, |
Dong Aisheng | f5b7efc | 2012-05-04 20:12:15 +0800 | [diff] [blame] | 242 | mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 243 | |
| 244 | mxs_chan->status = DMA_PAUSED; |
| 245 | } |
| 246 | |
| 247 | static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan) |
| 248 | { |
| 249 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; |
| 250 | int chan_id = mxs_chan->chan.chan_id; |
| 251 | |
| 252 | /* unfreeze the channel */ |
Shawn Guo | bb11fb6 | 2012-05-07 14:14:08 +0800 | [diff] [blame] | 253 | if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 254 | writel(1 << chan_id, |
Dong Aisheng | f5b7efc | 2012-05-04 20:12:15 +0800 | [diff] [blame] | 255 | mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 256 | else |
| 257 | writel(1 << chan_id, |
Dong Aisheng | f5b7efc | 2012-05-04 20:12:15 +0800 | [diff] [blame] | 258 | mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_CLR); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 259 | |
| 260 | mxs_chan->status = DMA_IN_PROGRESS; |
| 261 | } |
| 262 | |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 263 | static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx) |
| 264 | { |
Russell King - ARM Linux | 884485e | 2012-03-06 22:34:46 +0000 | [diff] [blame] | 265 | return dma_cookie_assign(tx); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 266 | } |
| 267 | |
| 268 | static void mxs_dma_tasklet(unsigned long data) |
| 269 | { |
| 270 | struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data; |
| 271 | |
| 272 | if (mxs_chan->desc.callback) |
| 273 | mxs_chan->desc.callback(mxs_chan->desc.callback_param); |
| 274 | } |
| 275 | |
Markus Pargmann | b2d6398 | 2013-10-29 08:47:45 +0100 | [diff] [blame^] | 276 | static int mxs_dma_irq_to_chan(struct mxs_dma_engine *mxs_dma, int irq) |
| 277 | { |
| 278 | int i; |
| 279 | |
| 280 | for (i = 0; i != mxs_dma->nr_channels; ++i) |
| 281 | if (mxs_dma->mxs_chans[i].chan_irq == irq) |
| 282 | return i; |
| 283 | |
| 284 | return -EINVAL; |
| 285 | } |
| 286 | |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 287 | static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id) |
| 288 | { |
| 289 | struct mxs_dma_engine *mxs_dma = dev_id; |
Markus Pargmann | b2d6398 | 2013-10-29 08:47:45 +0100 | [diff] [blame^] | 290 | struct mxs_dma_chan *mxs_chan; |
| 291 | u32 completed; |
| 292 | u32 err; |
| 293 | int chan = mxs_dma_irq_to_chan(mxs_dma, irq); |
| 294 | |
| 295 | if (chan < 0) |
| 296 | return IRQ_NONE; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 297 | |
| 298 | /* completion status */ |
Markus Pargmann | b2d6398 | 2013-10-29 08:47:45 +0100 | [diff] [blame^] | 299 | completed = readl(mxs_dma->base + HW_APBHX_CTRL1); |
| 300 | completed = (completed >> chan) & 0x1; |
| 301 | |
| 302 | /* Clear interrupt */ |
| 303 | writel((1 << chan), |
| 304 | mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 305 | |
| 306 | /* error status */ |
Markus Pargmann | b2d6398 | 2013-10-29 08:47:45 +0100 | [diff] [blame^] | 307 | err = readl(mxs_dma->base + HW_APBHX_CTRL2); |
| 308 | err &= (1 << (MXS_DMA_CHANNELS + chan)) | (1 << chan); |
| 309 | |
| 310 | /* |
| 311 | * error status bit is in the upper 16 bits, error irq bit in the lower |
| 312 | * 16 bits. We transform it into a simpler error code: |
| 313 | * err: 0x00 = no error, 0x01 = TERMINATION, 0x02 = BUS_ERROR |
| 314 | */ |
| 315 | err = (err >> (MXS_DMA_CHANNELS + chan)) + (err >> chan); |
| 316 | |
| 317 | /* Clear error irq */ |
| 318 | writel((1 << chan), |
| 319 | mxs_dma->base + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 320 | |
| 321 | /* |
| 322 | * When both completion and error of termination bits set at the |
| 323 | * same time, we do not take it as an error. IOW, it only becomes |
Markus Pargmann | b2d6398 | 2013-10-29 08:47:45 +0100 | [diff] [blame^] | 324 | * an error we need to handle here in case of either it's a bus |
| 325 | * error or a termination error with no completion. 0x01 is termination |
| 326 | * error, so we can subtract err & completed to get the real error case. |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 327 | */ |
Markus Pargmann | b2d6398 | 2013-10-29 08:47:45 +0100 | [diff] [blame^] | 328 | err -= err & completed; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 329 | |
Markus Pargmann | b2d6398 | 2013-10-29 08:47:45 +0100 | [diff] [blame^] | 330 | mxs_chan = &mxs_dma->mxs_chans[chan]; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 331 | |
Markus Pargmann | b2d6398 | 2013-10-29 08:47:45 +0100 | [diff] [blame^] | 332 | if (err) { |
| 333 | dev_dbg(mxs_dma->dma_device.dev, |
| 334 | "%s: error in channel %d\n", __func__, |
| 335 | chan); |
| 336 | mxs_chan->status = DMA_ERROR; |
| 337 | mxs_dma_reset_chan(mxs_chan); |
| 338 | } else { |
| 339 | if (mxs_chan->flags & MXS_DMA_SG_LOOP) |
| 340 | mxs_chan->status = DMA_IN_PROGRESS; |
| 341 | else |
| 342 | mxs_chan->status = DMA_COMPLETE; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 343 | } |
| 344 | |
Markus Pargmann | b2d6398 | 2013-10-29 08:47:45 +0100 | [diff] [blame^] | 345 | if (mxs_chan->status == DMA_COMPLETE) |
| 346 | dma_cookie_complete(&mxs_chan->desc); |
| 347 | |
| 348 | /* schedule tasklet on this channel */ |
| 349 | tasklet_schedule(&mxs_chan->tasklet); |
| 350 | |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 351 | return IRQ_HANDLED; |
| 352 | } |
| 353 | |
| 354 | static int mxs_dma_alloc_chan_resources(struct dma_chan *chan) |
| 355 | { |
| 356 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 357 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; |
| 358 | int ret; |
| 359 | |
Marek Vasut | 5e97fa9 | 2012-09-04 06:04:25 +0200 | [diff] [blame] | 360 | mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, |
| 361 | CCW_BLOCK_SIZE, &mxs_chan->ccw_phys, |
| 362 | GFP_KERNEL); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 363 | if (!mxs_chan->ccw) { |
| 364 | ret = -ENOMEM; |
| 365 | goto err_alloc; |
| 366 | } |
| 367 | |
Marek Vasut | 5e97fa9 | 2012-09-04 06:04:25 +0200 | [diff] [blame] | 368 | memset(mxs_chan->ccw, 0, CCW_BLOCK_SIZE); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 369 | |
Shawn Guo | 95bfea1 | 2011-06-30 16:06:33 +0800 | [diff] [blame] | 370 | if (mxs_chan->chan_irq != NO_IRQ) { |
| 371 | ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler, |
| 372 | 0, "mxs-dma", mxs_dma); |
| 373 | if (ret) |
| 374 | goto err_irq; |
| 375 | } |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 376 | |
Shawn Guo | 759a2e3 | 2011-12-20 13:54:00 +0800 | [diff] [blame] | 377 | ret = clk_prepare_enable(mxs_dma->clk); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 378 | if (ret) |
| 379 | goto err_clk; |
| 380 | |
| 381 | mxs_dma_reset_chan(mxs_chan); |
| 382 | |
| 383 | dma_async_tx_descriptor_init(&mxs_chan->desc, chan); |
| 384 | mxs_chan->desc.tx_submit = mxs_dma_tx_submit; |
| 385 | |
| 386 | /* the descriptor is ready */ |
| 387 | async_tx_ack(&mxs_chan->desc); |
| 388 | |
| 389 | return 0; |
| 390 | |
| 391 | err_clk: |
| 392 | free_irq(mxs_chan->chan_irq, mxs_dma); |
| 393 | err_irq: |
Marek Vasut | 5e97fa9 | 2012-09-04 06:04:25 +0200 | [diff] [blame] | 394 | dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE, |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 395 | mxs_chan->ccw, mxs_chan->ccw_phys); |
| 396 | err_alloc: |
| 397 | return ret; |
| 398 | } |
| 399 | |
| 400 | static void mxs_dma_free_chan_resources(struct dma_chan *chan) |
| 401 | { |
| 402 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); |
| 403 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; |
| 404 | |
| 405 | mxs_dma_disable_chan(mxs_chan); |
| 406 | |
| 407 | free_irq(mxs_chan->chan_irq, mxs_dma); |
| 408 | |
Marek Vasut | 5e97fa9 | 2012-09-04 06:04:25 +0200 | [diff] [blame] | 409 | dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE, |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 410 | mxs_chan->ccw, mxs_chan->ccw_phys); |
| 411 | |
Shawn Guo | 759a2e3 | 2011-12-20 13:54:00 +0800 | [diff] [blame] | 412 | clk_disable_unprepare(mxs_dma->clk); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 413 | } |
| 414 | |
Huang Shijie | 921de86 | 2012-02-16 14:17:33 +0800 | [diff] [blame] | 415 | /* |
| 416 | * How to use the flags for ->device_prep_slave_sg() : |
| 417 | * [1] If there is only one DMA command in the DMA chain, the code should be: |
| 418 | * ...... |
| 419 | * ->device_prep_slave_sg(DMA_CTRL_ACK); |
| 420 | * ...... |
| 421 | * [2] If there are two DMA commands in the DMA chain, the code should be |
| 422 | * ...... |
| 423 | * ->device_prep_slave_sg(0); |
| 424 | * ...... |
| 425 | * ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 426 | * ...... |
| 427 | * [3] If there are more than two DMA commands in the DMA chain, the code |
| 428 | * should be: |
| 429 | * ...... |
| 430 | * ->device_prep_slave_sg(0); // First |
| 431 | * ...... |
| 432 | * ->device_prep_slave_sg(DMA_PREP_INTERRUPT [| DMA_CTRL_ACK]); |
| 433 | * ...... |
| 434 | * ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK); // Last |
| 435 | * ...... |
| 436 | */ |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 437 | static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg( |
| 438 | struct dma_chan *chan, struct scatterlist *sgl, |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 439 | unsigned int sg_len, enum dma_transfer_direction direction, |
Linus Torvalds | 623ff77 | 2012-03-30 17:31:56 -0700 | [diff] [blame] | 440 | unsigned long flags, void *context) |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 441 | { |
| 442 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); |
| 443 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; |
| 444 | struct mxs_dma_ccw *ccw; |
| 445 | struct scatterlist *sg; |
Fabio Estevam | f2ad699 | 2013-01-07 23:48:39 -0200 | [diff] [blame] | 446 | u32 i, j; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 447 | u32 *pio; |
Huang Shijie | 921de86 | 2012-02-16 14:17:33 +0800 | [diff] [blame] | 448 | bool append = flags & DMA_PREP_INTERRUPT; |
Lothar Waßmann | 6d23ea4 | 2011-12-08 09:15:43 +0100 | [diff] [blame] | 449 | int idx = append ? mxs_chan->desc_count : 0; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 450 | |
| 451 | if (mxs_chan->status == DMA_IN_PROGRESS && !append) |
| 452 | return NULL; |
| 453 | |
| 454 | if (sg_len + (append ? idx : 0) > NUM_CCW) { |
| 455 | dev_err(mxs_dma->dma_device.dev, |
| 456 | "maximum number of sg exceeded: %d > %d\n", |
| 457 | sg_len, NUM_CCW); |
| 458 | goto err_out; |
| 459 | } |
| 460 | |
| 461 | mxs_chan->status = DMA_IN_PROGRESS; |
| 462 | mxs_chan->flags = 0; |
| 463 | |
| 464 | /* |
| 465 | * If the sg is prepared with append flag set, the sg |
| 466 | * will be appended to the last prepared sg. |
| 467 | */ |
| 468 | if (append) { |
| 469 | BUG_ON(idx < 1); |
| 470 | ccw = &mxs_chan->ccw[idx - 1]; |
| 471 | ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; |
| 472 | ccw->bits |= CCW_CHAIN; |
| 473 | ccw->bits &= ~CCW_IRQ; |
| 474 | ccw->bits &= ~CCW_DEC_SEM; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 475 | } else { |
| 476 | idx = 0; |
| 477 | } |
| 478 | |
Shawn Guo | 62268ce | 2011-12-13 23:48:03 +0800 | [diff] [blame] | 479 | if (direction == DMA_TRANS_NONE) { |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 480 | ccw = &mxs_chan->ccw[idx++]; |
| 481 | pio = (u32 *) sgl; |
| 482 | |
| 483 | for (j = 0; j < sg_len;) |
| 484 | ccw->pio_words[j++] = *pio++; |
| 485 | |
| 486 | ccw->bits = 0; |
| 487 | ccw->bits |= CCW_IRQ; |
| 488 | ccw->bits |= CCW_DEC_SEM; |
Huang Shijie | 921de86 | 2012-02-16 14:17:33 +0800 | [diff] [blame] | 489 | if (flags & DMA_CTRL_ACK) |
| 490 | ccw->bits |= CCW_WAIT4END; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 491 | ccw->bits |= CCW_HALT_ON_TERM; |
| 492 | ccw->bits |= CCW_TERM_FLUSH; |
| 493 | ccw->bits |= BF_CCW(sg_len, PIO_NUM); |
| 494 | ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND); |
| 495 | } else { |
| 496 | for_each_sg(sgl, sg, sg_len, i) { |
Lars-Peter Clausen | fdaf9c4 | 2012-04-25 20:50:52 +0200 | [diff] [blame] | 497 | if (sg_dma_len(sg) > MAX_XFER_BYTES) { |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 498 | dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n", |
Lars-Peter Clausen | fdaf9c4 | 2012-04-25 20:50:52 +0200 | [diff] [blame] | 499 | sg_dma_len(sg), MAX_XFER_BYTES); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 500 | goto err_out; |
| 501 | } |
| 502 | |
| 503 | ccw = &mxs_chan->ccw[idx++]; |
| 504 | |
| 505 | ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; |
| 506 | ccw->bufaddr = sg->dma_address; |
Lars-Peter Clausen | fdaf9c4 | 2012-04-25 20:50:52 +0200 | [diff] [blame] | 507 | ccw->xfer_bytes = sg_dma_len(sg); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 508 | |
| 509 | ccw->bits = 0; |
| 510 | ccw->bits |= CCW_CHAIN; |
| 511 | ccw->bits |= CCW_HALT_ON_TERM; |
| 512 | ccw->bits |= CCW_TERM_FLUSH; |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 513 | ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ? |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 514 | MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, |
| 515 | COMMAND); |
| 516 | |
| 517 | if (i + 1 == sg_len) { |
| 518 | ccw->bits &= ~CCW_CHAIN; |
| 519 | ccw->bits |= CCW_IRQ; |
| 520 | ccw->bits |= CCW_DEC_SEM; |
Huang Shijie | 921de86 | 2012-02-16 14:17:33 +0800 | [diff] [blame] | 521 | if (flags & DMA_CTRL_ACK) |
| 522 | ccw->bits |= CCW_WAIT4END; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 523 | } |
| 524 | } |
| 525 | } |
Lothar Waßmann | 6d23ea4 | 2011-12-08 09:15:43 +0100 | [diff] [blame] | 526 | mxs_chan->desc_count = idx; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 527 | |
| 528 | return &mxs_chan->desc; |
| 529 | |
| 530 | err_out: |
| 531 | mxs_chan->status = DMA_ERROR; |
| 532 | return NULL; |
| 533 | } |
| 534 | |
| 535 | static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic( |
| 536 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, |
Alexandre Bounine | 185ecb5 | 2012-03-08 15:35:13 -0500 | [diff] [blame] | 537 | size_t period_len, enum dma_transfer_direction direction, |
Peter Ujfalusi | ec8b5e4 | 2012-09-14 15:05:47 +0300 | [diff] [blame] | 538 | unsigned long flags, void *context) |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 539 | { |
| 540 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); |
| 541 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; |
Fabio Estevam | f2ad699 | 2013-01-07 23:48:39 -0200 | [diff] [blame] | 542 | u32 num_periods = buf_len / period_len; |
| 543 | u32 i = 0, buf = 0; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 544 | |
| 545 | if (mxs_chan->status == DMA_IN_PROGRESS) |
| 546 | return NULL; |
| 547 | |
| 548 | mxs_chan->status = DMA_IN_PROGRESS; |
| 549 | mxs_chan->flags |= MXS_DMA_SG_LOOP; |
| 550 | |
| 551 | if (num_periods > NUM_CCW) { |
| 552 | dev_err(mxs_dma->dma_device.dev, |
| 553 | "maximum number of sg exceeded: %d > %d\n", |
| 554 | num_periods, NUM_CCW); |
| 555 | goto err_out; |
| 556 | } |
| 557 | |
| 558 | if (period_len > MAX_XFER_BYTES) { |
| 559 | dev_err(mxs_dma->dma_device.dev, |
| 560 | "maximum period size exceeded: %d > %d\n", |
| 561 | period_len, MAX_XFER_BYTES); |
| 562 | goto err_out; |
| 563 | } |
| 564 | |
| 565 | while (buf < buf_len) { |
| 566 | struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i]; |
| 567 | |
| 568 | if (i + 1 == num_periods) |
| 569 | ccw->next = mxs_chan->ccw_phys; |
| 570 | else |
| 571 | ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1); |
| 572 | |
| 573 | ccw->bufaddr = dma_addr; |
| 574 | ccw->xfer_bytes = period_len; |
| 575 | |
| 576 | ccw->bits = 0; |
| 577 | ccw->bits |= CCW_CHAIN; |
| 578 | ccw->bits |= CCW_IRQ; |
| 579 | ccw->bits |= CCW_HALT_ON_TERM; |
| 580 | ccw->bits |= CCW_TERM_FLUSH; |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 581 | ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ? |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 582 | MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND); |
| 583 | |
| 584 | dma_addr += period_len; |
| 585 | buf += period_len; |
| 586 | |
| 587 | i++; |
| 588 | } |
Lothar Waßmann | 6d23ea4 | 2011-12-08 09:15:43 +0100 | [diff] [blame] | 589 | mxs_chan->desc_count = i; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 590 | |
| 591 | return &mxs_chan->desc; |
| 592 | |
| 593 | err_out: |
| 594 | mxs_chan->status = DMA_ERROR; |
| 595 | return NULL; |
| 596 | } |
| 597 | |
| 598 | static int mxs_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
| 599 | unsigned long arg) |
| 600 | { |
| 601 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); |
| 602 | int ret = 0; |
| 603 | |
| 604 | switch (cmd) { |
| 605 | case DMA_TERMINATE_ALL: |
Dong Aisheng | a62bae9 | 2011-07-19 12:09:56 +0800 | [diff] [blame] | 606 | mxs_dma_reset_chan(mxs_chan); |
Lothar Waßmann | 7ad7a34 | 2011-12-08 09:15:44 +0100 | [diff] [blame] | 607 | mxs_dma_disable_chan(mxs_chan); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 608 | break; |
| 609 | case DMA_PAUSE: |
| 610 | mxs_dma_pause_chan(mxs_chan); |
| 611 | break; |
| 612 | case DMA_RESUME: |
| 613 | mxs_dma_resume_chan(mxs_chan); |
| 614 | break; |
| 615 | default: |
| 616 | ret = -ENOSYS; |
| 617 | } |
| 618 | |
| 619 | return ret; |
| 620 | } |
| 621 | |
| 622 | static enum dma_status mxs_dma_tx_status(struct dma_chan *chan, |
| 623 | dma_cookie_t cookie, struct dma_tx_state *txstate) |
| 624 | { |
| 625 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 626 | |
Andy Shevchenko | 09d1669 | 2013-05-27 15:14:32 +0300 | [diff] [blame] | 627 | dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, 0); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 628 | |
| 629 | return mxs_chan->status; |
| 630 | } |
| 631 | |
| 632 | static void mxs_dma_issue_pending(struct dma_chan *chan) |
| 633 | { |
Shawn Guo | d04525e | 2012-04-11 13:29:31 +0800 | [diff] [blame] | 634 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); |
| 635 | |
| 636 | mxs_dma_enable_chan(mxs_chan); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 637 | } |
| 638 | |
| 639 | static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) |
| 640 | { |
| 641 | int ret; |
| 642 | |
Shawn Guo | 759a2e3 | 2011-12-20 13:54:00 +0800 | [diff] [blame] | 643 | ret = clk_prepare_enable(mxs_dma->clk); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 644 | if (ret) |
Lothar Waßmann | feb397d | 2011-12-08 09:15:42 +0100 | [diff] [blame] | 645 | return ret; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 646 | |
Dong Aisheng | f5b7efc | 2012-05-04 20:12:15 +0800 | [diff] [blame] | 647 | ret = stmp_reset_block(mxs_dma->base); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 648 | if (ret) |
| 649 | goto err_out; |
| 650 | |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 651 | /* enable apbh burst */ |
Shawn Guo | bb11fb6 | 2012-05-07 14:14:08 +0800 | [diff] [blame] | 652 | if (dma_is_apbh(mxs_dma)) { |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 653 | writel(BM_APBH_CTRL0_APB_BURST_EN, |
Dong Aisheng | f5b7efc | 2012-05-04 20:12:15 +0800 | [diff] [blame] | 654 | mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 655 | writel(BM_APBH_CTRL0_APB_BURST8_EN, |
Dong Aisheng | f5b7efc | 2012-05-04 20:12:15 +0800 | [diff] [blame] | 656 | mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 657 | } |
| 658 | |
| 659 | /* enable irq for all the channels */ |
| 660 | writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS, |
Dong Aisheng | f5b7efc | 2012-05-04 20:12:15 +0800 | [diff] [blame] | 661 | mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 662 | |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 663 | err_out: |
Linus Torvalds | 57f2685 | 2012-01-17 18:40:24 -0800 | [diff] [blame] | 664 | clk_disable_unprepare(mxs_dma->clk); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 665 | return ret; |
| 666 | } |
| 667 | |
Shawn Guo | d84f638 | 2013-02-26 09:42:09 +0800 | [diff] [blame] | 668 | struct mxs_dma_filter_param { |
| 669 | struct device_node *of_node; |
| 670 | unsigned int chan_id; |
| 671 | }; |
| 672 | |
| 673 | static bool mxs_dma_filter_fn(struct dma_chan *chan, void *fn_param) |
| 674 | { |
| 675 | struct mxs_dma_filter_param *param = fn_param; |
| 676 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); |
| 677 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; |
| 678 | int chan_irq; |
| 679 | |
| 680 | if (mxs_dma->dma_device.dev->of_node != param->of_node) |
| 681 | return false; |
| 682 | |
| 683 | if (chan->chan_id != param->chan_id) |
| 684 | return false; |
| 685 | |
| 686 | chan_irq = platform_get_irq(mxs_dma->pdev, param->chan_id); |
| 687 | if (chan_irq < 0) |
| 688 | return false; |
| 689 | |
| 690 | mxs_chan->chan_irq = chan_irq; |
| 691 | |
| 692 | return true; |
| 693 | } |
| 694 | |
Fabio Estevam | 3208b37 | 2013-05-24 16:37:27 -0300 | [diff] [blame] | 695 | static struct dma_chan *mxs_dma_xlate(struct of_phandle_args *dma_spec, |
Shawn Guo | d84f638 | 2013-02-26 09:42:09 +0800 | [diff] [blame] | 696 | struct of_dma *ofdma) |
| 697 | { |
| 698 | struct mxs_dma_engine *mxs_dma = ofdma->of_dma_data; |
| 699 | dma_cap_mask_t mask = mxs_dma->dma_device.cap_mask; |
| 700 | struct mxs_dma_filter_param param; |
| 701 | |
| 702 | if (dma_spec->args_count != 1) |
| 703 | return NULL; |
| 704 | |
| 705 | param.of_node = ofdma->of_node; |
| 706 | param.chan_id = dma_spec->args[0]; |
| 707 | |
| 708 | if (param.chan_id >= mxs_dma->nr_channels) |
| 709 | return NULL; |
| 710 | |
| 711 | return dma_request_channel(mask, mxs_dma_filter_fn, ¶m); |
| 712 | } |
| 713 | |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 714 | static int __init mxs_dma_probe(struct platform_device *pdev) |
| 715 | { |
Shawn Guo | d84f638 | 2013-02-26 09:42:09 +0800 | [diff] [blame] | 716 | struct device_node *np = pdev->dev.of_node; |
Dong Aisheng | 90c9abc | 2012-05-04 20:12:17 +0800 | [diff] [blame] | 717 | const struct platform_device_id *id_entry; |
| 718 | const struct of_device_id *of_id; |
| 719 | const struct mxs_dma_type *dma_type; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 720 | struct mxs_dma_engine *mxs_dma; |
| 721 | struct resource *iores; |
| 722 | int ret, i; |
| 723 | |
Shawn Guo | aaa2051 | 2013-02-25 14:57:26 +0800 | [diff] [blame] | 724 | mxs_dma = devm_kzalloc(&pdev->dev, sizeof(*mxs_dma), GFP_KERNEL); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 725 | if (!mxs_dma) |
| 726 | return -ENOMEM; |
| 727 | |
Shawn Guo | d84f638 | 2013-02-26 09:42:09 +0800 | [diff] [blame] | 728 | ret = of_property_read_u32(np, "dma-channels", &mxs_dma->nr_channels); |
| 729 | if (ret) { |
| 730 | dev_err(&pdev->dev, "failed to read dma-channels\n"); |
| 731 | return ret; |
| 732 | } |
| 733 | |
Dong Aisheng | 90c9abc | 2012-05-04 20:12:17 +0800 | [diff] [blame] | 734 | of_id = of_match_device(mxs_dma_dt_ids, &pdev->dev); |
| 735 | if (of_id) |
| 736 | id_entry = of_id->data; |
| 737 | else |
| 738 | id_entry = platform_get_device_id(pdev); |
| 739 | |
| 740 | dma_type = (struct mxs_dma_type *)id_entry->driver_data; |
Shawn Guo | 8c92013 | 2012-05-10 06:23:26 +0800 | [diff] [blame] | 741 | mxs_dma->type = dma_type->type; |
Dong Aisheng | 90c9abc | 2012-05-04 20:12:17 +0800 | [diff] [blame] | 742 | mxs_dma->dev_id = dma_type->id; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 743 | |
| 744 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Shawn Guo | aaa2051 | 2013-02-25 14:57:26 +0800 | [diff] [blame] | 745 | mxs_dma->base = devm_ioremap_resource(&pdev->dev, iores); |
| 746 | if (IS_ERR(mxs_dma->base)) |
| 747 | return PTR_ERR(mxs_dma->base); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 748 | |
Shawn Guo | aaa2051 | 2013-02-25 14:57:26 +0800 | [diff] [blame] | 749 | mxs_dma->clk = devm_clk_get(&pdev->dev, NULL); |
| 750 | if (IS_ERR(mxs_dma->clk)) |
| 751 | return PTR_ERR(mxs_dma->clk); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 752 | |
| 753 | dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask); |
| 754 | dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask); |
| 755 | |
| 756 | INIT_LIST_HEAD(&mxs_dma->dma_device.channels); |
| 757 | |
| 758 | /* Initialize channel parameters */ |
| 759 | for (i = 0; i < MXS_DMA_CHANNELS; i++) { |
| 760 | struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i]; |
| 761 | |
| 762 | mxs_chan->mxs_dma = mxs_dma; |
| 763 | mxs_chan->chan.device = &mxs_dma->dma_device; |
Russell King - ARM Linux | 8ac6954 | 2012-03-06 22:36:27 +0000 | [diff] [blame] | 764 | dma_cookie_init(&mxs_chan->chan); |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 765 | |
| 766 | tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet, |
| 767 | (unsigned long) mxs_chan); |
| 768 | |
| 769 | |
| 770 | /* Add the channel to mxs_chan list */ |
| 771 | list_add_tail(&mxs_chan->chan.device_node, |
| 772 | &mxs_dma->dma_device.channels); |
| 773 | } |
| 774 | |
| 775 | ret = mxs_dma_init(mxs_dma); |
| 776 | if (ret) |
Shawn Guo | aaa2051 | 2013-02-25 14:57:26 +0800 | [diff] [blame] | 777 | return ret; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 778 | |
Shawn Guo | d84f638 | 2013-02-26 09:42:09 +0800 | [diff] [blame] | 779 | mxs_dma->pdev = pdev; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 780 | mxs_dma->dma_device.dev = &pdev->dev; |
| 781 | |
| 782 | /* mxs_dma gets 65535 bytes maximum sg size */ |
| 783 | mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms; |
| 784 | dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES); |
| 785 | |
| 786 | mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources; |
| 787 | mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources; |
| 788 | mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status; |
| 789 | mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg; |
| 790 | mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic; |
| 791 | mxs_dma->dma_device.device_control = mxs_dma_control; |
| 792 | mxs_dma->dma_device.device_issue_pending = mxs_dma_issue_pending; |
| 793 | |
| 794 | ret = dma_async_device_register(&mxs_dma->dma_device); |
| 795 | if (ret) { |
| 796 | dev_err(mxs_dma->dma_device.dev, "unable to register\n"); |
Shawn Guo | aaa2051 | 2013-02-25 14:57:26 +0800 | [diff] [blame] | 797 | return ret; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 798 | } |
| 799 | |
Shawn Guo | d84f638 | 2013-02-26 09:42:09 +0800 | [diff] [blame] | 800 | ret = of_dma_controller_register(np, mxs_dma_xlate, mxs_dma); |
| 801 | if (ret) { |
| 802 | dev_err(mxs_dma->dma_device.dev, |
| 803 | "failed to register controller\n"); |
| 804 | dma_async_device_unregister(&mxs_dma->dma_device); |
| 805 | } |
| 806 | |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 807 | dev_info(mxs_dma->dma_device.dev, "initialized\n"); |
| 808 | |
| 809 | return 0; |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 810 | } |
| 811 | |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 812 | static struct platform_driver mxs_dma_driver = { |
| 813 | .driver = { |
| 814 | .name = "mxs-dma", |
Dong Aisheng | 90c9abc | 2012-05-04 20:12:17 +0800 | [diff] [blame] | 815 | .of_match_table = mxs_dma_dt_ids, |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 816 | }, |
Shawn Guo | 8c92013 | 2012-05-10 06:23:26 +0800 | [diff] [blame] | 817 | .id_table = mxs_dma_ids, |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 818 | }; |
| 819 | |
| 820 | static int __init mxs_dma_module_init(void) |
| 821 | { |
| 822 | return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe); |
| 823 | } |
| 824 | subsys_initcall(mxs_dma_module_init); |