Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | */ |
| 14 | |
| 15 | #define pr_fmt(fmt) "dsi-hw:" fmt |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/iopoll.h> |
| 18 | |
Sandeep Panda | 7945000 | 2017-05-08 17:14:24 +0530 | [diff] [blame] | 19 | #include "dsi_catalog.h" |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 20 | #include "dsi_ctrl_hw.h" |
| 21 | #include "dsi_ctrl_reg.h" |
| 22 | #include "dsi_hw.h" |
Lloyd Atkinson | 16e96de | 2017-04-19 11:18:14 -0400 | [diff] [blame] | 23 | #include "dsi_panel.h" |
Rajkumar Subbiah | 01e6dd64 | 2017-07-05 14:47:47 -0400 | [diff] [blame] | 24 | #include "dsi_catalog.h" |
Raviteja Tamatam | 68892de | 2017-06-20 04:47:19 +0530 | [diff] [blame] | 25 | #include "sde_dbg.h" |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 26 | |
| 27 | #define MMSS_MISC_CLAMP_REG_OFF 0x0014 |
Clarence Ip | 9de0bbc | 2017-03-02 09:56:06 -0500 | [diff] [blame] | 28 | #define DSI_CTRL_DYNAMIC_FORCE_ON (0x23F|BIT(8)|BIT(9)|BIT(11)|BIT(21)) |
Rajkumar Subbiah | 01e6dd64 | 2017-07-05 14:47:47 -0400 | [diff] [blame] | 29 | #define DSI_CTRL_CMD_MISR_ENABLE BIT(28) |
| 30 | #define DSI_CTRL_VIDEO_MISR_ENABLE BIT(16) |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 31 | |
| 32 | /* Unsupported formats default to RGB888 */ |
| 33 | static const u8 cmd_mode_format_map[DSI_PIXEL_FORMAT_MAX] = { |
| 34 | 0x6, 0x7, 0x8, 0x8, 0x0, 0x3, 0x4 }; |
| 35 | static const u8 video_mode_format_map[DSI_PIXEL_FORMAT_MAX] = { |
| 36 | 0x0, 0x1, 0x2, 0x3, 0x3, 0x3, 0x3 }; |
| 37 | |
| 38 | /** |
| 39 | * dsi_setup_trigger_controls() - setup dsi trigger configurations |
| 40 | * @ctrl: Pointer to the controller host hardware. |
| 41 | * @cfg: DSI host configuration that is common to both video and |
| 42 | * command modes. |
| 43 | */ |
| 44 | static void dsi_setup_trigger_controls(struct dsi_ctrl_hw *ctrl, |
| 45 | struct dsi_host_common_cfg *cfg) |
| 46 | { |
| 47 | u32 reg = 0; |
| 48 | const u8 trigger_map[DSI_TRIGGER_MAX] = { |
| 49 | 0x0, 0x2, 0x1, 0x4, 0x5, 0x6 }; |
| 50 | |
| 51 | reg |= (cfg->te_mode == DSI_TE_ON_EXT_PIN) ? BIT(31) : 0; |
| 52 | reg |= (trigger_map[cfg->dma_cmd_trigger] & 0x7); |
| 53 | reg |= (trigger_map[cfg->mdp_cmd_trigger] & 0x7) << 4; |
| 54 | DSI_W32(ctrl, DSI_TRIG_CTRL, reg); |
| 55 | } |
| 56 | |
| 57 | /** |
| 58 | * dsi_ctrl_hw_cmn_host_setup() - setup dsi host configuration |
| 59 | * @ctrl: Pointer to the controller host hardware. |
| 60 | * @cfg: DSI host configuration that is common to both video and |
| 61 | * command modes. |
| 62 | */ |
| 63 | void dsi_ctrl_hw_cmn_host_setup(struct dsi_ctrl_hw *ctrl, |
| 64 | struct dsi_host_common_cfg *cfg) |
| 65 | { |
| 66 | u32 reg_value = 0; |
| 67 | |
| 68 | dsi_setup_trigger_controls(ctrl, cfg); |
| 69 | |
| 70 | /* Setup clocking timing controls */ |
| 71 | reg_value = ((cfg->t_clk_post & 0x3F) << 8); |
| 72 | reg_value |= (cfg->t_clk_pre & 0x3F); |
| 73 | DSI_W32(ctrl, DSI_CLKOUT_TIMING_CTRL, reg_value); |
| 74 | |
| 75 | /* EOT packet control */ |
| 76 | reg_value = cfg->append_tx_eot ? 1 : 0; |
| 77 | reg_value |= (cfg->ignore_rx_eot ? (1 << 4) : 0); |
| 78 | DSI_W32(ctrl, DSI_EOT_PACKET_CTRL, reg_value); |
| 79 | |
| 80 | /* Turn on dsi clocks */ |
| 81 | DSI_W32(ctrl, DSI_CLK_CTRL, 0x23F); |
| 82 | |
| 83 | /* Setup DSI control register */ |
Jeykumar Sankaran | a7c7bbe | 2017-05-31 18:12:05 -0700 | [diff] [blame] | 84 | reg_value = DSI_R32(ctrl, DSI_CTRL); |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 85 | reg_value |= (cfg->en_crc_check ? BIT(24) : 0); |
| 86 | reg_value |= (cfg->en_ecc_check ? BIT(20) : 0); |
| 87 | reg_value |= BIT(8); /* Clock lane */ |
| 88 | reg_value |= ((cfg->data_lanes & DSI_DATA_LANE_3) ? BIT(7) : 0); |
| 89 | reg_value |= ((cfg->data_lanes & DSI_DATA_LANE_2) ? BIT(6) : 0); |
| 90 | reg_value |= ((cfg->data_lanes & DSI_DATA_LANE_1) ? BIT(5) : 0); |
| 91 | reg_value |= ((cfg->data_lanes & DSI_DATA_LANE_0) ? BIT(4) : 0); |
| 92 | |
| 93 | DSI_W32(ctrl, DSI_CTRL, reg_value); |
| 94 | |
Dhaval Patel | abfaa08 | 2017-07-28 12:41:10 -0700 | [diff] [blame] | 95 | if (ctrl->phy_isolation_enabled) |
| 96 | DSI_W32(ctrl, DSI_DEBUG_CTRL, BIT(28)); |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 97 | pr_debug("[DSI_%d]Host configuration complete\n", ctrl->index); |
| 98 | } |
| 99 | |
| 100 | /** |
| 101 | * phy_sw_reset() - perform a soft reset on the PHY. |
| 102 | * @ctrl: Pointer to the controller host hardware. |
| 103 | */ |
| 104 | void dsi_ctrl_hw_cmn_phy_sw_reset(struct dsi_ctrl_hw *ctrl) |
| 105 | { |
Clarence Ip | 9de0bbc | 2017-03-02 09:56:06 -0500 | [diff] [blame] | 106 | DSI_W32(ctrl, DSI_PHY_SW_RESET, BIT(24)|BIT(0)); |
| 107 | wmb(); /* make sure reset is asserted */ |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 108 | udelay(1000); |
| 109 | DSI_W32(ctrl, DSI_PHY_SW_RESET, 0x0); |
Clarence Ip | 9de0bbc | 2017-03-02 09:56:06 -0500 | [diff] [blame] | 110 | wmb(); /* ensure reset is cleared before waiting */ |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 111 | udelay(100); |
| 112 | |
| 113 | pr_debug("[DSI_%d] phy sw reset done\n", ctrl->index); |
| 114 | } |
| 115 | |
| 116 | /** |
| 117 | * soft_reset() - perform a soft reset on DSI controller |
| 118 | * @ctrl: Pointer to the controller host hardware. |
| 119 | * |
Clarence Ip | 9de0bbc | 2017-03-02 09:56:06 -0500 | [diff] [blame] | 120 | * The video, command and controller engines will be disabled before the |
| 121 | * reset is triggered and re-enabled after the reset is complete. |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 122 | * |
| 123 | * If the reset is done while MDP timing engine is turned on, the video |
| 124 | * enigne should be re-enabled only during the vertical blanking time. |
| 125 | */ |
| 126 | void dsi_ctrl_hw_cmn_soft_reset(struct dsi_ctrl_hw *ctrl) |
| 127 | { |
| 128 | u32 reg = 0; |
| 129 | u32 reg_ctrl = 0; |
| 130 | |
| 131 | /* Clear DSI_EN, VIDEO_MODE_EN, CMD_MODE_EN */ |
| 132 | reg_ctrl = DSI_R32(ctrl, DSI_CTRL); |
| 133 | DSI_W32(ctrl, DSI_CTRL, reg_ctrl & ~0x7); |
Clarence Ip | 9de0bbc | 2017-03-02 09:56:06 -0500 | [diff] [blame] | 134 | wmb(); /* wait controller to be disabled before reset */ |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 135 | |
| 136 | /* Force enable PCLK, BYTECLK, AHBM_HCLK */ |
| 137 | reg = DSI_R32(ctrl, DSI_CLK_CTRL); |
Clarence Ip | 9de0bbc | 2017-03-02 09:56:06 -0500 | [diff] [blame] | 138 | DSI_W32(ctrl, DSI_CLK_CTRL, reg | DSI_CTRL_DYNAMIC_FORCE_ON); |
| 139 | wmb(); /* wait for clocks to be enabled */ |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 140 | |
| 141 | /* Trigger soft reset */ |
| 142 | DSI_W32(ctrl, DSI_SOFT_RESET, 0x1); |
Clarence Ip | 9de0bbc | 2017-03-02 09:56:06 -0500 | [diff] [blame] | 143 | wmb(); /* wait for reset to assert before waiting */ |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 144 | udelay(1); |
| 145 | DSI_W32(ctrl, DSI_SOFT_RESET, 0x0); |
Clarence Ip | 9de0bbc | 2017-03-02 09:56:06 -0500 | [diff] [blame] | 146 | wmb(); /* ensure reset is cleared */ |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 147 | |
| 148 | /* Disable force clock on */ |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 149 | DSI_W32(ctrl, DSI_CLK_CTRL, reg); |
Clarence Ip | 9de0bbc | 2017-03-02 09:56:06 -0500 | [diff] [blame] | 150 | wmb(); /* make sure clocks are restored */ |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 151 | |
| 152 | /* Re-enable DSI controller */ |
| 153 | DSI_W32(ctrl, DSI_CTRL, reg_ctrl); |
Clarence Ip | 9de0bbc | 2017-03-02 09:56:06 -0500 | [diff] [blame] | 154 | wmb(); /* make sure DSI controller is enabled again */ |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 155 | pr_debug("[DSI_%d] ctrl soft reset done\n", ctrl->index); |
| 156 | } |
| 157 | |
| 158 | /** |
Rajkumar Subbiah | 01e6dd64 | 2017-07-05 14:47:47 -0400 | [diff] [blame] | 159 | * setup_misr() - Setup frame MISR |
| 160 | * @ctrl: Pointer to the controller host hardware. |
| 161 | * @panel_mode: CMD or VIDEO mode indicator |
| 162 | * @enable: Enable/disable MISR. |
| 163 | * @frame_count: Number of frames to accumulate MISR. |
| 164 | */ |
| 165 | void dsi_ctrl_hw_cmn_setup_misr(struct dsi_ctrl_hw *ctrl, |
| 166 | enum dsi_op_mode panel_mode, |
| 167 | bool enable, |
| 168 | u32 frame_count) |
| 169 | { |
| 170 | u32 addr; |
| 171 | u32 config = 0; |
| 172 | |
| 173 | if (panel_mode == DSI_OP_CMD_MODE) { |
| 174 | addr = DSI_MISR_CMD_CTRL; |
| 175 | if (enable) |
| 176 | config = DSI_CTRL_CMD_MISR_ENABLE; |
| 177 | } else { |
| 178 | addr = DSI_MISR_VIDEO_CTRL; |
| 179 | if (enable) |
| 180 | config = DSI_CTRL_VIDEO_MISR_ENABLE; |
| 181 | if (frame_count > 255) |
| 182 | frame_count = 255; |
| 183 | config |= frame_count << 8; |
| 184 | } |
| 185 | |
| 186 | pr_debug("[DSI_%d] MISR ctrl: 0x%x\n", ctrl->index, |
| 187 | config); |
| 188 | DSI_W32(ctrl, addr, config); |
| 189 | wmb(); /* make sure MISR is configured */ |
| 190 | } |
| 191 | |
| 192 | /** |
| 193 | * collect_misr() - Read frame MISR |
| 194 | * @ctrl: Pointer to the controller host hardware. |
| 195 | * @panel_mode: CMD or VIDEO mode indicator |
| 196 | */ |
| 197 | u32 dsi_ctrl_hw_cmn_collect_misr(struct dsi_ctrl_hw *ctrl, |
| 198 | enum dsi_op_mode panel_mode) |
| 199 | { |
| 200 | u32 addr; |
| 201 | u32 enabled; |
| 202 | u32 misr = 0; |
| 203 | |
| 204 | if (panel_mode == DSI_OP_CMD_MODE) { |
| 205 | addr = DSI_MISR_CMD_MDP0_32BIT; |
| 206 | enabled = DSI_R32(ctrl, DSI_MISR_CMD_CTRL) & |
| 207 | DSI_CTRL_CMD_MISR_ENABLE; |
| 208 | } else { |
| 209 | addr = DSI_MISR_VIDEO_32BIT; |
| 210 | enabled = DSI_R32(ctrl, DSI_MISR_VIDEO_CTRL) & |
| 211 | DSI_CTRL_VIDEO_MISR_ENABLE; |
| 212 | } |
| 213 | |
| 214 | if (enabled) |
| 215 | misr = DSI_R32(ctrl, addr); |
| 216 | |
| 217 | pr_debug("[DSI_%d] MISR enabled %x value: 0x%x\n", ctrl->index, |
| 218 | enabled, misr); |
| 219 | return misr; |
| 220 | } |
| 221 | |
| 222 | /** |
Raviteja Tamatam | 68892de | 2017-06-20 04:47:19 +0530 | [diff] [blame] | 223 | * set_timing_db() - enable/disable Timing DB register |
| 224 | * @ctrl: Pointer to controller host hardware. |
| 225 | * @enable: Enable/Disable flag. |
| 226 | * |
| 227 | * Enable or Disabe the Timing DB register. |
| 228 | */ |
| 229 | void dsi_ctrl_hw_cmn_set_timing_db(struct dsi_ctrl_hw *ctrl, |
| 230 | bool enable) |
| 231 | { |
| 232 | if (enable) |
| 233 | DSI_W32(ctrl, DSI_DSI_TIMING_DB_MODE, 0x1); |
| 234 | else |
| 235 | DSI_W32(ctrl, DSI_DSI_TIMING_DB_MODE, 0x0); |
| 236 | |
| 237 | wmb(); /* make sure timing db registers are set */ |
| 238 | pr_debug("[DSI_%d] ctrl timing DB set:%d\n", ctrl->index, |
| 239 | enable); |
| 240 | SDE_EVT32(ctrl->index, enable); |
| 241 | } |
| 242 | |
| 243 | /** |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 244 | * set_video_timing() - set up the timing for video frame |
| 245 | * @ctrl: Pointer to controller host hardware. |
| 246 | * @mode: Video mode information. |
| 247 | * |
| 248 | * Set up the video timing parameters for the DSI video mode operation. |
| 249 | */ |
| 250 | void dsi_ctrl_hw_cmn_set_video_timing(struct dsi_ctrl_hw *ctrl, |
| 251 | struct dsi_mode_info *mode) |
| 252 | { |
| 253 | u32 reg = 0; |
| 254 | u32 hs_start = 0; |
Alexander Beykun | ac18235 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 255 | u32 hs_end, active_h_start, active_h_end, h_total, width = 0; |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 256 | u32 vs_start = 0, vs_end = 0; |
| 257 | u32 vpos_start = 0, vpos_end, active_v_start, active_v_end, v_total; |
| 258 | |
Alexander Beykun | ac18235 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 259 | if (mode->dsc_enabled && mode->dsc) { |
| 260 | width = mode->dsc->pclk_per_line; |
| 261 | reg = mode->dsc->bytes_per_pkt << 16; |
| 262 | reg |= (0x0b << 8); /* dtype of compressed image */ |
| 263 | /* |
| 264 | * pkt_per_line: |
| 265 | * 0 == 1 pkt |
| 266 | * 1 == 2 pkt |
| 267 | * 2 == 4 pkt |
| 268 | * 3 pkt is not support |
| 269 | */ |
| 270 | if (mode->dsc->pkt_per_line == 4) |
| 271 | reg |= (mode->dsc->pkt_per_line - 2) << 6; |
| 272 | else |
| 273 | reg |= (mode->dsc->pkt_per_line - 1) << 6; |
| 274 | reg |= mode->dsc->eol_byte_num << 4; |
| 275 | reg |= 1; |
| 276 | DSI_W32(ctrl, DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); |
| 277 | } else { |
| 278 | width = mode->h_active; |
| 279 | } |
| 280 | |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 281 | hs_end = mode->h_sync_width; |
| 282 | active_h_start = mode->h_sync_width + mode->h_back_porch; |
Alexander Beykun | ac18235 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 283 | active_h_end = active_h_start + width; |
| 284 | h_total = (mode->h_sync_width + mode->h_back_porch + width + |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 285 | mode->h_front_porch) - 1; |
| 286 | |
| 287 | vpos_end = mode->v_sync_width; |
| 288 | active_v_start = mode->v_sync_width + mode->v_back_porch; |
| 289 | active_v_end = active_v_start + mode->v_active; |
| 290 | v_total = (mode->v_sync_width + mode->v_back_porch + mode->v_active + |
| 291 | mode->v_front_porch) - 1; |
| 292 | |
| 293 | reg = ((active_h_end & 0xFFFF) << 16) | (active_h_start & 0xFFFF); |
| 294 | DSI_W32(ctrl, DSI_VIDEO_MODE_ACTIVE_H, reg); |
| 295 | |
| 296 | reg = ((active_v_end & 0xFFFF) << 16) | (active_v_start & 0xFFFF); |
| 297 | DSI_W32(ctrl, DSI_VIDEO_MODE_ACTIVE_V, reg); |
| 298 | |
| 299 | reg = ((v_total & 0xFFFF) << 16) | (h_total & 0xFFFF); |
| 300 | DSI_W32(ctrl, DSI_VIDEO_MODE_TOTAL, reg); |
| 301 | |
| 302 | reg = ((hs_end & 0xFFFF) << 16) | (hs_start & 0xFFFF); |
| 303 | DSI_W32(ctrl, DSI_VIDEO_MODE_HSYNC, reg); |
| 304 | |
| 305 | reg = ((vs_end & 0xFFFF) << 16) | (vs_start & 0xFFFF); |
| 306 | DSI_W32(ctrl, DSI_VIDEO_MODE_VSYNC, reg); |
| 307 | |
| 308 | reg = ((vpos_end & 0xFFFF) << 16) | (vpos_start & 0xFFFF); |
| 309 | DSI_W32(ctrl, DSI_VIDEO_MODE_VSYNC_VPOS, reg); |
| 310 | |
| 311 | /* TODO: HS TIMER value? */ |
| 312 | DSI_W32(ctrl, DSI_HS_TIMER_CTRL, 0x3FD08); |
| 313 | DSI_W32(ctrl, DSI_MISR_VIDEO_CTRL, 0x10100); |
| 314 | DSI_W32(ctrl, DSI_DSI_TIMING_FLUSH, 0x1); |
| 315 | pr_debug("[DSI_%d] ctrl video parameters updated\n", ctrl->index); |
Raviteja Tamatam | 68892de | 2017-06-20 04:47:19 +0530 | [diff] [blame] | 316 | SDE_EVT32(v_total, h_total); |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 317 | } |
| 318 | |
| 319 | /** |
| 320 | * setup_cmd_stream() - set up parameters for command pixel streams |
Alexander Beykun | ac18235 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 321 | * @ctrl: Pointer to controller host hardware. |
| 322 | * @mode: Pointer to mode information. |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 323 | * @h_stride: Horizontal stride in bytes. |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 324 | * @vc_id: stream_id |
| 325 | * |
| 326 | * Setup parameters for command mode pixel stream size. |
| 327 | */ |
| 328 | void dsi_ctrl_hw_cmn_setup_cmd_stream(struct dsi_ctrl_hw *ctrl, |
Alexander Beykun | ac18235 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 329 | struct dsi_mode_info *mode, |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 330 | u32 h_stride, |
Lloyd Atkinson | 16e96de | 2017-04-19 11:18:14 -0400 | [diff] [blame] | 331 | u32 vc_id, |
| 332 | struct dsi_rect *roi) |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 333 | { |
Alexander Beykun | ac18235 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 334 | u32 width_final, stride_final; |
Lloyd Atkinson | 16e96de | 2017-04-19 11:18:14 -0400 | [diff] [blame] | 335 | u32 height_final; |
| 336 | u32 stream_total = 0, stream_ctrl = 0; |
Sravanthi Kollukuduru | d880932 | 2017-10-26 15:24:13 +0530 | [diff] [blame] | 337 | u32 reg_ctrl = 0, reg_ctrl2 = 0, data = 0; |
Lloyd Atkinson | 16e96de | 2017-04-19 11:18:14 -0400 | [diff] [blame] | 338 | |
| 339 | if (roi && (!roi->w || !roi->h)) |
| 340 | return; |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 341 | |
Alexander Beykun | ac18235 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 342 | if (mode->dsc_enabled && mode->dsc) { |
Lloyd Atkinson | 16e96de | 2017-04-19 11:18:14 -0400 | [diff] [blame] | 343 | u32 reg = 0; |
Alexander Beykun | ac18235 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 344 | u32 offset = 0; |
Lloyd Atkinson | 16e96de | 2017-04-19 11:18:14 -0400 | [diff] [blame] | 345 | int pic_width, this_frame_slices, intf_ip_w; |
| 346 | struct msm_display_dsc_info dsc; |
| 347 | |
| 348 | memcpy(&dsc, mode->dsc, sizeof(dsc)); |
| 349 | pic_width = roi ? roi->w : mode->h_active; |
| 350 | this_frame_slices = pic_width / dsc.slice_width; |
| 351 | intf_ip_w = this_frame_slices * dsc.slice_width; |
| 352 | dsi_dsc_pclk_param_calc(&dsc, intf_ip_w); |
Alexander Beykun | ac18235 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 353 | |
| 354 | if (vc_id != 0) |
| 355 | offset = 16; |
| 356 | reg_ctrl = DSI_R32(ctrl, DSI_COMMAND_COMPRESSION_MODE_CTRL); |
| 357 | reg_ctrl2 = DSI_R32(ctrl, DSI_COMMAND_COMPRESSION_MODE_CTRL2); |
Lloyd Atkinson | 16e96de | 2017-04-19 11:18:14 -0400 | [diff] [blame] | 358 | width_final = dsc.pclk_per_line; |
| 359 | stride_final = dsc.bytes_per_pkt; |
| 360 | height_final = roi ? roi->h : mode->v_active; |
Alexander Beykun | ac18235 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 361 | |
| 362 | reg = 0x39 << 8; |
| 363 | /* |
| 364 | * pkt_per_line: |
| 365 | * 0 == 1 pkt |
| 366 | * 1 == 2 pkt |
| 367 | * 2 == 4 pkt |
| 368 | * 3 pkt is not support |
| 369 | */ |
Lloyd Atkinson | 16e96de | 2017-04-19 11:18:14 -0400 | [diff] [blame] | 370 | if (dsc.pkt_per_line == 4) |
| 371 | reg |= (dsc.pkt_per_line - 2) << 6; |
Alexander Beykun | ac18235 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 372 | else |
Lloyd Atkinson | 16e96de | 2017-04-19 11:18:14 -0400 | [diff] [blame] | 373 | reg |= (dsc.pkt_per_line - 1) << 6; |
| 374 | reg |= dsc.eol_byte_num << 4; |
Alexander Beykun | ac18235 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 375 | reg |= 1; |
| 376 | |
| 377 | reg_ctrl &= ~(0xFFFF << offset); |
| 378 | reg_ctrl |= (reg << offset); |
| 379 | reg_ctrl2 &= ~(0xFFFF << offset); |
Lloyd Atkinson | 16e96de | 2017-04-19 11:18:14 -0400 | [diff] [blame] | 380 | reg_ctrl2 |= (dsc.bytes_in_slice << offset); |
Lloyd Atkinson | 16e96de | 2017-04-19 11:18:14 -0400 | [diff] [blame] | 381 | |
| 382 | pr_debug("ctrl %d reg_ctrl 0x%x reg_ctrl2 0x%x\n", ctrl->index, |
| 383 | reg_ctrl, reg_ctrl2); |
| 384 | } else if (roi) { |
| 385 | width_final = roi->w; |
| 386 | stride_final = roi->w * 3; |
| 387 | height_final = roi->h; |
Alexander Beykun | ac18235 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 388 | } else { |
| 389 | width_final = mode->h_active; |
| 390 | stride_final = h_stride; |
Lloyd Atkinson | 16e96de | 2017-04-19 11:18:14 -0400 | [diff] [blame] | 391 | height_final = mode->v_active; |
Alexander Beykun | ac18235 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 392 | } |
| 393 | |
Sandeep Panda | 11b20d8 | 2017-06-19 12:57:27 +0530 | [diff] [blame] | 394 | /* HS Timer value */ |
| 395 | DSI_W32(ctrl, DSI_HS_TIMER_CTRL, 0x3FD08); |
| 396 | |
Lloyd Atkinson | 16e96de | 2017-04-19 11:18:14 -0400 | [diff] [blame] | 397 | stream_ctrl = (stride_final + 1) << 16; |
| 398 | stream_ctrl |= (vc_id & 0x3) << 8; |
| 399 | stream_ctrl |= 0x39; /* packet data type */ |
Alexander Beykun | ac18235 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 400 | |
Ingrid Gallardo | 2a2befb | 2017-08-07 15:02:51 -0700 | [diff] [blame] | 401 | DSI_W32(ctrl, DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl); |
| 402 | DSI_W32(ctrl, DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); |
| 403 | |
Lloyd Atkinson | 16e96de | 2017-04-19 11:18:14 -0400 | [diff] [blame] | 404 | DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_STREAM0_CTRL, stream_ctrl); |
| 405 | DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_STREAM1_CTRL, stream_ctrl); |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 406 | |
Lloyd Atkinson | 16e96de | 2017-04-19 11:18:14 -0400 | [diff] [blame] | 407 | stream_total = (height_final << 16) | width_final; |
| 408 | DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_STREAM0_TOTAL, stream_total); |
| 409 | DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_STREAM1_TOTAL, stream_total); |
| 410 | |
Sravanthi Kollukuduru | d880932 | 2017-10-26 15:24:13 +0530 | [diff] [blame] | 411 | if (ctrl->null_insertion_enabled) { |
| 412 | /* enable null packet insertion */ |
| 413 | data = (vc_id << 1); |
| 414 | data |= 0 << 16; |
| 415 | data |= 0x1; |
| 416 | DSI_W32(ctrl, DSI_COMMAND_MODE_NULL_INSERTION_CTRL, data); |
| 417 | } |
| 418 | |
Lloyd Atkinson | 16e96de | 2017-04-19 11:18:14 -0400 | [diff] [blame] | 419 | pr_debug("ctrl %d stream_ctrl 0x%x stream_total 0x%x\n", ctrl->index, |
| 420 | stream_ctrl, stream_total); |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 421 | } |
| 422 | |
| 423 | /** |
| 424 | * video_engine_setup() - Setup dsi host controller for video mode |
| 425 | * @ctrl: Pointer to controller host hardware. |
| 426 | * @common_cfg: Common configuration parameters. |
| 427 | * @cfg: Video mode configuration. |
| 428 | * |
| 429 | * Set up DSI video engine with a specific configuration. Controller and |
| 430 | * video engine are not enabled as part of this function. |
| 431 | */ |
| 432 | void dsi_ctrl_hw_cmn_video_engine_setup(struct dsi_ctrl_hw *ctrl, |
| 433 | struct dsi_host_common_cfg *common_cfg, |
| 434 | struct dsi_video_engine_cfg *cfg) |
| 435 | { |
| 436 | u32 reg = 0; |
| 437 | |
| 438 | reg |= (cfg->last_line_interleave_en ? BIT(31) : 0); |
| 439 | reg |= (cfg->pulse_mode_hsa_he ? BIT(28) : 0); |
| 440 | reg |= (cfg->hfp_lp11_en ? BIT(24) : 0); |
| 441 | reg |= (cfg->hbp_lp11_en ? BIT(20) : 0); |
| 442 | reg |= (cfg->hsa_lp11_en ? BIT(16) : 0); |
| 443 | reg |= (cfg->eof_bllp_lp11_en ? BIT(15) : 0); |
| 444 | reg |= (cfg->bllp_lp11_en ? BIT(12) : 0); |
| 445 | reg |= (cfg->traffic_mode & 0x3) << 8; |
| 446 | reg |= (cfg->vc_id & 0x3); |
| 447 | reg |= (video_mode_format_map[common_cfg->dst_format] & 0x3) << 4; |
| 448 | DSI_W32(ctrl, DSI_VIDEO_MODE_CTRL, reg); |
| 449 | |
| 450 | reg = (common_cfg->swap_mode & 0x7) << 12; |
| 451 | reg |= (common_cfg->bit_swap_red ? BIT(0) : 0); |
| 452 | reg |= (common_cfg->bit_swap_green ? BIT(4) : 0); |
| 453 | reg |= (common_cfg->bit_swap_blue ? BIT(8) : 0); |
| 454 | DSI_W32(ctrl, DSI_VIDEO_MODE_DATA_CTRL, reg); |
Shashank Babu Chinta Venkata | 2f24e98 | 2017-04-21 14:57:53 -0700 | [diff] [blame] | 455 | /* Disable Timing double buffering */ |
| 456 | DSI_W32(ctrl, DSI_DSI_TIMING_DB_MODE, 0x0); |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 457 | |
| 458 | |
| 459 | pr_debug("[DSI_%d] Video engine setup done\n", ctrl->index); |
| 460 | } |
| 461 | |
Dhaval Patel | f9f3ffe | 2017-08-16 16:03:10 -0700 | [diff] [blame] | 462 | void dsi_ctrl_hw_cmn_debug_bus(struct dsi_ctrl_hw *ctrl) |
| 463 | { |
| 464 | u32 reg = 0; |
| 465 | |
| 466 | DSI_W32(ctrl, DSI_DEBUG_BUS_CTL, 0x181); |
| 467 | |
| 468 | /* make sure that debug test point is enabled */ |
| 469 | wmb(); |
| 470 | reg = DSI_R32(ctrl, DSI_DEBUG_BUS_STATUS); |
| 471 | |
| 472 | pr_err("[DSI_%d] debug bus status:0x%x\n", ctrl->index, reg); |
| 473 | } |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 474 | /** |
| 475 | * cmd_engine_setup() - setup dsi host controller for command mode |
| 476 | * @ctrl: Pointer to the controller host hardware. |
| 477 | * @common_cfg: Common configuration parameters. |
| 478 | * @cfg: Command mode configuration. |
| 479 | * |
| 480 | * Setup DSI CMD engine with a specific configuration. Controller and |
| 481 | * command engine are not enabled as part of this function. |
| 482 | */ |
| 483 | void dsi_ctrl_hw_cmn_cmd_engine_setup(struct dsi_ctrl_hw *ctrl, |
| 484 | struct dsi_host_common_cfg *common_cfg, |
| 485 | struct dsi_cmd_engine_cfg *cfg) |
| 486 | { |
| 487 | u32 reg = 0; |
| 488 | |
| 489 | reg = (cfg->max_cmd_packets_interleave & 0xF) << 20; |
| 490 | reg |= (common_cfg->bit_swap_red ? BIT(4) : 0); |
| 491 | reg |= (common_cfg->bit_swap_green ? BIT(8) : 0); |
| 492 | reg |= (common_cfg->bit_swap_blue ? BIT(12) : 0); |
| 493 | reg |= cmd_mode_format_map[common_cfg->dst_format]; |
| 494 | DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_CTRL, reg); |
| 495 | |
| 496 | reg = DSI_R32(ctrl, DSI_COMMAND_MODE_MDP_CTRL2); |
| 497 | reg |= BIT(16); |
| 498 | DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_CTRL2, reg); |
| 499 | |
| 500 | reg = cfg->wr_mem_start & 0xFF; |
| 501 | reg |= (cfg->wr_mem_continue & 0xFF) << 8; |
| 502 | reg |= (cfg->insert_dcs_command ? BIT(16) : 0); |
| 503 | DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL, reg); |
| 504 | |
| 505 | pr_debug("[DSI_%d] Cmd engine setup done\n", ctrl->index); |
| 506 | } |
| 507 | |
| 508 | /** |
| 509 | * video_engine_en() - enable DSI video engine |
| 510 | * @ctrl: Pointer to controller host hardware. |
| 511 | * @on: Enable/disabel video engine. |
| 512 | */ |
| 513 | void dsi_ctrl_hw_cmn_video_engine_en(struct dsi_ctrl_hw *ctrl, bool on) |
| 514 | { |
| 515 | u32 reg = 0; |
| 516 | |
| 517 | /* Set/Clear VIDEO_MODE_EN bit */ |
| 518 | reg = DSI_R32(ctrl, DSI_CTRL); |
| 519 | if (on) |
| 520 | reg |= BIT(1); |
| 521 | else |
| 522 | reg &= ~BIT(1); |
| 523 | |
| 524 | DSI_W32(ctrl, DSI_CTRL, reg); |
| 525 | |
| 526 | pr_debug("[DSI_%d] Video engine = %d\n", ctrl->index, on); |
| 527 | } |
| 528 | |
| 529 | /** |
| 530 | * ctrl_en() - enable DSI controller engine |
| 531 | * @ctrl: Pointer to the controller host hardware. |
| 532 | * @on: turn on/off the DSI controller engine. |
| 533 | */ |
| 534 | void dsi_ctrl_hw_cmn_ctrl_en(struct dsi_ctrl_hw *ctrl, bool on) |
| 535 | { |
| 536 | u32 reg = 0; |
Clarence Ip | 9de0bbc | 2017-03-02 09:56:06 -0500 | [diff] [blame] | 537 | u32 clk_ctrl; |
| 538 | |
| 539 | clk_ctrl = DSI_R32(ctrl, DSI_CLK_CTRL); |
| 540 | DSI_W32(ctrl, DSI_CLK_CTRL, clk_ctrl | DSI_CTRL_DYNAMIC_FORCE_ON); |
| 541 | wmb(); /* wait for clocks to enable */ |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 542 | |
| 543 | /* Set/Clear DSI_EN bit */ |
| 544 | reg = DSI_R32(ctrl, DSI_CTRL); |
| 545 | if (on) |
| 546 | reg |= BIT(0); |
| 547 | else |
| 548 | reg &= ~BIT(0); |
| 549 | |
| 550 | DSI_W32(ctrl, DSI_CTRL, reg); |
Clarence Ip | 9de0bbc | 2017-03-02 09:56:06 -0500 | [diff] [blame] | 551 | wmb(); /* wait for DSI_EN update before disabling clocks */ |
| 552 | |
| 553 | DSI_W32(ctrl, DSI_CLK_CTRL, clk_ctrl); |
| 554 | wmb(); /* make sure clocks are restored */ |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 555 | |
| 556 | pr_debug("[DSI_%d] Controller engine = %d\n", ctrl->index, on); |
| 557 | } |
| 558 | |
| 559 | /** |
| 560 | * cmd_engine_en() - enable DSI controller command engine |
| 561 | * @ctrl: Pointer to the controller host hardware. |
| 562 | * @on: Turn on/off the DSI command engine. |
| 563 | */ |
| 564 | void dsi_ctrl_hw_cmn_cmd_engine_en(struct dsi_ctrl_hw *ctrl, bool on) |
| 565 | { |
| 566 | u32 reg = 0; |
| 567 | |
| 568 | /* Set/Clear CMD_MODE_EN bit */ |
| 569 | reg = DSI_R32(ctrl, DSI_CTRL); |
| 570 | if (on) |
| 571 | reg |= BIT(2); |
| 572 | else |
| 573 | reg &= ~BIT(2); |
| 574 | |
| 575 | DSI_W32(ctrl, DSI_CTRL, reg); |
| 576 | |
| 577 | pr_debug("[DSI_%d] command engine = %d\n", ctrl->index, on); |
| 578 | } |
| 579 | |
| 580 | /** |
| 581 | * kickoff_command() - transmits commands stored in memory |
| 582 | * @ctrl: Pointer to the controller host hardware. |
| 583 | * @cmd: Command information. |
| 584 | * @flags: Modifiers for command transmission. |
| 585 | * |
| 586 | * The controller hardware is programmed with address and size of the |
| 587 | * command buffer. The transmission is kicked off if |
| 588 | * DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER flag is not set. If this flag is |
| 589 | * set, caller should make a separate call to trigger_command_dma() to |
| 590 | * transmit the command. |
| 591 | */ |
| 592 | void dsi_ctrl_hw_cmn_kickoff_command(struct dsi_ctrl_hw *ctrl, |
| 593 | struct dsi_ctrl_cmd_dma_info *cmd, |
| 594 | u32 flags) |
| 595 | { |
| 596 | u32 reg = 0; |
| 597 | |
| 598 | /*Set BROADCAST_EN and EMBEDDED_MODE */ |
| 599 | reg = DSI_R32(ctrl, DSI_COMMAND_MODE_DMA_CTRL); |
| 600 | if (cmd->en_broadcast) |
| 601 | reg |= BIT(31); |
| 602 | else |
| 603 | reg &= ~BIT(31); |
| 604 | |
| 605 | if (cmd->is_master) |
| 606 | reg |= BIT(30); |
| 607 | else |
| 608 | reg &= ~BIT(30); |
| 609 | |
| 610 | if (cmd->use_lpm) |
| 611 | reg |= BIT(26); |
| 612 | else |
| 613 | reg &= ~BIT(26); |
| 614 | |
| 615 | reg |= BIT(28); |
| 616 | DSI_W32(ctrl, DSI_COMMAND_MODE_DMA_CTRL, reg); |
| 617 | |
| 618 | DSI_W32(ctrl, DSI_DMA_CMD_OFFSET, cmd->offset); |
| 619 | DSI_W32(ctrl, DSI_DMA_CMD_LENGTH, (cmd->length & 0xFFFFFF)); |
| 620 | |
| 621 | /* wait for writes to complete before kick off */ |
| 622 | wmb(); |
| 623 | |
| 624 | if (!(flags & DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER)) |
| 625 | DSI_W32(ctrl, DSI_CMD_MODE_DMA_SW_TRIGGER, 0x1); |
| 626 | } |
| 627 | |
| 628 | /** |
| 629 | * kickoff_fifo_command() - transmits a command using FIFO in dsi |
| 630 | * hardware. |
| 631 | * @ctrl: Pointer to the controller host hardware. |
| 632 | * @cmd: Command information. |
| 633 | * @flags: Modifiers for command transmission. |
| 634 | * |
| 635 | * The controller hardware FIFO is programmed with command header and |
| 636 | * payload. The transmission is kicked off if |
| 637 | * DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER flag is not set. If this flag is |
| 638 | * set, caller should make a separate call to trigger_command_dma() to |
| 639 | * transmit the command. |
| 640 | */ |
| 641 | void dsi_ctrl_hw_cmn_kickoff_fifo_command(struct dsi_ctrl_hw *ctrl, |
| 642 | struct dsi_ctrl_cmd_dma_fifo_info *cmd, |
| 643 | u32 flags) |
| 644 | { |
| 645 | u32 reg = 0, i = 0; |
| 646 | u32 *ptr = cmd->command; |
| 647 | /* |
| 648 | * Set CMD_DMA_TPG_EN, TPG_DMA_FIFO_MODE and |
| 649 | * CMD_DMA_PATTERN_SEL = custom pattern stored in TPG DMA FIFO |
| 650 | */ |
| 651 | reg = (BIT(1) | BIT(2) | (0x3 << 16)); |
| 652 | DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CTRL, reg); |
| 653 | |
| 654 | /* |
| 655 | * Program the FIFO with command buffer. Hardware requires an extra |
| 656 | * DWORD (set to zero) if the length of command buffer is odd DWORDS. |
| 657 | */ |
| 658 | for (i = 0; i < cmd->size; i += 4) { |
| 659 | DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CMD_DMA_INIT_VAL, *ptr); |
| 660 | ptr++; |
| 661 | } |
| 662 | |
| 663 | if ((cmd->size / 4) & 0x1) |
| 664 | DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CMD_DMA_INIT_VAL, 0); |
| 665 | |
| 666 | /*Set BROADCAST_EN and EMBEDDED_MODE */ |
| 667 | reg = DSI_R32(ctrl, DSI_COMMAND_MODE_DMA_CTRL); |
| 668 | if (cmd->en_broadcast) |
| 669 | reg |= BIT(31); |
| 670 | else |
| 671 | reg &= ~BIT(31); |
| 672 | |
| 673 | if (cmd->is_master) |
| 674 | reg |= BIT(30); |
| 675 | else |
| 676 | reg &= ~BIT(30); |
| 677 | |
| 678 | if (cmd->use_lpm) |
| 679 | reg |= BIT(26); |
| 680 | else |
| 681 | reg &= ~BIT(26); |
| 682 | |
| 683 | reg |= BIT(28); |
| 684 | |
| 685 | DSI_W32(ctrl, DSI_COMMAND_MODE_DMA_CTRL, reg); |
| 686 | |
| 687 | DSI_W32(ctrl, DSI_DMA_CMD_LENGTH, (cmd->size & 0xFFFFFFFF)); |
| 688 | /* Finish writes before command trigger */ |
| 689 | wmb(); |
| 690 | |
| 691 | if (!(flags & DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER)) |
| 692 | DSI_W32(ctrl, DSI_CMD_MODE_DMA_SW_TRIGGER, 0x1); |
| 693 | |
| 694 | pr_debug("[DSI_%d]size=%d, trigger = %d\n", |
| 695 | ctrl->index, cmd->size, |
| 696 | (flags & DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER) ? false : true); |
| 697 | } |
| 698 | |
| 699 | void dsi_ctrl_hw_cmn_reset_cmd_fifo(struct dsi_ctrl_hw *ctrl) |
| 700 | { |
| 701 | /* disable cmd dma tpg */ |
| 702 | DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CTRL, 0x0); |
| 703 | |
| 704 | DSI_W32(ctrl, DSI_TPG_DMA_FIFO_RESET, 0x1); |
| 705 | udelay(1); |
| 706 | DSI_W32(ctrl, DSI_TPG_DMA_FIFO_RESET, 0x0); |
| 707 | } |
| 708 | |
| 709 | /** |
| 710 | * trigger_command_dma() - trigger transmission of command buffer. |
| 711 | * @ctrl: Pointer to the controller host hardware. |
| 712 | * |
| 713 | * This trigger can be only used if there was a prior call to |
| 714 | * kickoff_command() of kickoff_fifo_command() with |
| 715 | * DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER flag. |
| 716 | */ |
| 717 | void dsi_ctrl_hw_cmn_trigger_command_dma(struct dsi_ctrl_hw *ctrl) |
| 718 | { |
| 719 | DSI_W32(ctrl, DSI_CMD_MODE_DMA_SW_TRIGGER, 0x1); |
| 720 | pr_debug("[DSI_%d] CMD DMA triggered\n", ctrl->index); |
| 721 | } |
| 722 | |
| 723 | /** |
Sandeep Panda | 7945000 | 2017-05-08 17:14:24 +0530 | [diff] [blame] | 724 | * clear_rdbk_reg() - clear previously read panel data. |
| 725 | * @ctrl: Pointer to the controller host hardware. |
| 726 | * |
| 727 | * This function is called before sending DSI Rx command to |
| 728 | * panel in order to clear if any stale data remaining from |
| 729 | * previous read operation. |
| 730 | */ |
| 731 | void dsi_ctrl_hw_cmn_clear_rdbk_reg(struct dsi_ctrl_hw *ctrl) |
| 732 | { |
| 733 | DSI_W32(ctrl, DSI_RDBK_DATA_CTRL, 0x1); |
| 734 | wmb(); /* ensure read back register is reset */ |
| 735 | DSI_W32(ctrl, DSI_RDBK_DATA_CTRL, 0x0); |
| 736 | wmb(); /* ensure read back register is cleared */ |
| 737 | } |
| 738 | |
| 739 | /** |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 740 | * get_cmd_read_data() - get data read from the peripheral |
| 741 | * @ctrl: Pointer to the controller host hardware. |
| 742 | * @rd_buf: Buffer where data will be read into. |
| 743 | * @total_read_len: Number of bytes to read. |
| 744 | * |
| 745 | * return: number of bytes read. |
| 746 | */ |
| 747 | u32 dsi_ctrl_hw_cmn_get_cmd_read_data(struct dsi_ctrl_hw *ctrl, |
| 748 | u8 *rd_buf, |
| 749 | u32 read_offset, |
Sandeep Panda | 7945000 | 2017-05-08 17:14:24 +0530 | [diff] [blame] | 750 | u32 rx_byte, |
| 751 | u32 pkt_size, |
| 752 | u32 *hw_read_cnt) |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 753 | { |
| 754 | u32 *lp, *temp, data; |
Sandeep Panda | 7945000 | 2017-05-08 17:14:24 +0530 | [diff] [blame] | 755 | int i, j = 0, cnt, off; |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 756 | u32 read_cnt; |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 757 | u32 repeated_bytes = 0; |
| 758 | u8 reg[16] = {0}; |
Sandeep Panda | 7945000 | 2017-05-08 17:14:24 +0530 | [diff] [blame] | 759 | bool ack_err = false; |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 760 | |
| 761 | lp = (u32 *)rd_buf; |
| 762 | temp = (u32 *)reg; |
| 763 | cnt = (rx_byte + 3) >> 2; |
| 764 | |
| 765 | if (cnt > 4) |
| 766 | cnt = 4; |
| 767 | |
Sandeep Panda | 7945000 | 2017-05-08 17:14:24 +0530 | [diff] [blame] | 768 | read_cnt = (DSI_R32(ctrl, DSI_RDBK_DATA_CTRL) >> 16); |
| 769 | ack_err = (rx_byte == 4) ? (read_cnt == 8) : |
| 770 | ((read_cnt - 4) == (pkt_size + 6)); |
| 771 | |
| 772 | if (ack_err) |
| 773 | read_cnt -= 4; |
| 774 | if (!read_cnt) { |
| 775 | pr_err("Panel detected error, no data read\n"); |
| 776 | return 0; |
| 777 | } |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 778 | |
| 779 | if (read_cnt > 16) { |
Sandeep Panda | 7945000 | 2017-05-08 17:14:24 +0530 | [diff] [blame] | 780 | int bytes_shifted, data_lost = 0, rem_header = 0; |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 781 | |
Sandeep Panda | 7945000 | 2017-05-08 17:14:24 +0530 | [diff] [blame] | 782 | bytes_shifted = read_cnt - rx_byte; |
| 783 | if (bytes_shifted >= 4) |
| 784 | data_lost = bytes_shifted - 4; /* remove DCS header */ |
| 785 | else |
| 786 | rem_header = 4 - bytes_shifted; /* remaining header */ |
| 787 | |
| 788 | repeated_bytes = (read_offset - 4) - data_lost + rem_header; |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 789 | } |
| 790 | |
Sandeep Panda | 7945000 | 2017-05-08 17:14:24 +0530 | [diff] [blame] | 791 | off = DSI_RDBK_DATA0; |
| 792 | off += ((cnt - 1) * 4); |
| 793 | |
| 794 | for (i = 0; i < cnt; i++) { |
| 795 | data = DSI_R32(ctrl, off); |
| 796 | if (!repeated_bytes) |
| 797 | *lp++ = ntohl(data); |
| 798 | else |
| 799 | *temp++ = ntohl(data); |
| 800 | off -= 4; |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 801 | } |
| 802 | |
Sandeep Panda | 7945000 | 2017-05-08 17:14:24 +0530 | [diff] [blame] | 803 | if (repeated_bytes) { |
| 804 | for (i = repeated_bytes; i < 16; i++) |
| 805 | rd_buf[j++] = reg[i]; |
| 806 | } |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 807 | |
Sandeep Panda | 7945000 | 2017-05-08 17:14:24 +0530 | [diff] [blame] | 808 | *hw_read_cnt = read_cnt; |
| 809 | pr_debug("[DSI_%d] Read %d bytes\n", ctrl->index, rx_byte); |
| 810 | return rx_byte; |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 811 | } |
| 812 | |
| 813 | /** |
| 814 | * get_interrupt_status() - returns the interrupt status |
| 815 | * @ctrl: Pointer to the controller host hardware. |
| 816 | * |
| 817 | * Returns the ORed list of interrupts(enum dsi_status_int_type) that |
| 818 | * are active. This list does not include any error interrupts. Caller |
| 819 | * should call get_error_status for error interrupts. |
| 820 | * |
| 821 | * Return: List of active interrupts. |
| 822 | */ |
| 823 | u32 dsi_ctrl_hw_cmn_get_interrupt_status(struct dsi_ctrl_hw *ctrl) |
| 824 | { |
| 825 | u32 reg = 0; |
| 826 | u32 ints = 0; |
| 827 | |
| 828 | reg = DSI_R32(ctrl, DSI_INT_CTRL); |
| 829 | |
| 830 | if (reg & BIT(0)) |
| 831 | ints |= DSI_CMD_MODE_DMA_DONE; |
| 832 | if (reg & BIT(8)) |
| 833 | ints |= DSI_CMD_FRAME_DONE; |
| 834 | if (reg & BIT(10)) |
| 835 | ints |= DSI_CMD_STREAM0_FRAME_DONE; |
| 836 | if (reg & BIT(12)) |
| 837 | ints |= DSI_CMD_STREAM1_FRAME_DONE; |
| 838 | if (reg & BIT(14)) |
| 839 | ints |= DSI_CMD_STREAM2_FRAME_DONE; |
| 840 | if (reg & BIT(16)) |
| 841 | ints |= DSI_VIDEO_MODE_FRAME_DONE; |
| 842 | if (reg & BIT(20)) |
| 843 | ints |= DSI_BTA_DONE; |
| 844 | if (reg & BIT(28)) |
| 845 | ints |= DSI_DYN_REFRESH_DONE; |
| 846 | if (reg & BIT(30)) |
| 847 | ints |= DSI_DESKEW_DONE; |
Sandeep Panda | 11b20d8 | 2017-06-19 12:57:27 +0530 | [diff] [blame] | 848 | if (reg & BIT(24)) |
| 849 | ints |= DSI_ERROR; |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 850 | |
| 851 | pr_debug("[DSI_%d] Interrupt status = 0x%x, INT_CTRL=0x%x\n", |
| 852 | ctrl->index, ints, reg); |
| 853 | return ints; |
| 854 | } |
| 855 | |
| 856 | /** |
| 857 | * clear_interrupt_status() - clears the specified interrupts |
| 858 | * @ctrl: Pointer to the controller host hardware. |
| 859 | * @ints: List of interrupts to be cleared. |
| 860 | */ |
| 861 | void dsi_ctrl_hw_cmn_clear_interrupt_status(struct dsi_ctrl_hw *ctrl, u32 ints) |
| 862 | { |
| 863 | u32 reg = 0; |
| 864 | |
Clarence Ip | 80ada7f | 2017-05-04 09:55:21 -0700 | [diff] [blame] | 865 | reg = DSI_R32(ctrl, DSI_INT_CTRL); |
| 866 | |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 867 | if (ints & DSI_CMD_MODE_DMA_DONE) |
| 868 | reg |= BIT(0); |
| 869 | if (ints & DSI_CMD_FRAME_DONE) |
| 870 | reg |= BIT(8); |
| 871 | if (ints & DSI_CMD_STREAM0_FRAME_DONE) |
| 872 | reg |= BIT(10); |
| 873 | if (ints & DSI_CMD_STREAM1_FRAME_DONE) |
| 874 | reg |= BIT(12); |
| 875 | if (ints & DSI_CMD_STREAM2_FRAME_DONE) |
| 876 | reg |= BIT(14); |
| 877 | if (ints & DSI_VIDEO_MODE_FRAME_DONE) |
| 878 | reg |= BIT(16); |
| 879 | if (ints & DSI_BTA_DONE) |
| 880 | reg |= BIT(20); |
| 881 | if (ints & DSI_DYN_REFRESH_DONE) |
| 882 | reg |= BIT(28); |
| 883 | if (ints & DSI_DESKEW_DONE) |
| 884 | reg |= BIT(30); |
| 885 | |
Sandeep Panda | 11b20d8 | 2017-06-19 12:57:27 +0530 | [diff] [blame] | 886 | /* |
| 887 | * Do not clear error status. |
| 888 | * It will be cleared as part of |
| 889 | * error handler function. |
| 890 | */ |
| 891 | reg &= ~BIT(24); |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 892 | DSI_W32(ctrl, DSI_INT_CTRL, reg); |
| 893 | |
| 894 | pr_debug("[DSI_%d] Clear interrupts, ints = 0x%x, INT_CTRL=0x%x\n", |
| 895 | ctrl->index, ints, reg); |
| 896 | } |
| 897 | |
| 898 | /** |
| 899 | * enable_status_interrupts() - enable the specified interrupts |
| 900 | * @ctrl: Pointer to the controller host hardware. |
| 901 | * @ints: List of interrupts to be enabled. |
| 902 | * |
| 903 | * Enables the specified interrupts. This list will override the |
| 904 | * previous interrupts enabled through this function. Caller has to |
| 905 | * maintain the state of the interrupts enabled. To disable all |
| 906 | * interrupts, set ints to 0. |
| 907 | */ |
| 908 | void dsi_ctrl_hw_cmn_enable_status_interrupts( |
| 909 | struct dsi_ctrl_hw *ctrl, u32 ints) |
| 910 | { |
| 911 | u32 reg = 0; |
| 912 | |
| 913 | /* Do not change value of DSI_ERROR_MASK bit */ |
| 914 | reg |= (DSI_R32(ctrl, DSI_INT_CTRL) & BIT(25)); |
| 915 | if (ints & DSI_CMD_MODE_DMA_DONE) |
| 916 | reg |= BIT(1); |
| 917 | if (ints & DSI_CMD_FRAME_DONE) |
| 918 | reg |= BIT(9); |
| 919 | if (ints & DSI_CMD_STREAM0_FRAME_DONE) |
| 920 | reg |= BIT(11); |
| 921 | if (ints & DSI_CMD_STREAM1_FRAME_DONE) |
| 922 | reg |= BIT(13); |
| 923 | if (ints & DSI_CMD_STREAM2_FRAME_DONE) |
| 924 | reg |= BIT(15); |
| 925 | if (ints & DSI_VIDEO_MODE_FRAME_DONE) |
| 926 | reg |= BIT(17); |
| 927 | if (ints & DSI_BTA_DONE) |
| 928 | reg |= BIT(21); |
| 929 | if (ints & DSI_DYN_REFRESH_DONE) |
| 930 | reg |= BIT(29); |
| 931 | if (ints & DSI_DESKEW_DONE) |
| 932 | reg |= BIT(31); |
| 933 | |
| 934 | DSI_W32(ctrl, DSI_INT_CTRL, reg); |
| 935 | |
| 936 | pr_debug("[DSI_%d] Enable interrupts 0x%x, INT_CTRL=0x%x\n", |
| 937 | ctrl->index, ints, reg); |
| 938 | } |
| 939 | |
| 940 | /** |
| 941 | * get_error_status() - returns the error status |
| 942 | * @ctrl: Pointer to the controller host hardware. |
| 943 | * |
| 944 | * Returns the ORed list of errors(enum dsi_error_int_type) that are |
| 945 | * active. This list does not include any status interrupts. Caller |
| 946 | * should call get_interrupt_status for status interrupts. |
| 947 | * |
| 948 | * Return: List of active error interrupts. |
| 949 | */ |
| 950 | u64 dsi_ctrl_hw_cmn_get_error_status(struct dsi_ctrl_hw *ctrl) |
| 951 | { |
| 952 | u32 dln0_phy_err; |
| 953 | u32 fifo_status; |
| 954 | u32 ack_error; |
| 955 | u32 timeout_errors; |
| 956 | u32 clk_error; |
| 957 | u32 dsi_status; |
Sandeep Panda | 11b20d8 | 2017-06-19 12:57:27 +0530 | [diff] [blame] | 958 | u64 errors = 0, shift = 0x1; |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 959 | |
| 960 | dln0_phy_err = DSI_R32(ctrl, DSI_DLN0_PHY_ERR); |
| 961 | if (dln0_phy_err & BIT(0)) |
| 962 | errors |= DSI_DLN0_ESC_ENTRY_ERR; |
| 963 | if (dln0_phy_err & BIT(4)) |
| 964 | errors |= DSI_DLN0_ESC_SYNC_ERR; |
| 965 | if (dln0_phy_err & BIT(8)) |
| 966 | errors |= DSI_DLN0_LP_CONTROL_ERR; |
| 967 | if (dln0_phy_err & BIT(12)) |
| 968 | errors |= DSI_DLN0_LP0_CONTENTION; |
| 969 | if (dln0_phy_err & BIT(16)) |
| 970 | errors |= DSI_DLN0_LP1_CONTENTION; |
| 971 | |
| 972 | fifo_status = DSI_R32(ctrl, DSI_FIFO_STATUS); |
| 973 | if (fifo_status & BIT(7)) |
| 974 | errors |= DSI_CMD_MDP_FIFO_UNDERFLOW; |
| 975 | if (fifo_status & BIT(10)) |
| 976 | errors |= DSI_CMD_DMA_FIFO_UNDERFLOW; |
| 977 | if (fifo_status & BIT(18)) |
| 978 | errors |= DSI_DLN0_HS_FIFO_OVERFLOW; |
| 979 | if (fifo_status & BIT(19)) |
| 980 | errors |= DSI_DLN0_HS_FIFO_UNDERFLOW; |
| 981 | if (fifo_status & BIT(22)) |
| 982 | errors |= DSI_DLN1_HS_FIFO_OVERFLOW; |
| 983 | if (fifo_status & BIT(23)) |
| 984 | errors |= DSI_DLN1_HS_FIFO_UNDERFLOW; |
| 985 | if (fifo_status & BIT(26)) |
| 986 | errors |= DSI_DLN2_HS_FIFO_OVERFLOW; |
| 987 | if (fifo_status & BIT(27)) |
| 988 | errors |= DSI_DLN2_HS_FIFO_UNDERFLOW; |
| 989 | if (fifo_status & BIT(30)) |
| 990 | errors |= DSI_DLN3_HS_FIFO_OVERFLOW; |
| 991 | if (fifo_status & BIT(31)) |
| 992 | errors |= DSI_DLN3_HS_FIFO_UNDERFLOW; |
| 993 | |
| 994 | ack_error = DSI_R32(ctrl, DSI_ACK_ERR_STATUS); |
| 995 | if (ack_error & BIT(16)) |
| 996 | errors |= DSI_RDBK_SINGLE_ECC_ERR; |
| 997 | if (ack_error & BIT(17)) |
| 998 | errors |= DSI_RDBK_MULTI_ECC_ERR; |
| 999 | if (ack_error & BIT(20)) |
| 1000 | errors |= DSI_RDBK_CRC_ERR; |
| 1001 | if (ack_error & BIT(23)) |
| 1002 | errors |= DSI_RDBK_INCOMPLETE_PKT; |
| 1003 | if (ack_error & BIT(24)) |
| 1004 | errors |= DSI_PERIPH_ERROR_PKT; |
Sandeep Panda | 11b20d8 | 2017-06-19 12:57:27 +0530 | [diff] [blame] | 1005 | if (ack_error & BIT(15)) |
| 1006 | errors |= (shift << DSI_EINT_PANEL_SPECIFIC_ERR); |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 1007 | |
| 1008 | timeout_errors = DSI_R32(ctrl, DSI_TIMEOUT_STATUS); |
| 1009 | if (timeout_errors & BIT(0)) |
| 1010 | errors |= DSI_HS_TX_TIMEOUT; |
| 1011 | if (timeout_errors & BIT(4)) |
| 1012 | errors |= DSI_LP_RX_TIMEOUT; |
| 1013 | if (timeout_errors & BIT(8)) |
| 1014 | errors |= DSI_BTA_TIMEOUT; |
| 1015 | |
| 1016 | clk_error = DSI_R32(ctrl, DSI_CLK_STATUS); |
| 1017 | if (clk_error & BIT(16)) |
| 1018 | errors |= DSI_PLL_UNLOCK; |
| 1019 | |
| 1020 | dsi_status = DSI_R32(ctrl, DSI_STATUS); |
| 1021 | if (dsi_status & BIT(31)) |
| 1022 | errors |= DSI_INTERLEAVE_OP_CONTENTION; |
| 1023 | |
| 1024 | pr_debug("[DSI_%d] Error status = 0x%llx, phy=0x%x, fifo=0x%x", |
| 1025 | ctrl->index, errors, dln0_phy_err, fifo_status); |
| 1026 | pr_debug("[DSI_%d] ack=0x%x, timeout=0x%x, clk=0x%x, dsi=0x%x\n", |
| 1027 | ctrl->index, ack_error, timeout_errors, clk_error, dsi_status); |
| 1028 | return errors; |
| 1029 | } |
| 1030 | |
| 1031 | /** |
| 1032 | * clear_error_status() - clears the specified errors |
| 1033 | * @ctrl: Pointer to the controller host hardware. |
| 1034 | * @errors: List of errors to be cleared. |
| 1035 | */ |
| 1036 | void dsi_ctrl_hw_cmn_clear_error_status(struct dsi_ctrl_hw *ctrl, u64 errors) |
| 1037 | { |
| 1038 | u32 dln0_phy_err = 0; |
| 1039 | u32 fifo_status = 0; |
| 1040 | u32 ack_error = 0; |
| 1041 | u32 timeout_error = 0; |
| 1042 | u32 clk_error = 0; |
| 1043 | u32 dsi_status = 0; |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 1044 | |
| 1045 | if (errors & DSI_RDBK_SINGLE_ECC_ERR) |
| 1046 | ack_error |= BIT(16); |
| 1047 | if (errors & DSI_RDBK_MULTI_ECC_ERR) |
| 1048 | ack_error |= BIT(17); |
| 1049 | if (errors & DSI_RDBK_CRC_ERR) |
| 1050 | ack_error |= BIT(20); |
| 1051 | if (errors & DSI_RDBK_INCOMPLETE_PKT) |
| 1052 | ack_error |= BIT(23); |
| 1053 | if (errors & DSI_PERIPH_ERROR_PKT) |
| 1054 | ack_error |= BIT(24); |
Sandeep Panda | 11b20d8 | 2017-06-19 12:57:27 +0530 | [diff] [blame] | 1055 | if (errors & DSI_PANEL_SPECIFIC_ERR) |
| 1056 | ack_error |= BIT(15); |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 1057 | |
| 1058 | if (errors & DSI_LP_RX_TIMEOUT) |
| 1059 | timeout_error |= BIT(4); |
| 1060 | if (errors & DSI_HS_TX_TIMEOUT) |
| 1061 | timeout_error |= BIT(0); |
| 1062 | if (errors & DSI_BTA_TIMEOUT) |
| 1063 | timeout_error |= BIT(8); |
| 1064 | |
| 1065 | if (errors & DSI_PLL_UNLOCK) |
| 1066 | clk_error |= BIT(16); |
| 1067 | |
| 1068 | if (errors & DSI_DLN0_LP0_CONTENTION) |
| 1069 | dln0_phy_err |= BIT(12); |
| 1070 | if (errors & DSI_DLN0_LP1_CONTENTION) |
| 1071 | dln0_phy_err |= BIT(16); |
| 1072 | if (errors & DSI_DLN0_ESC_ENTRY_ERR) |
| 1073 | dln0_phy_err |= BIT(0); |
| 1074 | if (errors & DSI_DLN0_ESC_SYNC_ERR) |
| 1075 | dln0_phy_err |= BIT(4); |
| 1076 | if (errors & DSI_DLN0_LP_CONTROL_ERR) |
| 1077 | dln0_phy_err |= BIT(8); |
| 1078 | |
| 1079 | if (errors & DSI_CMD_DMA_FIFO_UNDERFLOW) |
| 1080 | fifo_status |= BIT(10); |
| 1081 | if (errors & DSI_CMD_MDP_FIFO_UNDERFLOW) |
| 1082 | fifo_status |= BIT(7); |
| 1083 | if (errors & DSI_DLN0_HS_FIFO_OVERFLOW) |
| 1084 | fifo_status |= BIT(18); |
| 1085 | if (errors & DSI_DLN1_HS_FIFO_OVERFLOW) |
| 1086 | fifo_status |= BIT(22); |
| 1087 | if (errors & DSI_DLN2_HS_FIFO_OVERFLOW) |
| 1088 | fifo_status |= BIT(26); |
| 1089 | if (errors & DSI_DLN3_HS_FIFO_OVERFLOW) |
| 1090 | fifo_status |= BIT(30); |
| 1091 | if (errors & DSI_DLN0_HS_FIFO_UNDERFLOW) |
| 1092 | fifo_status |= BIT(19); |
| 1093 | if (errors & DSI_DLN1_HS_FIFO_UNDERFLOW) |
| 1094 | fifo_status |= BIT(23); |
| 1095 | if (errors & DSI_DLN2_HS_FIFO_UNDERFLOW) |
| 1096 | fifo_status |= BIT(27); |
| 1097 | if (errors & DSI_DLN3_HS_FIFO_UNDERFLOW) |
| 1098 | fifo_status |= BIT(31); |
| 1099 | |
| 1100 | if (errors & DSI_INTERLEAVE_OP_CONTENTION) |
| 1101 | dsi_status |= BIT(31); |
| 1102 | |
| 1103 | DSI_W32(ctrl, DSI_DLN0_PHY_ERR, dln0_phy_err); |
| 1104 | DSI_W32(ctrl, DSI_FIFO_STATUS, fifo_status); |
Sandeep Panda | 11b20d8 | 2017-06-19 12:57:27 +0530 | [diff] [blame] | 1105 | /* Writing of an extra 0 is needed to clear ack error bits */ |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 1106 | DSI_W32(ctrl, DSI_ACK_ERR_STATUS, ack_error); |
Sandeep Panda | 11b20d8 | 2017-06-19 12:57:27 +0530 | [diff] [blame] | 1107 | wmb(); /* make sure register is committed */ |
| 1108 | DSI_W32(ctrl, DSI_ACK_ERR_STATUS, 0x0); |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 1109 | DSI_W32(ctrl, DSI_TIMEOUT_STATUS, timeout_error); |
| 1110 | DSI_W32(ctrl, DSI_CLK_STATUS, clk_error); |
| 1111 | DSI_W32(ctrl, DSI_STATUS, dsi_status); |
| 1112 | |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 1113 | pr_debug("[DSI_%d] clear errors = 0x%llx, phy=0x%x, fifo=0x%x", |
| 1114 | ctrl->index, errors, dln0_phy_err, fifo_status); |
| 1115 | pr_debug("[DSI_%d] ack=0x%x, timeout=0x%x, clk=0x%x, dsi=0x%x\n", |
| 1116 | ctrl->index, ack_error, timeout_error, clk_error, dsi_status); |
| 1117 | } |
| 1118 | |
| 1119 | /** |
| 1120 | * enable_error_interrupts() - enable the specified interrupts |
| 1121 | * @ctrl: Pointer to the controller host hardware. |
| 1122 | * @errors: List of errors to be enabled. |
| 1123 | * |
| 1124 | * Enables the specified interrupts. This list will override the |
| 1125 | * previous interrupts enabled through this function. Caller has to |
| 1126 | * maintain the state of the interrupts enabled. To disable all |
| 1127 | * interrupts, set errors to 0. |
| 1128 | */ |
| 1129 | void dsi_ctrl_hw_cmn_enable_error_interrupts(struct dsi_ctrl_hw *ctrl, |
| 1130 | u64 errors) |
| 1131 | { |
| 1132 | u32 int_ctrl = 0; |
| 1133 | u32 int_mask0 = 0x7FFF3BFF; |
| 1134 | |
| 1135 | int_ctrl = DSI_R32(ctrl, DSI_INT_CTRL); |
| 1136 | if (errors) |
| 1137 | int_ctrl |= BIT(25); |
| 1138 | else |
| 1139 | int_ctrl &= ~BIT(25); |
| 1140 | |
| 1141 | if (errors & DSI_RDBK_SINGLE_ECC_ERR) |
| 1142 | int_mask0 &= ~BIT(0); |
| 1143 | if (errors & DSI_RDBK_MULTI_ECC_ERR) |
| 1144 | int_mask0 &= ~BIT(1); |
| 1145 | if (errors & DSI_RDBK_CRC_ERR) |
| 1146 | int_mask0 &= ~BIT(2); |
| 1147 | if (errors & DSI_RDBK_INCOMPLETE_PKT) |
| 1148 | int_mask0 &= ~BIT(3); |
| 1149 | if (errors & DSI_PERIPH_ERROR_PKT) |
| 1150 | int_mask0 &= ~BIT(4); |
| 1151 | |
| 1152 | if (errors & DSI_LP_RX_TIMEOUT) |
| 1153 | int_mask0 &= ~BIT(5); |
| 1154 | if (errors & DSI_HS_TX_TIMEOUT) |
| 1155 | int_mask0 &= ~BIT(6); |
| 1156 | if (errors & DSI_BTA_TIMEOUT) |
| 1157 | int_mask0 &= ~BIT(7); |
| 1158 | |
| 1159 | if (errors & DSI_PLL_UNLOCK) |
| 1160 | int_mask0 &= ~BIT(28); |
| 1161 | |
| 1162 | if (errors & DSI_DLN0_LP0_CONTENTION) |
| 1163 | int_mask0 &= ~BIT(24); |
| 1164 | if (errors & DSI_DLN0_LP1_CONTENTION) |
| 1165 | int_mask0 &= ~BIT(25); |
| 1166 | if (errors & DSI_DLN0_ESC_ENTRY_ERR) |
| 1167 | int_mask0 &= ~BIT(21); |
| 1168 | if (errors & DSI_DLN0_ESC_SYNC_ERR) |
| 1169 | int_mask0 &= ~BIT(22); |
| 1170 | if (errors & DSI_DLN0_LP_CONTROL_ERR) |
| 1171 | int_mask0 &= ~BIT(23); |
| 1172 | |
| 1173 | if (errors & DSI_CMD_DMA_FIFO_UNDERFLOW) |
| 1174 | int_mask0 &= ~BIT(9); |
| 1175 | if (errors & DSI_CMD_MDP_FIFO_UNDERFLOW) |
| 1176 | int_mask0 &= ~BIT(11); |
| 1177 | if (errors & DSI_DLN0_HS_FIFO_OVERFLOW) |
| 1178 | int_mask0 &= ~BIT(16); |
| 1179 | if (errors & DSI_DLN1_HS_FIFO_OVERFLOW) |
| 1180 | int_mask0 &= ~BIT(17); |
| 1181 | if (errors & DSI_DLN2_HS_FIFO_OVERFLOW) |
| 1182 | int_mask0 &= ~BIT(18); |
| 1183 | if (errors & DSI_DLN3_HS_FIFO_OVERFLOW) |
| 1184 | int_mask0 &= ~BIT(19); |
| 1185 | if (errors & DSI_DLN0_HS_FIFO_UNDERFLOW) |
| 1186 | int_mask0 &= ~BIT(26); |
| 1187 | if (errors & DSI_DLN1_HS_FIFO_UNDERFLOW) |
| 1188 | int_mask0 &= ~BIT(27); |
| 1189 | if (errors & DSI_DLN2_HS_FIFO_UNDERFLOW) |
| 1190 | int_mask0 &= ~BIT(29); |
| 1191 | if (errors & DSI_DLN3_HS_FIFO_UNDERFLOW) |
| 1192 | int_mask0 &= ~BIT(30); |
| 1193 | |
| 1194 | if (errors & DSI_INTERLEAVE_OP_CONTENTION) |
| 1195 | int_mask0 &= ~BIT(8); |
| 1196 | |
| 1197 | DSI_W32(ctrl, DSI_INT_CTRL, int_ctrl); |
| 1198 | DSI_W32(ctrl, DSI_ERR_INT_MASK0, int_mask0); |
| 1199 | |
| 1200 | pr_debug("[DSI_%d] enable errors = 0x%llx, int_mask0=0x%x\n", |
| 1201 | ctrl->index, errors, int_mask0); |
| 1202 | } |
| 1203 | |
| 1204 | /** |
| 1205 | * video_test_pattern_setup() - setup test pattern engine for video mode |
| 1206 | * @ctrl: Pointer to the controller host hardware. |
| 1207 | * @type: Type of test pattern. |
| 1208 | * @init_val: Initial value to use for generating test pattern. |
| 1209 | */ |
| 1210 | void dsi_ctrl_hw_cmn_video_test_pattern_setup(struct dsi_ctrl_hw *ctrl, |
| 1211 | enum dsi_test_pattern type, |
| 1212 | u32 init_val) |
| 1213 | { |
| 1214 | u32 reg = 0; |
| 1215 | |
| 1216 | DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, init_val); |
| 1217 | |
| 1218 | switch (type) { |
| 1219 | case DSI_TEST_PATTERN_FIXED: |
| 1220 | reg |= (0x2 << 4); |
| 1221 | break; |
| 1222 | case DSI_TEST_PATTERN_INC: |
| 1223 | reg |= (0x1 << 4); |
| 1224 | break; |
| 1225 | case DSI_TEST_PATTERN_POLY: |
| 1226 | DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_VIDEO_POLY, 0xF0F0F); |
| 1227 | break; |
| 1228 | default: |
| 1229 | break; |
| 1230 | } |
| 1231 | |
| 1232 | DSI_W32(ctrl, DSI_TPG_MAIN_CONTROL, 0x100); |
| 1233 | DSI_W32(ctrl, DSI_TPG_VIDEO_CONFIG, 0x5); |
| 1234 | DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CTRL, reg); |
| 1235 | |
| 1236 | pr_debug("[DSI_%d] Video test pattern setup done\n", ctrl->index); |
| 1237 | } |
| 1238 | |
| 1239 | /** |
| 1240 | * cmd_test_pattern_setup() - setup test patttern engine for cmd mode |
| 1241 | * @ctrl: Pointer to the controller host hardware. |
| 1242 | * @type: Type of test pattern. |
| 1243 | * @init_val: Initial value to use for generating test pattern. |
| 1244 | * @stream_id: Stream Id on which packets are generated. |
| 1245 | */ |
| 1246 | void dsi_ctrl_hw_cmn_cmd_test_pattern_setup(struct dsi_ctrl_hw *ctrl, |
| 1247 | enum dsi_test_pattern type, |
| 1248 | u32 init_val, |
| 1249 | u32 stream_id) |
| 1250 | { |
| 1251 | u32 reg = 0; |
| 1252 | u32 init_offset; |
| 1253 | u32 poly_offset; |
| 1254 | u32 pattern_sel_shift; |
| 1255 | |
| 1256 | switch (stream_id) { |
| 1257 | case 0: |
| 1258 | init_offset = DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0; |
| 1259 | poly_offset = DSI_TEST_PATTERN_GEN_CMD_MDP_STREAM0_POLY; |
| 1260 | pattern_sel_shift = 8; |
| 1261 | break; |
| 1262 | case 1: |
| 1263 | init_offset = DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL1; |
| 1264 | poly_offset = DSI_TEST_PATTERN_GEN_CMD_MDP_STREAM1_POLY; |
| 1265 | pattern_sel_shift = 12; |
| 1266 | break; |
| 1267 | case 2: |
| 1268 | init_offset = DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL2; |
| 1269 | poly_offset = DSI_TEST_PATTERN_GEN_CMD_MDP_STREAM2_POLY; |
| 1270 | pattern_sel_shift = 20; |
| 1271 | break; |
| 1272 | default: |
| 1273 | return; |
| 1274 | } |
| 1275 | |
| 1276 | DSI_W32(ctrl, init_offset, init_val); |
| 1277 | |
| 1278 | switch (type) { |
| 1279 | case DSI_TEST_PATTERN_FIXED: |
| 1280 | reg |= (0x2 << pattern_sel_shift); |
| 1281 | break; |
| 1282 | case DSI_TEST_PATTERN_INC: |
| 1283 | reg |= (0x1 << pattern_sel_shift); |
| 1284 | break; |
| 1285 | case DSI_TEST_PATTERN_POLY: |
| 1286 | DSI_W32(ctrl, poly_offset, 0xF0F0F); |
| 1287 | break; |
| 1288 | default: |
| 1289 | break; |
| 1290 | } |
| 1291 | |
| 1292 | DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CTRL, reg); |
| 1293 | pr_debug("[DSI_%d] Cmd test pattern setup done\n", ctrl->index); |
| 1294 | } |
| 1295 | |
| 1296 | /** |
| 1297 | * test_pattern_enable() - enable test pattern engine |
| 1298 | * @ctrl: Pointer to the controller host hardware. |
| 1299 | * @enable: Enable/Disable test pattern engine. |
| 1300 | */ |
| 1301 | void dsi_ctrl_hw_cmn_test_pattern_enable(struct dsi_ctrl_hw *ctrl, |
| 1302 | bool enable) |
| 1303 | { |
| 1304 | u32 reg = DSI_R32(ctrl, DSI_TEST_PATTERN_GEN_CTRL); |
| 1305 | |
| 1306 | if (enable) |
| 1307 | reg |= BIT(0); |
| 1308 | else |
| 1309 | reg &= ~BIT(0); |
| 1310 | |
| 1311 | DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CTRL, reg); |
| 1312 | |
| 1313 | pr_debug("[DSI_%d] Test pattern enable=%d\n", ctrl->index, enable); |
| 1314 | } |
| 1315 | |
| 1316 | /** |
| 1317 | * trigger_cmd_test_pattern() - trigger a command mode frame update with |
| 1318 | * test pattern |
| 1319 | * @ctrl: Pointer to the controller host hardware. |
| 1320 | * @stream_id: Stream on which frame update is sent. |
| 1321 | */ |
| 1322 | void dsi_ctrl_hw_cmn_trigger_cmd_test_pattern(struct dsi_ctrl_hw *ctrl, |
| 1323 | u32 stream_id) |
| 1324 | { |
| 1325 | switch (stream_id) { |
| 1326 | case 0: |
| 1327 | DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER, 0x1); |
| 1328 | break; |
| 1329 | case 1: |
| 1330 | DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CMD_STREAM1_TRIGGER, 0x1); |
| 1331 | break; |
| 1332 | case 2: |
| 1333 | DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CMD_STREAM2_TRIGGER, 0x1); |
| 1334 | break; |
| 1335 | default: |
| 1336 | break; |
| 1337 | } |
| 1338 | |
| 1339 | pr_debug("[DSI_%d] Cmd Test pattern trigger\n", ctrl->index); |
| 1340 | } |
| 1341 | |
| 1342 | void dsi_ctrl_hw_dln0_phy_err(struct dsi_ctrl_hw *ctrl) |
| 1343 | { |
| 1344 | u32 status = 0; |
| 1345 | /* |
| 1346 | * Clear out any phy errors prior to exiting ULPS |
| 1347 | * This fixes certain instances where phy does not exit |
| 1348 | * ULPS cleanly. Also, do not print error during such cases. |
| 1349 | */ |
| 1350 | status = DSI_R32(ctrl, DSI_DLN0_PHY_ERR); |
| 1351 | if (status & 0x011111) { |
| 1352 | DSI_W32(ctrl, DSI_DLN0_PHY_ERR, status); |
| 1353 | pr_err("%s: phy_err_status = %x\n", __func__, status); |
| 1354 | } |
| 1355 | } |
| 1356 | |
| 1357 | void dsi_ctrl_hw_cmn_phy_reset_config(struct dsi_ctrl_hw *ctrl, |
| 1358 | bool enable) |
| 1359 | { |
| 1360 | u32 reg = 0; |
| 1361 | |
| 1362 | reg = DSI_MMSS_MISC_R32(ctrl, MMSS_MISC_CLAMP_REG_OFF); |
| 1363 | |
| 1364 | /* Mask/unmask disable PHY reset bit */ |
| 1365 | if (enable) |
| 1366 | reg |= BIT(30); |
| 1367 | else |
| 1368 | reg &= ~BIT(30); |
| 1369 | |
| 1370 | DSI_MMSS_MISC_W32(ctrl, MMSS_MISC_CLAMP_REG_OFF, reg); |
| 1371 | } |
| 1372 | |
Sandeep Panda | 11b20d8 | 2017-06-19 12:57:27 +0530 | [diff] [blame] | 1373 | int dsi_ctrl_hw_cmn_ctrl_reset(struct dsi_ctrl_hw *ctrl, |
| 1374 | int mask) |
| 1375 | { |
| 1376 | int rc = 0; |
| 1377 | u32 data; |
| 1378 | |
| 1379 | pr_debug("DSI CTRL and PHY reset. ctrl-num = %d %d\n", |
| 1380 | ctrl->index, mask); |
| 1381 | |
| 1382 | data = DSI_R32(ctrl, 0x0004); |
| 1383 | /* Disable DSI video mode */ |
| 1384 | DSI_W32(ctrl, 0x004, (data & ~BIT(1))); |
| 1385 | wmb(); /* ensure register committed */ |
| 1386 | /* Disable DSI controller */ |
| 1387 | DSI_W32(ctrl, 0x004, (data & ~(BIT(0) | BIT(1)))); |
| 1388 | wmb(); /* ensure register committed */ |
| 1389 | /* "Force On" all dynamic clocks */ |
| 1390 | DSI_W32(ctrl, 0x11c, 0x100a00); |
| 1391 | |
| 1392 | /* DSI_SW_RESET */ |
| 1393 | DSI_W32(ctrl, 0x118, 0x1); |
| 1394 | wmb(); /* ensure register is committed */ |
| 1395 | DSI_W32(ctrl, 0x118, 0x0); |
| 1396 | wmb(); /* ensure register is committed */ |
| 1397 | |
| 1398 | /* Remove "Force On" all dynamic clocks */ |
| 1399 | DSI_W32(ctrl, 0x11c, 0x00); |
| 1400 | /* Enable DSI controller */ |
| 1401 | DSI_W32(ctrl, 0x004, (data & ~BIT(1))); |
| 1402 | wmb(); /* ensure register committed */ |
| 1403 | |
| 1404 | return rc; |
| 1405 | } |
| 1406 | |
| 1407 | void dsi_ctrl_hw_cmn_mask_error_intr(struct dsi_ctrl_hw *ctrl, u32 idx, bool en) |
| 1408 | { |
| 1409 | u32 reg = 0; |
| 1410 | |
| 1411 | reg = DSI_R32(ctrl, 0x10c); |
| 1412 | |
| 1413 | if (idx & BIT(DSI_FIFO_OVERFLOW)) { |
| 1414 | if (en) |
| 1415 | reg |= (0xf << 16); |
| 1416 | else |
| 1417 | reg &= ~(0xf << 16); |
| 1418 | } |
| 1419 | |
| 1420 | if (idx & BIT(DSI_FIFO_UNDERFLOW)) { |
| 1421 | if (en) |
| 1422 | reg |= (0xf << 26); |
| 1423 | else |
| 1424 | reg &= ~(0xf << 26); |
| 1425 | } |
| 1426 | |
| 1427 | if (idx & BIT(DSI_LP_Rx_TIMEOUT)) { |
| 1428 | if (en) |
| 1429 | reg |= (0x7 << 23); |
| 1430 | else |
| 1431 | reg &= ~(0x7 << 23); |
| 1432 | } |
| 1433 | |
| 1434 | DSI_W32(ctrl, 0x10c, reg); |
| 1435 | wmb(); /* ensure error is masked */ |
| 1436 | } |
| 1437 | |
| 1438 | void dsi_ctrl_hw_cmn_error_intr_ctrl(struct dsi_ctrl_hw *ctrl, bool en) |
| 1439 | { |
| 1440 | u32 reg = 0; |
| 1441 | u32 dsi_total_mask = 0x2222AA02; |
| 1442 | |
| 1443 | reg = DSI_R32(ctrl, 0x110); |
| 1444 | reg &= dsi_total_mask; |
| 1445 | |
| 1446 | if (en) |
| 1447 | reg |= (BIT(24) | BIT(25)); |
| 1448 | else |
| 1449 | reg &= ~BIT(25); |
| 1450 | |
| 1451 | DSI_W32(ctrl, 0x110, reg); |
| 1452 | wmb(); /* ensure error is masked */ |
| 1453 | } |
| 1454 | |
| 1455 | u32 dsi_ctrl_hw_cmn_get_error_mask(struct dsi_ctrl_hw *ctrl) |
| 1456 | { |
| 1457 | u32 reg = 0; |
| 1458 | |
| 1459 | reg = DSI_R32(ctrl, 0x10c); |
| 1460 | |
| 1461 | return reg; |
| 1462 | } |
| 1463 | |
| 1464 | u32 dsi_ctrl_hw_cmn_get_hw_version(struct dsi_ctrl_hw *ctrl) |
| 1465 | { |
| 1466 | u32 reg = 0; |
| 1467 | |
| 1468 | reg = DSI_R32(ctrl, 0x0); |
| 1469 | |
| 1470 | return reg; |
| 1471 | } |