Dave Airlie | 282a167 | 2005-08-07 15:43:54 +1000 | [diff] [blame] | 1 | /* savage_drv.h -- Private header for the savage driver |
| 2 | * |
| 3 | * Copyright 2004 Felix Kuehling |
| 4 | * All Rights Reserved. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sub license, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the |
| 14 | * next paragraph) shall be included in all copies or substantial portions |
| 15 | * of the Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 18 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 20 | * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR |
| 21 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF |
| 22 | * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
| 23 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 24 | */ |
| 25 | |
| 26 | #ifndef __SAVAGE_DRV_H__ |
| 27 | #define __SAVAGE_DRV_H__ |
| 28 | |
| 29 | #define DRIVER_AUTHOR "Felix Kuehling" |
| 30 | |
| 31 | #define DRIVER_NAME "savage" |
| 32 | #define DRIVER_DESC "Savage3D/MX/IX, Savage4, SuperSavage, Twister, ProSavage[DDR]" |
| 33 | #define DRIVER_DATE "20050313" |
| 34 | |
| 35 | #define DRIVER_MAJOR 2 |
| 36 | #define DRIVER_MINOR 4 |
| 37 | #define DRIVER_PATCHLEVEL 1 |
| 38 | /* Interface history: |
| 39 | * |
| 40 | * 1.x The DRM driver from the VIA/S3 code drop, basically a dummy |
| 41 | * 2.0 The first real DRM |
| 42 | * 2.1 Scissors registers managed by the DRM, 3D operations clipped by |
| 43 | * cliprects of the cmdbuf ioctl |
| 44 | * 2.2 Implemented SAVAGE_CMD_DMA_IDX and SAVAGE_CMD_VB_IDX |
| 45 | * 2.3 Event counters used by BCI_EVENT_EMIT/WAIT ioctls are now 32 bits |
| 46 | * wide and thus very long lived (unlikely to ever wrap). The size |
| 47 | * in the struct was 32 bits before, but only 16 bits were used |
| 48 | * 2.4 Implemented command DMA. Now drm_savage_init_t.cmd_dma_offset is |
| 49 | * actually used |
| 50 | */ |
| 51 | |
| 52 | typedef struct drm_savage_age { |
| 53 | uint16_t event; |
| 54 | unsigned int wrap; |
| 55 | } drm_savage_age_t; |
| 56 | |
| 57 | typedef struct drm_savage_buf_priv { |
| 58 | struct drm_savage_buf_priv *next; |
| 59 | struct drm_savage_buf_priv *prev; |
| 60 | drm_savage_age_t age; |
| 61 | drm_buf_t *buf; |
| 62 | } drm_savage_buf_priv_t; |
| 63 | |
| 64 | typedef struct drm_savage_dma_page { |
| 65 | drm_savage_age_t age; |
| 66 | unsigned int used, flushed; |
| 67 | } drm_savage_dma_page_t; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 68 | #define SAVAGE_DMA_PAGE_SIZE 1024 /* in dwords */ |
Dave Airlie | 282a167 | 2005-08-07 15:43:54 +1000 | [diff] [blame] | 69 | /* Fake DMA buffer size in bytes. 4 pages. Allows a maximum command |
| 70 | * size of 16kbytes or 4k entries. Minimum requirement would be |
| 71 | * 10kbytes for 255 40-byte vertices in one drawing command. */ |
| 72 | #define SAVAGE_FAKE_DMA_SIZE (SAVAGE_DMA_PAGE_SIZE*4*4) |
| 73 | |
| 74 | /* interesting bits of hardware state that are saved in dev_priv */ |
| 75 | typedef union { |
| 76 | struct drm_savage_common_state { |
| 77 | uint32_t vbaddr; |
| 78 | } common; |
| 79 | struct { |
| 80 | unsigned char pad[sizeof(struct drm_savage_common_state)]; |
| 81 | uint32_t texctrl, texaddr; |
| 82 | uint32_t scstart, new_scstart; |
| 83 | uint32_t scend, new_scend; |
| 84 | } s3d; |
| 85 | struct { |
| 86 | unsigned char pad[sizeof(struct drm_savage_common_state)]; |
| 87 | uint32_t texdescr, texaddr0, texaddr1; |
| 88 | uint32_t drawctrl0, new_drawctrl0; |
| 89 | uint32_t drawctrl1, new_drawctrl1; |
| 90 | } s4; |
| 91 | } drm_savage_state_t; |
| 92 | |
| 93 | /* these chip tags should match the ones in the 2D driver in savage_regs.h. */ |
| 94 | enum savage_family { |
| 95 | S3_UNKNOWN = 0, |
| 96 | S3_SAVAGE3D, |
| 97 | S3_SAVAGE_MX, |
| 98 | S3_SAVAGE4, |
| 99 | S3_PROSAVAGE, |
| 100 | S3_TWISTER, |
| 101 | S3_PROSAVAGEDDR, |
| 102 | S3_SUPERSAVAGE, |
| 103 | S3_SAVAGE2000, |
| 104 | S3_LAST |
| 105 | }; |
| 106 | |
Dave Airlie | b3a8363 | 2005-09-30 18:37:36 +1000 | [diff] [blame^] | 107 | extern drm_ioctl_desc_t savage_ioctls[]; |
| 108 | extern int savage_max_ioctl; |
| 109 | |
Dave Airlie | 282a167 | 2005-08-07 15:43:54 +1000 | [diff] [blame] | 110 | #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) |
| 111 | |
| 112 | #define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) \ |
| 113 | || (chip==S3_PROSAVAGE) \ |
| 114 | || (chip==S3_TWISTER) \ |
| 115 | || (chip==S3_PROSAVAGEDDR)) |
| 116 | |
| 117 | #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE)) |
| 118 | |
| 119 | #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000)) |
| 120 | |
| 121 | #define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) \ |
| 122 | ||(chip==S3_PROSAVAGEDDR)) |
| 123 | |
| 124 | /* flags */ |
| 125 | #define SAVAGE_IS_AGP 1 |
| 126 | |
| 127 | typedef struct drm_savage_private { |
| 128 | drm_savage_sarea_t *sarea_priv; |
| 129 | |
| 130 | drm_savage_buf_priv_t head, tail; |
| 131 | |
| 132 | /* who am I? */ |
| 133 | enum savage_family chipset; |
| 134 | |
| 135 | unsigned int cob_size; |
| 136 | unsigned int bci_threshold_lo, bci_threshold_hi; |
| 137 | unsigned int dma_type; |
| 138 | |
| 139 | /* frame buffer layout */ |
| 140 | unsigned int fb_bpp; |
| 141 | unsigned int front_offset, front_pitch; |
| 142 | unsigned int back_offset, back_pitch; |
| 143 | unsigned int depth_bpp; |
| 144 | unsigned int depth_offset, depth_pitch; |
| 145 | |
| 146 | /* bitmap descriptors for swap and clear */ |
| 147 | unsigned int front_bd, back_bd, depth_bd; |
| 148 | |
| 149 | /* local textures */ |
| 150 | unsigned int texture_offset; |
| 151 | unsigned int texture_size; |
| 152 | |
| 153 | /* memory regions in physical memory */ |
| 154 | drm_local_map_t *sarea; |
| 155 | drm_local_map_t *mmio; |
| 156 | drm_local_map_t *fb; |
| 157 | drm_local_map_t *aperture; |
| 158 | drm_local_map_t *status; |
| 159 | drm_local_map_t *agp_textures; |
| 160 | drm_local_map_t *cmd_dma; |
| 161 | drm_local_map_t fake_dma; |
| 162 | |
| 163 | struct { |
| 164 | int handle; |
| 165 | unsigned long base, size; |
| 166 | } mtrr[3]; |
| 167 | |
| 168 | /* BCI and status-related stuff */ |
| 169 | volatile uint32_t *status_ptr, *bci_ptr; |
| 170 | uint32_t status_used_mask; |
| 171 | uint16_t event_counter; |
| 172 | unsigned int event_wrap; |
| 173 | |
| 174 | /* Savage4 command DMA */ |
| 175 | drm_savage_dma_page_t *dma_pages; |
| 176 | unsigned int nr_dma_pages, first_dma_page, current_dma_page; |
| 177 | drm_savage_age_t last_dma_age; |
| 178 | |
| 179 | /* saved hw state for global/local check on S3D */ |
| 180 | uint32_t hw_draw_ctrl, hw_zbuf_ctrl; |
| 181 | /* and for scissors (global, so don't emit if not changed) */ |
| 182 | uint32_t hw_scissors_start, hw_scissors_end; |
| 183 | |
| 184 | drm_savage_state_t state; |
| 185 | |
| 186 | /* after emitting a wait cmd Savage3D needs 63 nops before next DMA */ |
| 187 | unsigned int waiting; |
| 188 | |
| 189 | /* config/hardware-dependent function pointers */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 190 | int (*wait_fifo) (struct drm_savage_private * dev_priv, unsigned int n); |
| 191 | int (*wait_evnt) (struct drm_savage_private * dev_priv, uint16_t e); |
Dave Airlie | 282a167 | 2005-08-07 15:43:54 +1000 | [diff] [blame] | 192 | /* Err, there is a macro wait_event in include/linux/wait.h. |
| 193 | * Avoid unwanted macro expansion. */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 194 | void (*emit_clip_rect) (struct drm_savage_private * dev_priv, |
| 195 | drm_clip_rect_t * pbox); |
| 196 | void (*dma_flush) (struct drm_savage_private * dev_priv); |
Dave Airlie | 282a167 | 2005-08-07 15:43:54 +1000 | [diff] [blame] | 197 | } drm_savage_private_t; |
| 198 | |
| 199 | /* ioctls */ |
| 200 | extern int savage_bci_cmdbuf(DRM_IOCTL_ARGS); |
| 201 | extern int savage_bci_buffers(DRM_IOCTL_ARGS); |
| 202 | |
| 203 | /* BCI functions */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 204 | extern uint16_t savage_bci_emit_event(drm_savage_private_t * dev_priv, |
Dave Airlie | 282a167 | 2005-08-07 15:43:54 +1000 | [diff] [blame] | 205 | unsigned int flags); |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 206 | extern void savage_freelist_put(drm_device_t * dev, drm_buf_t * buf); |
| 207 | extern void savage_dma_reset(drm_savage_private_t * dev_priv); |
| 208 | extern void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page); |
| 209 | extern uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv, |
Dave Airlie | 282a167 | 2005-08-07 15:43:54 +1000 | [diff] [blame] | 210 | unsigned int n); |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 211 | extern int savage_preinit(drm_device_t * dev, unsigned long chipset); |
| 212 | extern int savage_postcleanup(drm_device_t * dev); |
| 213 | extern int savage_do_cleanup_bci(drm_device_t * dev); |
| 214 | extern void savage_reclaim_buffers(drm_device_t * dev, DRMFILE filp); |
Dave Airlie | 282a167 | 2005-08-07 15:43:54 +1000 | [diff] [blame] | 215 | |
| 216 | /* state functions */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 217 | extern void savage_emit_clip_rect_s3d(drm_savage_private_t * dev_priv, |
| 218 | drm_clip_rect_t * pbox); |
| 219 | extern void savage_emit_clip_rect_s4(drm_savage_private_t * dev_priv, |
| 220 | drm_clip_rect_t * pbox); |
Dave Airlie | 282a167 | 2005-08-07 15:43:54 +1000 | [diff] [blame] | 221 | |
| 222 | #define SAVAGE_FB_SIZE_S3 0x01000000 /* 16MB */ |
| 223 | #define SAVAGE_FB_SIZE_S4 0x02000000 /* 32MB */ |
| 224 | #define SAVAGE_MMIO_SIZE 0x00080000 /* 512kB */ |
| 225 | #define SAVAGE_APERTURE_OFFSET 0x02000000 /* 32MB */ |
| 226 | #define SAVAGE_APERTURE_SIZE 0x05000000 /* 5 tiled surfaces, 16MB each */ |
| 227 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 228 | #define SAVAGE_BCI_OFFSET 0x00010000 /* offset of the BCI region |
Dave Airlie | 282a167 | 2005-08-07 15:43:54 +1000 | [diff] [blame] | 229 | * inside the MMIO region */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 230 | #define SAVAGE_BCI_FIFO_SIZE 32 /* number of entries in on-chip |
| 231 | * BCI FIFO */ |
Dave Airlie | 282a167 | 2005-08-07 15:43:54 +1000 | [diff] [blame] | 232 | |
| 233 | /* |
| 234 | * MMIO registers |
| 235 | */ |
| 236 | #define SAVAGE_STATUS_WORD0 0x48C00 |
| 237 | #define SAVAGE_STATUS_WORD1 0x48C04 |
| 238 | #define SAVAGE_ALT_STATUS_WORD0 0x48C60 |
| 239 | |
| 240 | #define SAVAGE_FIFO_USED_MASK_S3D 0x0001ffff |
| 241 | #define SAVAGE_FIFO_USED_MASK_S4 0x001fffff |
| 242 | |
| 243 | /* Copied from savage_bci.h in the 2D driver with some renaming. */ |
| 244 | |
| 245 | /* Bitmap descriptors */ |
| 246 | #define SAVAGE_BD_STRIDE_SHIFT 0 |
| 247 | #define SAVAGE_BD_BPP_SHIFT 16 |
| 248 | #define SAVAGE_BD_TILE_SHIFT 24 |
| 249 | #define SAVAGE_BD_BW_DISABLE (1<<28) |
| 250 | /* common: */ |
| 251 | #define SAVAGE_BD_TILE_LINEAR 0 |
| 252 | /* savage4, MX, IX, 3D */ |
| 253 | #define SAVAGE_BD_TILE_16BPP 2 |
| 254 | #define SAVAGE_BD_TILE_32BPP 3 |
| 255 | /* twister, prosavage, DDR, supersavage, 2000 */ |
| 256 | #define SAVAGE_BD_TILE_DEST 1 |
| 257 | #define SAVAGE_BD_TILE_TEXTURE 2 |
| 258 | /* GBD - BCI enable */ |
| 259 | /* savage4, MX, IX, 3D */ |
| 260 | #define SAVAGE_GBD_BCI_ENABLE 8 |
| 261 | /* twister, prosavage, DDR, supersavage, 2000 */ |
| 262 | #define SAVAGE_GBD_BCI_ENABLE_TWISTER 0 |
| 263 | |
| 264 | #define SAVAGE_GBD_BIG_ENDIAN 4 |
| 265 | #define SAVAGE_GBD_LITTLE_ENDIAN 0 |
| 266 | #define SAVAGE_GBD_64 1 |
| 267 | |
| 268 | /* Global Bitmap Descriptor */ |
| 269 | #define SAVAGE_BCI_GLB_BD_LOW 0x8168 |
| 270 | #define SAVAGE_BCI_GLB_BD_HIGH 0x816C |
| 271 | |
| 272 | /* |
| 273 | * BCI registers |
| 274 | */ |
| 275 | /* Savage4/Twister/ProSavage 3D registers */ |
| 276 | #define SAVAGE_DRAWLOCALCTRL_S4 0x1e |
| 277 | #define SAVAGE_TEXPALADDR_S4 0x1f |
| 278 | #define SAVAGE_TEXCTRL0_S4 0x20 |
| 279 | #define SAVAGE_TEXCTRL1_S4 0x21 |
| 280 | #define SAVAGE_TEXADDR0_S4 0x22 |
| 281 | #define SAVAGE_TEXADDR1_S4 0x23 |
| 282 | #define SAVAGE_TEXBLEND0_S4 0x24 |
| 283 | #define SAVAGE_TEXBLEND1_S4 0x25 |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 284 | #define SAVAGE_TEXXPRCLR_S4 0x26 /* never used */ |
Dave Airlie | 282a167 | 2005-08-07 15:43:54 +1000 | [diff] [blame] | 285 | #define SAVAGE_TEXDESCR_S4 0x27 |
| 286 | #define SAVAGE_FOGTABLE_S4 0x28 |
| 287 | #define SAVAGE_FOGCTRL_S4 0x30 |
| 288 | #define SAVAGE_STENCILCTRL_S4 0x31 |
| 289 | #define SAVAGE_ZBUFCTRL_S4 0x32 |
| 290 | #define SAVAGE_ZBUFOFF_S4 0x33 |
| 291 | #define SAVAGE_DESTCTRL_S4 0x34 |
| 292 | #define SAVAGE_DRAWCTRL0_S4 0x35 |
| 293 | #define SAVAGE_DRAWCTRL1_S4 0x36 |
| 294 | #define SAVAGE_ZWATERMARK_S4 0x37 |
| 295 | #define SAVAGE_DESTTEXRWWATERMARK_S4 0x38 |
| 296 | #define SAVAGE_TEXBLENDCOLOR_S4 0x39 |
| 297 | /* Savage3D/MX/IX 3D registers */ |
| 298 | #define SAVAGE_TEXPALADDR_S3D 0x18 |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 299 | #define SAVAGE_TEXXPRCLR_S3D 0x19 /* never used */ |
Dave Airlie | 282a167 | 2005-08-07 15:43:54 +1000 | [diff] [blame] | 300 | #define SAVAGE_TEXADDR_S3D 0x1A |
| 301 | #define SAVAGE_TEXDESCR_S3D 0x1B |
| 302 | #define SAVAGE_TEXCTRL_S3D 0x1C |
| 303 | #define SAVAGE_FOGTABLE_S3D 0x20 |
| 304 | #define SAVAGE_FOGCTRL_S3D 0x30 |
| 305 | #define SAVAGE_DRAWCTRL_S3D 0x31 |
| 306 | #define SAVAGE_ZBUFCTRL_S3D 0x32 |
| 307 | #define SAVAGE_ZBUFOFF_S3D 0x33 |
| 308 | #define SAVAGE_DESTCTRL_S3D 0x34 |
| 309 | #define SAVAGE_SCSTART_S3D 0x35 |
| 310 | #define SAVAGE_SCEND_S3D 0x36 |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 311 | #define SAVAGE_ZWATERMARK_S3D 0x37 |
Dave Airlie | 282a167 | 2005-08-07 15:43:54 +1000 | [diff] [blame] | 312 | #define SAVAGE_DESTTEXRWWATERMARK_S3D 0x38 |
| 313 | /* common stuff */ |
| 314 | #define SAVAGE_VERTBUFADDR 0x3e |
| 315 | #define SAVAGE_BITPLANEWTMASK 0xd7 |
| 316 | #define SAVAGE_DMABUFADDR 0x51 |
| 317 | |
| 318 | /* texture enable bits (needed for tex addr checking) */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 319 | #define SAVAGE_TEXCTRL_TEXEN_MASK 0x00010000 /* S3D */ |
| 320 | #define SAVAGE_TEXDESCR_TEX0EN_MASK 0x02000000 /* S4 */ |
| 321 | #define SAVAGE_TEXDESCR_TEX1EN_MASK 0x04000000 /* S4 */ |
Dave Airlie | 282a167 | 2005-08-07 15:43:54 +1000 | [diff] [blame] | 322 | |
| 323 | /* Global fields in Savage4/Twister/ProSavage 3D registers: |
| 324 | * |
| 325 | * All texture registers and DrawLocalCtrl are local. All other |
| 326 | * registers are global. */ |
| 327 | |
| 328 | /* Global fields in Savage3D/MX/IX 3D registers: |
| 329 | * |
| 330 | * All texture registers are local. DrawCtrl and ZBufCtrl are |
| 331 | * partially local. All other registers are global. |
| 332 | * |
| 333 | * DrawCtrl global fields: cullMode, alphaTestCmpFunc, alphaTestEn, alphaRefVal |
| 334 | * ZBufCtrl global fields: zCmpFunc, zBufEn |
| 335 | */ |
| 336 | #define SAVAGE_DRAWCTRL_S3D_GLOBAL 0x03f3c00c |
| 337 | #define SAVAGE_ZBUFCTRL_S3D_GLOBAL 0x00000027 |
| 338 | |
| 339 | /* Masks for scissor bits (drawCtrl[01] on s4, scissorStart/End on s3d) |
| 340 | */ |
| 341 | #define SAVAGE_SCISSOR_MASK_S4 0x00fff7ff |
| 342 | #define SAVAGE_SCISSOR_MASK_S3D 0x07ff07ff |
| 343 | |
| 344 | /* |
| 345 | * BCI commands |
| 346 | */ |
| 347 | #define BCI_CMD_NOP 0x40000000 |
| 348 | #define BCI_CMD_RECT 0x48000000 |
| 349 | #define BCI_CMD_RECT_XP 0x01000000 |
| 350 | #define BCI_CMD_RECT_YP 0x02000000 |
| 351 | #define BCI_CMD_SCANLINE 0x50000000 |
| 352 | #define BCI_CMD_LINE 0x5C000000 |
| 353 | #define BCI_CMD_LINE_LAST_PIXEL 0x58000000 |
| 354 | #define BCI_CMD_BYTE_TEXT 0x63000000 |
| 355 | #define BCI_CMD_NT_BYTE_TEXT 0x67000000 |
| 356 | #define BCI_CMD_BIT_TEXT 0x6C000000 |
| 357 | #define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF) |
| 358 | #define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16)) |
| 359 | #define BCI_CMD_SEND_COLOR 0x00008000 |
| 360 | |
| 361 | #define BCI_CMD_CLIP_NONE 0x00000000 |
| 362 | #define BCI_CMD_CLIP_CURRENT 0x00002000 |
| 363 | #define BCI_CMD_CLIP_LR 0x00004000 |
| 364 | #define BCI_CMD_CLIP_NEW 0x00006000 |
| 365 | |
| 366 | #define BCI_CMD_DEST_GBD 0x00000000 |
| 367 | #define BCI_CMD_DEST_PBD 0x00000800 |
| 368 | #define BCI_CMD_DEST_PBD_NEW 0x00000C00 |
| 369 | #define BCI_CMD_DEST_SBD 0x00001000 |
| 370 | #define BCI_CMD_DEST_SBD_NEW 0x00001400 |
| 371 | |
| 372 | #define BCI_CMD_SRC_TRANSPARENT 0x00000200 |
| 373 | #define BCI_CMD_SRC_SOLID 0x00000000 |
| 374 | #define BCI_CMD_SRC_GBD 0x00000020 |
| 375 | #define BCI_CMD_SRC_COLOR 0x00000040 |
| 376 | #define BCI_CMD_SRC_MONO 0x00000060 |
| 377 | #define BCI_CMD_SRC_PBD_COLOR 0x00000080 |
| 378 | #define BCI_CMD_SRC_PBD_MONO 0x000000A0 |
| 379 | #define BCI_CMD_SRC_PBD_COLOR_NEW 0x000000C0 |
| 380 | #define BCI_CMD_SRC_PBD_MONO_NEW 0x000000E0 |
| 381 | #define BCI_CMD_SRC_SBD_COLOR 0x00000100 |
| 382 | #define BCI_CMD_SRC_SBD_MONO 0x00000120 |
| 383 | #define BCI_CMD_SRC_SBD_COLOR_NEW 0x00000140 |
| 384 | #define BCI_CMD_SRC_SBD_MONO_NEW 0x00000160 |
| 385 | |
| 386 | #define BCI_CMD_PAT_TRANSPARENT 0x00000010 |
| 387 | #define BCI_CMD_PAT_NONE 0x00000000 |
| 388 | #define BCI_CMD_PAT_COLOR 0x00000002 |
| 389 | #define BCI_CMD_PAT_MONO 0x00000003 |
| 390 | #define BCI_CMD_PAT_PBD_COLOR 0x00000004 |
| 391 | #define BCI_CMD_PAT_PBD_MONO 0x00000005 |
| 392 | #define BCI_CMD_PAT_PBD_COLOR_NEW 0x00000006 |
| 393 | #define BCI_CMD_PAT_PBD_MONO_NEW 0x00000007 |
| 394 | #define BCI_CMD_PAT_SBD_COLOR 0x00000008 |
| 395 | #define BCI_CMD_PAT_SBD_MONO 0x00000009 |
| 396 | #define BCI_CMD_PAT_SBD_COLOR_NEW 0x0000000A |
| 397 | #define BCI_CMD_PAT_SBD_MONO_NEW 0x0000000B |
| 398 | |
| 399 | #define BCI_BD_BW_DISABLE 0x10000000 |
| 400 | #define BCI_BD_TILE_MASK 0x03000000 |
| 401 | #define BCI_BD_TILE_NONE 0x00000000 |
| 402 | #define BCI_BD_TILE_16 0x02000000 |
| 403 | #define BCI_BD_TILE_32 0x03000000 |
| 404 | #define BCI_BD_GET_BPP(bd) (((bd) >> 16) & 0xFF) |
| 405 | #define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16)) |
| 406 | #define BCI_BD_GET_STRIDE(bd) ((bd) & 0xFFFF) |
| 407 | #define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF)) |
| 408 | |
| 409 | #define BCI_CMD_SET_REGISTER 0x96000000 |
| 410 | |
| 411 | #define BCI_CMD_WAIT 0xC0000000 |
| 412 | #define BCI_CMD_WAIT_3D 0x00010000 |
| 413 | #define BCI_CMD_WAIT_2D 0x00020000 |
| 414 | |
| 415 | #define BCI_CMD_UPDATE_EVENT_TAG 0x98000000 |
| 416 | |
| 417 | #define BCI_CMD_DRAW_PRIM 0x80000000 |
| 418 | #define BCI_CMD_DRAW_INDEXED_PRIM 0x88000000 |
| 419 | #define BCI_CMD_DRAW_CONT 0x01000000 |
| 420 | #define BCI_CMD_DRAW_TRILIST 0x00000000 |
| 421 | #define BCI_CMD_DRAW_TRISTRIP 0x02000000 |
| 422 | #define BCI_CMD_DRAW_TRIFAN 0x04000000 |
| 423 | #define BCI_CMD_DRAW_SKIPFLAGS 0x000000ff |
| 424 | #define BCI_CMD_DRAW_NO_Z 0x00000001 |
| 425 | #define BCI_CMD_DRAW_NO_W 0x00000002 |
| 426 | #define BCI_CMD_DRAW_NO_CD 0x00000004 |
| 427 | #define BCI_CMD_DRAW_NO_CS 0x00000008 |
| 428 | #define BCI_CMD_DRAW_NO_U0 0x00000010 |
| 429 | #define BCI_CMD_DRAW_NO_V0 0x00000020 |
| 430 | #define BCI_CMD_DRAW_NO_UV0 0x00000030 |
| 431 | #define BCI_CMD_DRAW_NO_U1 0x00000040 |
| 432 | #define BCI_CMD_DRAW_NO_V1 0x00000080 |
| 433 | #define BCI_CMD_DRAW_NO_UV1 0x000000c0 |
| 434 | |
| 435 | #define BCI_CMD_DMA 0xa8000000 |
| 436 | |
| 437 | #define BCI_W_H(w, h) ((((h) << 16) | (w)) & 0x0FFF0FFF) |
| 438 | #define BCI_X_Y(x, y) ((((y) << 16) | (x)) & 0x0FFF0FFF) |
| 439 | #define BCI_X_W(x, y) ((((w) << 16) | (x)) & 0x0FFF0FFF) |
| 440 | #define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF) |
| 441 | #define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF) |
| 442 | #define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF) |
| 443 | |
| 444 | #define BCI_LINE_X_Y(x, y) (((y) << 16) | ((x) & 0xFFFF)) |
| 445 | #define BCI_LINE_STEPS(diag, axi) (((axi) << 16) | ((diag) & 0xFFFF)) |
| 446 | #define BCI_LINE_MISC(maj, ym, xp, yp, err) \ |
| 447 | (((maj) & 0x1FFF) | \ |
| 448 | ((ym) ? 1<<13 : 0) | \ |
| 449 | ((xp) ? 1<<14 : 0) | \ |
| 450 | ((yp) ? 1<<15 : 0) | \ |
| 451 | ((err) << 16)) |
| 452 | |
| 453 | /* |
| 454 | * common commands |
| 455 | */ |
| 456 | #define BCI_SET_REGISTERS( first, n ) \ |
| 457 | BCI_WRITE(BCI_CMD_SET_REGISTER | \ |
| 458 | ((uint32_t)(n) & 0xff) << 16 | \ |
| 459 | ((uint32_t)(first) & 0xffff)) |
| 460 | #define DMA_SET_REGISTERS( first, n ) \ |
| 461 | DMA_WRITE(BCI_CMD_SET_REGISTER | \ |
| 462 | ((uint32_t)(n) & 0xff) << 16 | \ |
| 463 | ((uint32_t)(first) & 0xffff)) |
| 464 | |
| 465 | #define BCI_DRAW_PRIMITIVE(n, type, skip) \ |
| 466 | BCI_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \ |
| 467 | ((n) << 16)) |
| 468 | #define DMA_DRAW_PRIMITIVE(n, type, skip) \ |
| 469 | DMA_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \ |
| 470 | ((n) << 16)) |
| 471 | |
| 472 | #define BCI_DRAW_INDICES_S3D(n, type, i0) \ |
| 473 | BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \ |
| 474 | ((n) << 16) | (i0)) |
| 475 | |
| 476 | #define BCI_DRAW_INDICES_S4(n, type, skip) \ |
| 477 | BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \ |
| 478 | (skip) | ((n) << 16)) |
| 479 | |
| 480 | #define BCI_DMA(n) \ |
| 481 | BCI_WRITE(BCI_CMD_DMA | (((n) >> 1) - 1)) |
| 482 | |
| 483 | /* |
| 484 | * access to MMIO |
| 485 | */ |
| 486 | #define SAVAGE_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) |
| 487 | #define SAVAGE_WRITE(reg) DRM_WRITE32( dev_priv->mmio, (reg) ) |
| 488 | |
| 489 | /* |
| 490 | * access to the burst command interface (BCI) |
| 491 | */ |
| 492 | #define SAVAGE_BCI_DEBUG 1 |
| 493 | |
| 494 | #define BCI_LOCALS volatile uint32_t *bci_ptr; |
| 495 | |
| 496 | #define BEGIN_BCI( n ) do { \ |
| 497 | dev_priv->wait_fifo(dev_priv, (n)); \ |
| 498 | bci_ptr = dev_priv->bci_ptr; \ |
| 499 | } while(0) |
| 500 | |
| 501 | #define BCI_WRITE( val ) *bci_ptr++ = (uint32_t)(val) |
| 502 | |
| 503 | #define BCI_COPY_FROM_USER(src,n) do { \ |
| 504 | unsigned int i; \ |
| 505 | for (i = 0; i < n; ++i) { \ |
| 506 | uint32_t val; \ |
| 507 | DRM_GET_USER_UNCHECKED(val, &((uint32_t*)(src))[i]); \ |
| 508 | BCI_WRITE(val); \ |
| 509 | } \ |
| 510 | } while(0) |
| 511 | |
| 512 | /* |
| 513 | * command DMA support |
| 514 | */ |
| 515 | #define SAVAGE_DMA_DEBUG 1 |
| 516 | |
| 517 | #define DMA_LOCALS uint32_t *dma_ptr; |
| 518 | |
| 519 | #define BEGIN_DMA( n ) do { \ |
| 520 | unsigned int cur = dev_priv->current_dma_page; \ |
| 521 | unsigned int rest = SAVAGE_DMA_PAGE_SIZE - \ |
| 522 | dev_priv->dma_pages[cur].used; \ |
| 523 | if ((n) > rest) { \ |
| 524 | dma_ptr = savage_dma_alloc(dev_priv, (n)); \ |
| 525 | } else { /* fast path for small allocations */ \ |
| 526 | dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + \ |
| 527 | cur * SAVAGE_DMA_PAGE_SIZE + \ |
| 528 | dev_priv->dma_pages[cur].used; \ |
| 529 | if (dev_priv->dma_pages[cur].used == 0) \ |
| 530 | savage_dma_wait(dev_priv, cur); \ |
| 531 | dev_priv->dma_pages[cur].used += (n); \ |
| 532 | } \ |
| 533 | } while(0) |
| 534 | |
| 535 | #define DMA_WRITE( val ) *dma_ptr++ = (uint32_t)(val) |
| 536 | |
| 537 | #define DMA_COPY_FROM_USER(src,n) do { \ |
| 538 | DRM_COPY_FROM_USER_UNCHECKED(dma_ptr, (src), (n)*4); \ |
| 539 | dma_ptr += n; \ |
| 540 | } while(0) |
| 541 | |
| 542 | #if SAVAGE_DMA_DEBUG |
| 543 | #define DMA_COMMIT() do { \ |
| 544 | unsigned int cur = dev_priv->current_dma_page; \ |
| 545 | uint32_t *expected = (uint32_t *)dev_priv->cmd_dma->handle + \ |
| 546 | cur * SAVAGE_DMA_PAGE_SIZE + \ |
| 547 | dev_priv->dma_pages[cur].used; \ |
| 548 | if (dma_ptr != expected) { \ |
| 549 | DRM_ERROR("DMA allocation and use don't match: " \ |
| 550 | "%p != %p\n", expected, dma_ptr); \ |
| 551 | savage_dma_reset(dev_priv); \ |
| 552 | } \ |
| 553 | } while(0) |
| 554 | #else |
| 555 | #define DMA_COMMIT() do {/* nothing */} while(0) |
| 556 | #endif |
| 557 | |
| 558 | #define DMA_FLUSH() dev_priv->dma_flush(dev_priv) |
| 559 | |
| 560 | /* Buffer aging via event tag |
| 561 | */ |
| 562 | |
| 563 | #define UPDATE_EVENT_COUNTER( ) do { \ |
| 564 | if (dev_priv->status_ptr) { \ |
| 565 | uint16_t count; \ |
| 566 | /* coordinate with Xserver */ \ |
| 567 | count = dev_priv->status_ptr[1023]; \ |
| 568 | if (count < dev_priv->event_counter) \ |
| 569 | dev_priv->event_wrap++; \ |
| 570 | dev_priv->event_counter = count; \ |
| 571 | } \ |
| 572 | } while(0) |
| 573 | |
| 574 | #define SET_AGE( age, e, w ) do { \ |
| 575 | (age)->event = e; \ |
| 576 | (age)->wrap = w; \ |
| 577 | } while(0) |
| 578 | |
| 579 | #define TEST_AGE( age, e, w ) \ |
| 580 | ( (age)->wrap < (w) || ( (age)->wrap == (w) && (age)->event <= (e) ) ) |
| 581 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 582 | #endif /* __SAVAGE_DRV_H__ */ |