Harald Welte | aa9ad6a | 2009-12-01 01:24:34 +0000 | [diff] [blame] | 1 | /* linux/arch/arm/plat-samsung/clock-clksrc.c |
| 2 | * |
| 3 | * Copyright 2008 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * http://armlinux.simtec.co.uk/ |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/list.h> |
| 16 | #include <linux/errno.h> |
| 17 | #include <linux/err.h> |
| 18 | #include <linux/clk.h> |
| 19 | #include <linux/sysdev.h> |
| 20 | #include <linux/io.h> |
| 21 | |
| 22 | #include <plat/clock.h> |
| 23 | #include <plat/clock-clksrc.h> |
| 24 | #include <plat/cpu-freq.h> |
| 25 | |
| 26 | static inline struct clksrc_clk *to_clksrc(struct clk *clk) |
| 27 | { |
| 28 | return container_of(clk, struct clksrc_clk, clk); |
| 29 | } |
| 30 | |
| 31 | static inline u32 bit_mask(u32 shift, u32 nr_bits) |
| 32 | { |
| 33 | u32 mask = 0xffffffff >> (32 - nr_bits); |
| 34 | |
| 35 | return mask << shift; |
| 36 | } |
| 37 | |
| 38 | static unsigned long s3c_getrate_clksrc(struct clk *clk) |
| 39 | { |
| 40 | struct clksrc_clk *sclk = to_clksrc(clk); |
| 41 | unsigned long rate = clk_get_rate(clk->parent); |
| 42 | u32 clkdiv = __raw_readl(sclk->reg_div.reg); |
| 43 | u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size); |
| 44 | |
| 45 | clkdiv &= mask; |
| 46 | clkdiv >>= sclk->reg_div.shift; |
| 47 | clkdiv++; |
| 48 | |
| 49 | rate /= clkdiv; |
| 50 | return rate; |
| 51 | } |
| 52 | |
| 53 | static int s3c_setrate_clksrc(struct clk *clk, unsigned long rate) |
| 54 | { |
| 55 | struct clksrc_clk *sclk = to_clksrc(clk); |
| 56 | void __iomem *reg = sclk->reg_div.reg; |
| 57 | unsigned int div; |
| 58 | u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size); |
| 59 | u32 val; |
| 60 | |
| 61 | rate = clk_round_rate(clk, rate); |
| 62 | div = clk_get_rate(clk->parent) / rate; |
| 63 | if (div > 16) |
| 64 | return -EINVAL; |
| 65 | |
| 66 | val = __raw_readl(reg); |
| 67 | val &= ~mask; |
| 68 | val |= (div - 1) << sclk->reg_div.shift; |
| 69 | __raw_writel(val, reg); |
| 70 | |
| 71 | return 0; |
| 72 | } |
| 73 | |
| 74 | static int s3c_setparent_clksrc(struct clk *clk, struct clk *parent) |
| 75 | { |
| 76 | struct clksrc_clk *sclk = to_clksrc(clk); |
| 77 | struct clksrc_sources *srcs = sclk->sources; |
| 78 | u32 clksrc = __raw_readl(sclk->reg_src.reg); |
| 79 | u32 mask = bit_mask(sclk->reg_src.shift, sclk->reg_src.size); |
| 80 | int src_nr = -1; |
| 81 | int ptr; |
| 82 | |
| 83 | for (ptr = 0; ptr < srcs->nr_sources; ptr++) |
| 84 | if (srcs->sources[ptr] == parent) { |
| 85 | src_nr = ptr; |
| 86 | break; |
| 87 | } |
| 88 | |
| 89 | if (src_nr >= 0 && sclk->reg_src.reg) { |
| 90 | clk->parent = parent; |
| 91 | |
| 92 | clksrc &= ~mask; |
| 93 | clksrc |= src_nr << sclk->reg_src.shift; |
| 94 | |
| 95 | __raw_writel(clksrc, sclk->reg_src.reg); |
| 96 | return 0; |
| 97 | } |
| 98 | |
| 99 | return -EINVAL; |
| 100 | } |
| 101 | |
| 102 | static unsigned long s3c_roundrate_clksrc(struct clk *clk, |
| 103 | unsigned long rate) |
| 104 | { |
| 105 | unsigned long parent_rate = clk_get_rate(clk->parent); |
| 106 | int div; |
| 107 | |
| 108 | if (rate >= parent_rate) |
| 109 | rate = parent_rate; |
| 110 | else { |
| 111 | div = parent_rate / rate; |
| 112 | if (parent_rate % rate) |
| 113 | div++; |
| 114 | |
| 115 | if (div == 0) |
| 116 | div = 1; |
| 117 | if (div > 16) |
| 118 | div = 16; |
| 119 | |
| 120 | rate = parent_rate / div; |
| 121 | } |
| 122 | |
| 123 | return rate; |
| 124 | } |
| 125 | |
| 126 | /* Clock initialisation code */ |
| 127 | |
| 128 | void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk) |
| 129 | { |
| 130 | struct clksrc_sources *srcs = clk->sources; |
| 131 | u32 mask = bit_mask(clk->reg_src.shift, clk->reg_src.size); |
| 132 | u32 clksrc = 0; |
| 133 | |
| 134 | if (clk->reg_src.reg) |
| 135 | clksrc = __raw_readl(clk->reg_src.reg); |
| 136 | |
| 137 | clksrc &= mask; |
| 138 | clksrc >>= clk->reg_src.shift; |
| 139 | |
| 140 | if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) { |
| 141 | printk(KERN_ERR "%s: bad source %d\n", |
| 142 | clk->clk.name, clksrc); |
| 143 | return; |
| 144 | } |
| 145 | |
| 146 | clk->clk.parent = srcs->sources[clksrc]; |
| 147 | |
| 148 | printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", |
| 149 | clk->clk.name, clk->clk.parent->name, clksrc, |
| 150 | clk_get_rate(&clk->clk)); |
| 151 | } |
| 152 | |
Ben Dooks | b3bf41b | 2009-12-01 01:24:37 +0000 | [diff] [blame^] | 153 | static struct clk_ops clksrc_ops = { |
| 154 | .set_parent = s3c_setparent_clksrc, |
| 155 | .get_rate = s3c_getrate_clksrc, |
| 156 | .set_rate = s3c_setrate_clksrc, |
| 157 | .round_rate = s3c_roundrate_clksrc, |
| 158 | }; |
| 159 | |
Harald Welte | aa9ad6a | 2009-12-01 01:24:34 +0000 | [diff] [blame] | 160 | void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size) |
| 161 | { |
| 162 | int ret; |
| 163 | |
| 164 | for (; size > 0; size--, clksrc++) { |
| 165 | /* fill in the default functions */ |
Ben Dooks | b3bf41b | 2009-12-01 01:24:37 +0000 | [diff] [blame^] | 166 | if (!clksrc->clk.ops) |
| 167 | clksrc->clk.ops = &clksrc_ops; |
Harald Welte | aa9ad6a | 2009-12-01 01:24:34 +0000 | [diff] [blame] | 168 | |
| 169 | s3c_set_clksrc(clksrc); |
| 170 | |
| 171 | ret = s3c24xx_register_clock(&clksrc->clk); |
| 172 | |
| 173 | if (ret < 0) { |
| 174 | printk(KERN_ERR "%s: failed to register %s (%d)\n", |
| 175 | __func__, clksrc->clk.name, ret); |
| 176 | } |
| 177 | } |
| 178 | } |