blob: 9c05f381d95e0f700ee7ebaa956deb24a80e0710 [file] [log] [blame]
Manuel Laussb3c70c92011-07-25 13:44:45 +02001/*
2 * Au1000/Au1500/Au1100 AC97C controller driver for ASoC
3 *
4 * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com>
5 *
6 * based on the old ALSA driver originally written by
7 * Charles Eidsness <charles@cooper-street.com>
8 */
9
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/slab.h>
13#include <linux/device.h>
14#include <linux/delay.h>
15#include <linux/mutex.h>
16#include <linux/platform_device.h>
17#include <linux/suspend.h>
18#include <sound/core.h>
19#include <sound/pcm.h>
20#include <sound/initval.h>
21#include <sound/soc.h>
22#include <asm/mach-au1x00/au1000.h>
23
24#include "psc.h"
25
26/* register offsets and bits */
27#define AC97_CONFIG 0x00
28#define AC97_STATUS 0x04
29#define AC97_DATA 0x08
30#define AC97_CMDRESP 0x0c
31#define AC97_ENABLE 0x10
32
33#define CFG_RC(x) (((x) & 0x3ff) << 13) /* valid rx slots mask */
34#define CFG_XS(x) (((x) & 0x3ff) << 3) /* valid tx slots mask */
35#define CFG_SG (1 << 2) /* sync gate */
36#define CFG_SN (1 << 1) /* sync control */
37#define CFG_RS (1 << 0) /* acrst# control */
38#define STAT_XU (1 << 11) /* tx underflow */
39#define STAT_XO (1 << 10) /* tx overflow */
40#define STAT_RU (1 << 9) /* rx underflow */
41#define STAT_RO (1 << 8) /* rx overflow */
42#define STAT_RD (1 << 7) /* codec ready */
43#define STAT_CP (1 << 6) /* command pending */
44#define STAT_TE (1 << 4) /* tx fifo empty */
45#define STAT_TF (1 << 3) /* tx fifo full */
46#define STAT_RE (1 << 1) /* rx fifo empty */
47#define STAT_RF (1 << 0) /* rx fifo full */
48#define CMD_SET_DATA(x) (((x) & 0xffff) << 16)
49#define CMD_GET_DATA(x) ((x) & 0xffff)
50#define CMD_READ (1 << 7)
51#define CMD_WRITE (0 << 7)
52#define CMD_IDX(x) ((x) & 0x7f)
53#define EN_D (1 << 1) /* DISable bit */
54#define EN_CE (1 << 0) /* clock enable bit */
55
56/* how often to retry failed codec register reads/writes */
57#define AC97_RW_RETRIES 5
58
59#define AC97_RATES \
60 SNDRV_PCM_RATE_CONTINUOUS
61
62#define AC97_FMTS \
63 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE)
64
65/* instance data. There can be only one, MacLeod!!!!, fortunately there IS only
66 * once AC97C on early Alchemy chips. The newer ones aren't so lucky.
67 */
68static struct au1xpsc_audio_data *ac97c_workdata;
69#define ac97_to_ctx(x) ac97c_workdata
70
71static inline unsigned long RD(struct au1xpsc_audio_data *ctx, int reg)
72{
73 return __raw_readl(ctx->mmio + reg);
74}
75
76static inline void WR(struct au1xpsc_audio_data *ctx, int reg, unsigned long v)
77{
78 __raw_writel(v, ctx->mmio + reg);
79 wmb();
80}
81
82static unsigned short au1xac97c_ac97_read(struct snd_ac97 *ac97,
83 unsigned short r)
84{
85 struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
86 unsigned int tmo, retry;
87 unsigned long data;
88
89 data = ~0;
90 retry = AC97_RW_RETRIES;
91 do {
92 mutex_lock(&ctx->lock);
93
94 tmo = 5;
95 while ((RD(ctx, AC97_STATUS) & STAT_CP) && tmo--)
96 udelay(21); /* wait an ac97 frame time */
97 if (!tmo) {
98 pr_debug("ac97rd timeout #1\n");
99 goto next;
100 }
101
102 WR(ctx, AC97_CMDRESP, CMD_IDX(r) | CMD_READ);
103
104 /* stupid errata: data is only valid for 21us, so
105 * poll, Forrest, poll...
106 */
107 tmo = 0x10000;
108 while ((RD(ctx, AC97_STATUS) & STAT_CP) && tmo--)
109 asm volatile ("nop");
110 data = RD(ctx, AC97_CMDRESP);
111
112 if (!tmo)
113 pr_debug("ac97rd timeout #2\n");
114
115next:
116 mutex_unlock(&ctx->lock);
117 } while (--retry && !tmo);
118
119 pr_debug("AC97RD %04x %04lx %d\n", r, data, retry);
120
121 return retry ? data & 0xffff : 0xffff;
122}
123
124static void au1xac97c_ac97_write(struct snd_ac97 *ac97, unsigned short r,
125 unsigned short v)
126{
127 struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
128 unsigned int tmo, retry;
129
130 retry = AC97_RW_RETRIES;
131 do {
132 mutex_lock(&ctx->lock);
133
134 for (tmo = 5; (RD(ctx, AC97_STATUS) & STAT_CP) && tmo; tmo--)
135 udelay(21);
136 if (!tmo) {
137 pr_debug("ac97wr timeout #1\n");
138 goto next;
139 }
140
141 WR(ctx, AC97_CMDRESP, CMD_WRITE | CMD_IDX(r) | CMD_SET_DATA(v));
142
143 for (tmo = 10; (RD(ctx, AC97_STATUS) & STAT_CP) && tmo; tmo--)
144 udelay(21);
145 if (!tmo)
146 pr_debug("ac97wr timeout #2\n");
147next:
148 mutex_unlock(&ctx->lock);
149 } while (--retry && !tmo);
150
151 pr_debug("AC97WR %04x %04x %d\n", r, v, retry);
152}
153
154static void au1xac97c_ac97_warm_reset(struct snd_ac97 *ac97)
155{
156 struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
157
158 WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG | CFG_SN);
159 msleep(20);
160 WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG);
161 WR(ctx, AC97_CONFIG, ctx->cfg);
162}
163
164static void au1xac97c_ac97_cold_reset(struct snd_ac97 *ac97)
165{
166 struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
167 int i;
168
169 WR(ctx, AC97_CONFIG, ctx->cfg | CFG_RS);
170 msleep(500);
171 WR(ctx, AC97_CONFIG, ctx->cfg);
172
173 /* wait for codec ready */
174 i = 50;
175 while (((RD(ctx, AC97_STATUS) & STAT_RD) == 0) && --i)
176 msleep(20);
177 if (!i)
178 printk(KERN_ERR "ac97c: codec not ready after cold reset\n");
179}
180
181/* AC97 controller operations */
182struct snd_ac97_bus_ops soc_ac97_ops = {
183 .read = au1xac97c_ac97_read,
184 .write = au1xac97c_ac97_write,
185 .reset = au1xac97c_ac97_cold_reset,
186 .warm_reset = au1xac97c_ac97_warm_reset,
187};
188EXPORT_SYMBOL_GPL(soc_ac97_ops); /* globals be gone! */
189
190static int alchemy_ac97c_startup(struct snd_pcm_substream *substream,
191 struct snd_soc_dai *dai)
192{
193 struct au1xpsc_audio_data *ctx = snd_soc_dai_get_drvdata(dai);
194 snd_soc_dai_set_dma_data(dai, substream, &ctx->dmaids[0]);
195 return 0;
196}
197
198static struct snd_soc_dai_ops alchemy_ac97c_ops = {
199 .startup = alchemy_ac97c_startup,
200};
201
202static int au1xac97c_dai_probe(struct snd_soc_dai *dai)
203{
204 return ac97c_workdata ? 0 : -ENODEV;
205}
206
207static struct snd_soc_dai_driver au1xac97c_dai_driver = {
208 .name = "alchemy-ac97c",
209 .ac97_control = 1,
210 .probe = au1xac97c_dai_probe,
211 .playback = {
212 .rates = AC97_RATES,
213 .formats = AC97_FMTS,
214 .channels_min = 2,
215 .channels_max = 2,
216 },
217 .capture = {
218 .rates = AC97_RATES,
219 .formats = AC97_FMTS,
220 .channels_min = 2,
221 .channels_max = 2,
222 },
223 .ops = &alchemy_ac97c_ops,
224};
225
226static int __devinit au1xac97c_drvprobe(struct platform_device *pdev)
227{
228 int ret;
229 struct resource *r;
230 struct au1xpsc_audio_data *ctx;
231
232 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
233 if (!ctx)
234 return -ENOMEM;
235
236 mutex_init(&ctx->lock);
237
238 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
239 if (!r) {
240 ret = -ENODEV;
241 goto out0;
242 }
243
244 ret = -EBUSY;
245 if (!request_mem_region(r->start, resource_size(r), pdev->name))
246 goto out0;
247
248 ctx->mmio = ioremap_nocache(r->start, resource_size(r));
249 if (!ctx->mmio)
250 goto out1;
251
252 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
253 if (!r)
254 goto out1;
255 ctx->dmaids[SNDRV_PCM_STREAM_PLAYBACK] = r->start;
256
257 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
258 if (!r)
259 goto out1;
260 ctx->dmaids[SNDRV_PCM_STREAM_CAPTURE] = r->start;
261
262 /* switch it on */
263 WR(ctx, AC97_ENABLE, EN_D | EN_CE);
264 WR(ctx, AC97_ENABLE, EN_CE);
265
266 ctx->cfg = CFG_RC(3) | CFG_XS(3);
267 WR(ctx, AC97_CONFIG, ctx->cfg);
268
269 platform_set_drvdata(pdev, ctx);
270
271 ret = snd_soc_register_dai(&pdev->dev, &au1xac97c_dai_driver);
272 if (ret)
273 goto out1;
274
275 ac97c_workdata = ctx;
276 return 0;
277
278
279 snd_soc_unregister_dai(&pdev->dev);
280out1:
281 release_mem_region(r->start, resource_size(r));
282out0:
283 kfree(ctx);
284 return ret;
285}
286
287static int __devexit au1xac97c_drvremove(struct platform_device *pdev)
288{
289 struct au1xpsc_audio_data *ctx = platform_get_drvdata(pdev);
290 struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
291
292 snd_soc_unregister_dai(&pdev->dev);
293
294 WR(ctx, AC97_ENABLE, EN_D); /* clock off, disable */
295
296 iounmap(ctx->mmio);
297 release_mem_region(r->start, resource_size(r));
298 kfree(ctx);
299
300 ac97c_workdata = NULL; /* MDEV */
301
302 return 0;
303}
304
305#ifdef CONFIG_PM
306static int au1xac97c_drvsuspend(struct device *dev)
307{
308 struct au1xpsc_audio_data *ctx = dev_get_drvdata(dev);
309
310 WR(ctx, AC97_ENABLE, EN_D); /* clock off, disable */
311
312 return 0;
313}
314
315static int au1xac97c_drvresume(struct device *dev)
316{
317 struct au1xpsc_audio_data *ctx = dev_get_drvdata(dev);
318
319 WR(ctx, AC97_ENABLE, EN_D | EN_CE);
320 WR(ctx, AC97_ENABLE, EN_CE);
321 WR(ctx, AC97_CONFIG, ctx->cfg);
322
323 return 0;
324}
325
326static const struct dev_pm_ops au1xpscac97_pmops = {
327 .suspend = au1xac97c_drvsuspend,
328 .resume = au1xac97c_drvresume,
329};
330
331#define AU1XPSCAC97_PMOPS (&au1xpscac97_pmops)
332
333#else
334
335#define AU1XPSCAC97_PMOPS NULL
336
337#endif
338
339static struct platform_driver au1xac97c_driver = {
340 .driver = {
341 .name = "alchemy-ac97c",
342 .owner = THIS_MODULE,
343 .pm = AU1XPSCAC97_PMOPS,
344 },
345 .probe = au1xac97c_drvprobe,
346 .remove = __devexit_p(au1xac97c_drvremove),
347};
348
349static int __init au1xac97c_load(void)
350{
351 ac97c_workdata = NULL;
352 return platform_driver_register(&au1xac97c_driver);
353}
354
355static void __exit au1xac97c_unload(void)
356{
357 platform_driver_unregister(&au1xac97c_driver);
358}
359
360module_init(au1xac97c_load);
361module_exit(au1xac97c_unload);
362
363MODULE_LICENSE("GPL");
364MODULE_DESCRIPTION("Au1000/1500/1100 AC97C ASoC driver");
365MODULE_AUTHOR("Manuel Lauss");