| Ruud Derwig | 2924cd1 | 2014-12-03 15:52:41 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com) |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | |
| 9 | /* |
| 10 | * Device tree for AXC003 CPU card: |
| 11 | * HS38x2 (Dual Core) with IDU intc (VDK version) |
| 12 | */ |
| 13 | |
| Vineet Gupta | 2e8cd93 | 2016-01-19 16:00:42 +0530 | [diff] [blame] | 14 | /include/ "skeleton_hs_idu.dtsi" |
| 15 | |
| Ruud Derwig | 2924cd1 | 2014-12-03 15:52:41 +0100 | [diff] [blame] | 16 | / { |
| 17 | compatible = "snps,arc"; |
| 18 | clock-frequency = <50000000>; |
| 19 | #address-cells = <1>; |
| 20 | #size-cells = <1>; |
| 21 | |
| 22 | cpu_card { |
| 23 | compatible = "simple-bus"; |
| 24 | #address-cells = <1>; |
| 25 | #size-cells = <1>; |
| 26 | |
| 27 | ranges = <0x00000000 0xf0000000 0x10000000>; |
| 28 | |
| Vineet Gupta | b3d6aba | 2016-01-01 18:48:40 +0530 | [diff] [blame^] | 29 | core_clk: core_clk { |
| 30 | #clock-cells = <0>; |
| 31 | compatible = "fixed-clock"; |
| 32 | clock-frequency = <50000000>; |
| 33 | }; |
| 34 | |
| Vineet Gupta | 9ba7648 | 2016-01-28 09:57:12 +0530 | [diff] [blame] | 35 | core_intc: archs-intc@cpu { |
| Ruud Derwig | 2924cd1 | 2014-12-03 15:52:41 +0100 | [diff] [blame] | 36 | compatible = "snps,archs-intc"; |
| 37 | interrupt-controller; |
| 38 | #interrupt-cells = <1>; |
| 39 | }; |
| 40 | |
| 41 | idu_intc: idu-interrupt-controller { |
| 42 | compatible = "snps,archs-idu-intc"; |
| 43 | interrupt-controller; |
| Vineet Gupta | 9ba7648 | 2016-01-28 09:57:12 +0530 | [diff] [blame] | 44 | interrupt-parent = <&core_intc>; |
| Ruud Derwig | 2924cd1 | 2014-12-03 15:52:41 +0100 | [diff] [blame] | 45 | |
| 46 | /* |
| 47 | * <hwirq distribution> |
| 48 | * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 |
| 49 | */ |
| 50 | #interrupt-cells = <2>; |
| 51 | |
| 52 | interrupts = <24 25 26 27>; |
| 53 | }; |
| 54 | |
| 55 | debug_uart: dw-apb-uart@0x5000 { |
| 56 | compatible = "snps,dw-apb-uart"; |
| 57 | reg = <0x5000 0x100>; |
| 58 | clock-frequency = <2403200>; |
| 59 | interrupt-parent = <&idu_intc>; |
| 60 | interrupts = <2 0>; |
| 61 | baud = <115200>; |
| 62 | reg-shift = <2>; |
| 63 | reg-io-width = <4>; |
| 64 | }; |
| 65 | |
| 66 | }; |
| 67 | |
| 68 | mb_intc: dw-apb-ictl@0xe0012000 { |
| 69 | #interrupt-cells = <1>; |
| 70 | compatible = "snps,dw-apb-ictl"; |
| 71 | reg = < 0xe0012000 0x200 >; |
| 72 | interrupt-controller; |
| 73 | interrupt-parent = <&idu_intc>; |
| 74 | interrupts = < 0 0 >; |
| 75 | }; |
| 76 | |
| 77 | memory { |
| 78 | #address-cells = <1>; |
| 79 | #size-cells = <1>; |
| 80 | ranges = <0x00000000 0x80000000 0x40000000>; |
| 81 | device_type = "memory"; |
| Vineet Gupta | f759ee5 | 2015-01-23 18:10:26 +0530 | [diff] [blame] | 82 | reg = <0x80000000 0x20000000>; /* 512MiB */ |
| Ruud Derwig | 2924cd1 | 2014-12-03 15:52:41 +0100 | [diff] [blame] | 83 | }; |
| 84 | }; |