Pekka Enberg | 80aba53 | 2008-10-30 13:04:29 +0200 | [diff] [blame] | 1 | #ifndef __WINBOND_WB35REG_S_H |
| 2 | #define __WINBOND_WB35REG_S_H |
| 3 | |
| 4 | #include <linux/spinlock.h> |
| 5 | #include <linux/types.h> |
| 6 | #include <asm/atomic.h> |
| 7 | |
Pavel Machek | 66101de | 2008-10-01 14:36:56 +0200 | [diff] [blame] | 8 | //======================================================================================= |
| 9 | /* |
| 10 | HAL setting function |
| 11 | |
| 12 | ======================================== |
| 13 | |Uxx| |Dxx| |Mxx| |BB| |RF| |
| 14 | ======================================== |
| 15 | | | |
| 16 | Wb35Reg_Read Wb35Reg_Write |
| 17 | |
| 18 | ---------------------------------------- |
| 19 | WbUsb_CallUSBDASync supplied By WbUsb module |
| 20 | */ |
| 21 | //======================================================================================= |
| 22 | |
| 23 | #define GetBit( dwData, i) ( dwData & (0x00000001 << i)) |
| 24 | #define SetBit( dwData, i) ( dwData | (0x00000001 << i)) |
| 25 | #define ClearBit( dwData, i) ( dwData & ~(0x00000001 << i)) |
| 26 | |
| 27 | #define IGNORE_INCREMENT 0 |
| 28 | #define AUTO_INCREMENT 0 |
| 29 | #define NO_INCREMENT 1 |
| 30 | #define REG_DIRECTION(_x,_y) ((_y)->DIRECT ==0 ? usb_rcvctrlpipe(_x,0) : usb_sndctrlpipe(_x,0)) |
| 31 | #define REG_BUF_SIZE(_x) ((_x)->bRequest== 0x04 ? cpu_to_le16((_x)->wLength) : 4) |
| 32 | |
| 33 | // 20060613.2 Add the follow definition |
| 34 | #define BB48_DEFAULT_AL2230_11B 0x0033447c |
| 35 | #define BB4C_DEFAULT_AL2230_11B 0x0A00FEFF |
| 36 | #define BB48_DEFAULT_AL2230_11G 0x00332C1B |
| 37 | #define BB4C_DEFAULT_AL2230_11G 0x0A00FEFF |
| 38 | |
| 39 | |
| 40 | #define BB48_DEFAULT_WB242_11B 0x00292315 //backoff 2dB |
| 41 | #define BB4C_DEFAULT_WB242_11B 0x0800FEFF //backoff 2dB |
| 42 | //#define BB48_DEFAULT_WB242_11B 0x00201B11 //backoff 4dB |
| 43 | //#define BB4C_DEFAULT_WB242_11B 0x0600FF00 //backoff 4dB |
| 44 | #define BB48_DEFAULT_WB242_11G 0x00453B24 |
| 45 | #define BB4C_DEFAULT_WB242_11G 0x0E00FEFF |
| 46 | |
| 47 | //==================================== |
| 48 | // Default setting for Mxx |
| 49 | //==================================== |
| 50 | #define DEFAULT_CWMIN 31 //(M2C) CWmin. Its value is in the range 0-31. |
| 51 | #define DEFAULT_CWMAX 1023 //(M2C) CWmax. Its value is in the range 0-1023. |
| 52 | #define DEFAULT_AID 1 //(M34) AID. Its value is in the range 1-2007. |
| 53 | |
| 54 | #ifdef _USE_FALLBACK_RATE_ |
| 55 | #define DEFAULT_RATE_RETRY_LIMIT 2 //(M38) as named |
| 56 | #else |
| 57 | #define DEFAULT_RATE_RETRY_LIMIT 7 //(M38) as named |
| 58 | #endif |
| 59 | |
| 60 | #define DEFAULT_LONG_RETRY_LIMIT 7 //(M38) LongRetryLimit. Its value is in the range 0-15. |
| 61 | #define DEFAULT_SHORT_RETRY_LIMIT 7 //(M38) ShortRetryLimit. Its value is in the range 0-15. |
| 62 | #define DEFAULT_PIFST 25 //(M3C) PIFS Time. Its value is in the range 0-65535. |
| 63 | #define DEFAULT_EIFST 354 //(M3C) EIFS Time. Its value is in the range 0-1048575. |
| 64 | #define DEFAULT_DIFST 45 //(M3C) DIFS Time. Its value is in the range 0-65535. |
| 65 | #define DEFAULT_SIFST 5 //(M3C) SIFS Time. Its value is in the range 0-65535. |
| 66 | #define DEFAULT_OSIFST 10 //(M3C) Original SIFS Time. Its value is in the range 0-15. |
| 67 | #define DEFAULT_ATIMWD 0 //(M40) ATIM Window. Its value is in the range 0-65535. |
| 68 | #define DEFAULT_SLOT_TIME 20 //(M40) ($) SlotTime. Its value is in the range 0-255. |
| 69 | #define DEFAULT_MAX_TX_MSDU_LIFE_TIME 512 //(M44) MaxTxMSDULifeTime. Its value is in the range 0-4294967295. |
| 70 | #define DEFAULT_BEACON_INTERVAL 500 //(M48) Beacon Interval. Its value is in the range 0-65535. |
| 71 | #define DEFAULT_PROBE_DELAY_TIME 200 //(M48) Probe Delay Time. Its value is in the range 0-65535. |
| 72 | #define DEFAULT_PROTOCOL_VERSION 0 //(M4C) |
| 73 | #define DEFAULT_MAC_POWER_STATE 2 //(M4C) 2: MAC at power active |
| 74 | #define DEFAULT_DTIM_ALERT_TIME 0 |
| 75 | |
| 76 | |
Pekka Enberg | f37435c | 2008-10-22 11:01:47 +0300 | [diff] [blame] | 77 | struct wb35_reg_queue { |
| 78 | struct urb *urb; |
| 79 | void *pUsbReq; |
| 80 | void *Next; |
| 81 | union { |
Pavel Machek | 66101de | 2008-10-01 14:36:56 +0200 | [diff] [blame] | 82 | u32 VALUE; |
Pekka Enberg | f37435c | 2008-10-22 11:01:47 +0300 | [diff] [blame] | 83 | u32 *pBuffer; |
Pavel Machek | 66101de | 2008-10-01 14:36:56 +0200 | [diff] [blame] | 84 | }; |
Pekka Enberg | f37435c | 2008-10-22 11:01:47 +0300 | [diff] [blame] | 85 | u8 RESERVED[4]; // space reserved for communication |
| 86 | u16 INDEX; // For storing the register index |
| 87 | u8 RESERVED_VALID; // Indicate whether the RESERVED space is valid at this command. |
| 88 | u8 DIRECT; // 0:In 1:Out |
| 89 | }; |
Pavel Machek | 66101de | 2008-10-01 14:36:56 +0200 | [diff] [blame] | 90 | |
| 91 | //==================================== |
| 92 | // Internal variable for module |
| 93 | //==================================== |
| 94 | #define MAX_SQ3_FILTER_SIZE 5 |
Pekka Enberg | 65144de | 2008-10-22 11:02:37 +0300 | [diff] [blame] | 95 | struct wb35_reg { |
Pavel Machek | 66101de | 2008-10-01 14:36:56 +0200 | [diff] [blame] | 96 | //============================ |
| 97 | // Register Bank backup |
| 98 | //============================ |
| 99 | u32 U1B0; //bit16 record the h/w radio on/off status |
| 100 | u32 U1BC_LEDConfigure; |
| 101 | u32 D00_DmaControl; |
| 102 | u32 M00_MacControl; |
| 103 | union { |
| 104 | struct { |
| 105 | u32 M04_MulticastAddress1; |
| 106 | u32 M08_MulticastAddress2; |
| 107 | }; |
| 108 | u8 Multicast[8]; // contents of card multicast registers |
| 109 | }; |
| 110 | |
| 111 | u32 M24_MacControl; |
| 112 | u32 M28_MacControl; |
| 113 | u32 M2C_MacControl; |
| 114 | u32 M38_MacControl; |
| 115 | u32 M3C_MacControl; // 20060214 backup only |
| 116 | u32 M40_MacControl; |
| 117 | u32 M44_MacControl; // 20060214 backup only |
| 118 | u32 M48_MacControl; // 20060214 backup only |
| 119 | u32 M4C_MacStatus; |
| 120 | u32 M60_MacControl; // 20060214 backup only |
| 121 | u32 M68_MacControl; // 20060214 backup only |
| 122 | u32 M70_MacControl; // 20060214 backup only |
| 123 | u32 M74_MacControl; // 20060214 backup only |
| 124 | u32 M78_ERPInformation;//930206.2.b |
| 125 | u32 M7C_MacControl; // 20060214 backup only |
| 126 | u32 M80_MacControl; // 20060214 backup only |
| 127 | u32 M84_MacControl; // 20060214 backup only |
| 128 | u32 M88_MacControl; // 20060214 backup only |
| 129 | u32 M98_MacControl; // 20060214 backup only |
| 130 | |
| 131 | //[20040722 WK] |
| 132 | //Baseband register |
| 133 | u32 BB0C; // Used for LNA calculation |
| 134 | u32 BB2C; // |
| 135 | u32 BB30; //11b acquisition control register |
| 136 | u32 BB3C; |
| 137 | u32 BB48; // 20051221.1.a 20060613.1 Fix OBW issue of 11b/11g rate |
| 138 | u32 BB4C; // 20060613.1 Fix OBW issue of 11b/11g rate |
| 139 | u32 BB50; //mode control register |
| 140 | u32 BB54; |
| 141 | u32 BB58; //IQ_ALPHA |
| 142 | u32 BB5C; // For test |
| 143 | u32 BB60; // for WTO read value |
| 144 | |
| 145 | //------------------- |
| 146 | // VM |
| 147 | //------------------- |
Pekka Enberg | a1eb2ba | 2008-10-21 11:45:02 +0300 | [diff] [blame] | 148 | spinlock_t EP0VM_spin_lock; // 4B |
Pavel Machek | 66101de | 2008-10-01 14:36:56 +0200 | [diff] [blame] | 149 | u32 EP0VM_status;//$$ |
Pekka Enberg | f37435c | 2008-10-22 11:01:47 +0300 | [diff] [blame] | 150 | struct wb35_reg_queue *reg_first; |
| 151 | struct wb35_reg_queue *reg_last; |
Pekka Enberg | 44e8541 | 2008-10-29 20:10:32 +0200 | [diff] [blame] | 152 | atomic_t RegFireCount; |
Pavel Machek | 66101de | 2008-10-01 14:36:56 +0200 | [diff] [blame] | 153 | |
| 154 | // Hardware status |
| 155 | u8 EP0vm_state; |
| 156 | u8 mac_power_save; |
| 157 | u8 EEPROMPhyType; // 0 ~ 15 for Maxim (0 ĄV MAX2825, 1 ĄV MAX2827, 2 ĄV MAX2828, 3 ĄV MAX2829), |
| 158 | // 16 ~ 31 for Airoha (16 ĄV AL2230, 11 - AL7230) |
| 159 | // 32 ~ Reserved |
| 160 | // 33 ~ 47 For WB242 ( 33 - WB242, 34 - WB242 with new Txvga 0.5 db step) |
| 161 | // 48 ~ 255 ARE RESERVED. |
| 162 | u8 EEPROMRegion; //Region setting in EEPROM |
| 163 | |
| 164 | u32 SyncIoPause; // If user use the Sync Io to access Hw, then pause the async access |
| 165 | |
| 166 | u8 LNAValue[4]; //Table for speed up running |
| 167 | u32 SQ3_filter[MAX_SQ3_FILTER_SIZE]; |
| 168 | u32 SQ3_index; |
| 169 | |
Pekka Enberg | 65144de | 2008-10-22 11:02:37 +0300 | [diff] [blame] | 170 | }; |
Pavel Machek | 66101de | 2008-10-01 14:36:56 +0200 | [diff] [blame] | 171 | |
Pekka Enberg | 80aba53 | 2008-10-30 13:04:29 +0200 | [diff] [blame] | 172 | #endif |