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Pratik Patel2e1cdfe2015-05-13 10:34:09 -06001What: /sys/bus/coresight/devices/<memory_map>.etm/enable_source
2Date: April 2015
3KernelVersion: 4.01
4Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
5Description: (RW) Enable/disable tracing on this specific trace entiry.
6 Enabling a source implies the source has been configured
7 properly and a sink has been identidifed for it. The path
8 of coresight components linking the source to the sink is
9 configured and managed automatically by the coresight framework.
10
11What: /sys/bus/coresight/devices/<memory_map>.etm/cpu
12Date: April 2015
13KernelVersion: 4.01
14Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
15Description: (R) The CPU this tracing entity is associated with.
Pratik Patelc0ddbfe2015-05-13 10:34:10 -060016
17What: /sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp
18Date: April 2015
19KernelVersion: 4.01
20Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
21Description: (R) Indicates the number of PE comparator inputs that are
22 available for tracing.
23
24What: /sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp
25Date: April 2015
26KernelVersion: 4.01
27Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
28Description: (R) Indicates the number of address comparator pairs that are
29 available for tracing.
30
31What: /sys/bus/coresight/devices/<memory_map>.etm/nr_cntr
32Date: April 2015
33KernelVersion: 4.01
34Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
35Description: (R) Indicates the number of counters that are available for
36 tracing.
37
38What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp
39Date: April 2015
40KernelVersion: 4.01
41Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
42Description: (R) Indicates how many external inputs are implemented.
43
44What: /sys/bus/coresight/devices/<memory_map>.etm/numcidc
45Date: April 2015
46KernelVersion: 4.01
47Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
48Description: (R) Indicates the number of Context ID comparators that are
49 available for tracing.
50
51What: /sys/bus/coresight/devices/<memory_map>.etm/numvmidc
52Date: April 2015
53KernelVersion: 4.01
54Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
55Description: (R) Indicates the number of VMID comparators that are available
56 for tracing.
57
58What: /sys/bus/coresight/devices/<memory_map>.etm/nrseqstate
59Date: April 2015
60KernelVersion: 4.01
61Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
62Description: (R) Indicates the number of sequencer states that are
63 implemented.
64
65What: /sys/bus/coresight/devices/<memory_map>.etm/nr_resource
66Date: April 2015
67KernelVersion: 4.01
68Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
69Description: (R) Indicates the number of resource selection pairs that are
70 available for tracing.
71
72What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ss_cmp
73Date: April 2015
74KernelVersion: 4.01
75Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
76Description: (R) Indicates the number of single-shot comparator controls that
77 are available for tracing.
Pratik Pateld8c66962015-05-13 10:34:11 -060078
79What: /sys/bus/coresight/devices/<memory_map>.etm/reset
80Date: April 2015
81KernelVersion: 4.01
82Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
83Description: (W) Cancels all configuration on a trace unit and set it back
84 to its boot configuration.
85
86What: /sys/bus/coresight/devices/<memory_map>.etm/mode
87Date: April 2015
88KernelVersion: 4.01
89Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
90Description: (RW) Controls various modes supported by this ETM, for example
91 P0 instruction tracing, branch broadcast, cycle counting and
92 context ID tracing.
93
94What: /sys/bus/coresight/devices/<memory_map>.etm/pe
95Date: April 2015
96KernelVersion: 4.01
97Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
98Description: (RW) Controls which PE to trace.
99
100What: /sys/bus/coresight/devices/<memory_map>.etm/event
101Date: April 2015
102KernelVersion: 4.01
103Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
104Description: (RW) Controls the tracing of arbitrary events from bank 0 to 3.
105
106What: /sys/bus/coresight/devices/<memory_map>.etm/event_instren
107Date: April 2015
108KernelVersion: 4.01
109Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
110Description: (RW) Controls the behavior of the events in bank 0 to 3.
Pratik Patelb460daf2015-05-13 10:34:12 -0600111
112What: /sys/bus/coresight/devices/<memory_map>.etm/event_ts
113Date: April 2015
114KernelVersion: 4.01
115Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
116Description: (RW) Controls the insertion of global timestamps in the trace
117 streams.
118
119What: /sys/bus/coresight/devices/<memory_map>.etm/syncfreq
120Date: April 2015
121KernelVersion: 4.01
122Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
123Description: (RW) Controls how often trace synchronization requests occur.
124
125What: /sys/bus/coresight/devices/<memory_map>.etm/cyc_threshold
126Date: April 2015
127KernelVersion: 4.01
128Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
129Description: (RW) Sets the threshold value for cycle counting.
130
131What: /sys/bus/coresight/devices/<memory_map>.etm/bb_ctrl
132Date: April 2015
133KernelVersion: 4.01
134Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
135Description: (RW) Controls which regions in the memory map are enabled to
136 use branch broadcasting.