Brian Norris | 766a2d9 | 2015-05-12 16:28:21 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Broadcom SATA3 AHCI Controller Driver |
| 3 | * |
| 4 | * Copyright © 2009-2015 Broadcom Corporation |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2, or (at your option) |
| 9 | * any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/ahci_platform.h> |
| 18 | #include <linux/compiler.h> |
| 19 | #include <linux/device.h> |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/interrupt.h> |
| 22 | #include <linux/io.h> |
| 23 | #include <linux/kernel.h> |
| 24 | #include <linux/libata.h> |
| 25 | #include <linux/module.h> |
| 26 | #include <linux/of.h> |
| 27 | #include <linux/platform_device.h> |
| 28 | #include <linux/string.h> |
| 29 | |
| 30 | #include "ahci.h" |
| 31 | |
| 32 | #define DRV_NAME "brcm-ahci" |
| 33 | |
| 34 | #define SATA_TOP_CTRL_VERSION 0x0 |
| 35 | #define SATA_TOP_CTRL_BUS_CTRL 0x4 |
| 36 | #define MMIO_ENDIAN_SHIFT 0 /* CPU->AHCI */ |
| 37 | #define DMADESC_ENDIAN_SHIFT 2 /* AHCI->DDR */ |
| 38 | #define DMADATA_ENDIAN_SHIFT 4 /* AHCI->DDR */ |
| 39 | #define PIODATA_ENDIAN_SHIFT 6 |
| 40 | #define ENDIAN_SWAP_NONE 0 |
| 41 | #define ENDIAN_SWAP_FULL 2 |
| 42 | #define OVERRIDE_HWINIT BIT(16) |
| 43 | #define SATA_TOP_CTRL_TP_CTRL 0x8 |
| 44 | #define SATA_TOP_CTRL_PHY_CTRL 0xc |
| 45 | #define SATA_TOP_CTRL_PHY_CTRL_1 0x0 |
| 46 | #define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE BIT(14) |
| 47 | #define SATA_TOP_CTRL_PHY_CTRL_2 0x4 |
| 48 | #define SATA_TOP_CTRL_2_SW_RST_MDIOREG BIT(0) |
| 49 | #define SATA_TOP_CTRL_2_SW_RST_OOB BIT(1) |
| 50 | #define SATA_TOP_CTRL_2_SW_RST_RX BIT(2) |
| 51 | #define SATA_TOP_CTRL_2_SW_RST_TX BIT(3) |
| 52 | #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET BIT(14) |
| 53 | #define SATA_TOP_CTRL_PHY_OFFS 0x8 |
| 54 | #define SATA_TOP_MAX_PHYS 2 |
| 55 | #define SATA_TOP_CTRL_SATA_TP_OUT 0x1c |
| 56 | #define SATA_TOP_CTRL_CLIENT_INIT_CTRL 0x20 |
| 57 | |
| 58 | /* On big-endian MIPS, buses are reversed to big endian, so switch them back */ |
| 59 | #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN) |
| 60 | #define DATA_ENDIAN 2 /* AHCI->DDR inbound accesses */ |
| 61 | #define MMIO_ENDIAN 2 /* CPU->AHCI outbound accesses */ |
| 62 | #else |
| 63 | #define DATA_ENDIAN 0 |
| 64 | #define MMIO_ENDIAN 0 |
| 65 | #endif |
| 66 | |
| 67 | #define BUS_CTRL_ENDIAN_CONF \ |
| 68 | ((DATA_ENDIAN << DMADATA_ENDIAN_SHIFT) | \ |
| 69 | (DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) | \ |
| 70 | (MMIO_ENDIAN << MMIO_ENDIAN_SHIFT)) |
| 71 | |
Jaedon Shin | 7de3244 | 2015-11-26 11:56:30 +0900 | [diff] [blame] | 72 | enum brcm_ahci_quirks { |
| 73 | BRCM_AHCI_QUIRK_NO_NCQ = BIT(0), |
Jaedon Shin | b46f79b | 2015-11-26 11:56:31 +0900 | [diff] [blame^] | 74 | BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE = BIT(1), |
Jaedon Shin | 7de3244 | 2015-11-26 11:56:30 +0900 | [diff] [blame] | 75 | }; |
| 76 | |
Brian Norris | 766a2d9 | 2015-05-12 16:28:21 -0700 | [diff] [blame] | 77 | struct brcm_ahci_priv { |
| 78 | struct device *dev; |
| 79 | void __iomem *top_ctrl; |
| 80 | u32 port_mask; |
Jaedon Shin | 7de3244 | 2015-11-26 11:56:30 +0900 | [diff] [blame] | 81 | u32 quirks; |
Brian Norris | 766a2d9 | 2015-05-12 16:28:21 -0700 | [diff] [blame] | 82 | }; |
| 83 | |
| 84 | static const struct ata_port_info ahci_brcm_port_info = { |
| 85 | .flags = AHCI_FLAG_COMMON, |
| 86 | .pio_mask = ATA_PIO4, |
| 87 | .udma_mask = ATA_UDMA6, |
| 88 | .port_ops = &ahci_platform_ops, |
| 89 | }; |
| 90 | |
| 91 | static inline u32 brcm_sata_readreg(void __iomem *addr) |
| 92 | { |
| 93 | /* |
| 94 | * MIPS endianness is configured by boot strap, which also reverses all |
| 95 | * bus endianness (i.e., big-endian CPU + big endian bus ==> native |
| 96 | * endian I/O). |
| 97 | * |
| 98 | * Other architectures (e.g., ARM) either do not support big endian, or |
| 99 | * else leave I/O in little endian mode. |
| 100 | */ |
Axel Lin | f9114d3 | 2015-08-06 12:28:18 +0800 | [diff] [blame] | 101 | if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) |
Brian Norris | 766a2d9 | 2015-05-12 16:28:21 -0700 | [diff] [blame] | 102 | return __raw_readl(addr); |
| 103 | else |
| 104 | return readl_relaxed(addr); |
| 105 | } |
| 106 | |
| 107 | static inline void brcm_sata_writereg(u32 val, void __iomem *addr) |
| 108 | { |
| 109 | /* See brcm_sata_readreg() comments */ |
Axel Lin | f9114d3 | 2015-08-06 12:28:18 +0800 | [diff] [blame] | 110 | if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) |
Brian Norris | 766a2d9 | 2015-05-12 16:28:21 -0700 | [diff] [blame] | 111 | __raw_writel(val, addr); |
| 112 | else |
| 113 | writel_relaxed(val, addr); |
| 114 | } |
| 115 | |
| 116 | static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port) |
| 117 | { |
| 118 | void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL + |
| 119 | (port * SATA_TOP_CTRL_PHY_OFFS); |
| 120 | void __iomem *p; |
| 121 | u32 reg; |
| 122 | |
Jaedon Shin | b46f79b | 2015-11-26 11:56:31 +0900 | [diff] [blame^] | 123 | if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE) |
| 124 | return; |
| 125 | |
Brian Norris | 766a2d9 | 2015-05-12 16:28:21 -0700 | [diff] [blame] | 126 | /* clear PHY_DEFAULT_POWER_STATE */ |
| 127 | p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1; |
| 128 | reg = brcm_sata_readreg(p); |
| 129 | reg &= ~SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE; |
| 130 | brcm_sata_writereg(reg, p); |
| 131 | |
| 132 | /* reset the PHY digital logic */ |
| 133 | p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2; |
| 134 | reg = brcm_sata_readreg(p); |
| 135 | reg &= ~(SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB | |
| 136 | SATA_TOP_CTRL_2_SW_RST_RX); |
| 137 | reg |= SATA_TOP_CTRL_2_SW_RST_TX; |
| 138 | brcm_sata_writereg(reg, p); |
| 139 | reg = brcm_sata_readreg(p); |
| 140 | reg |= SATA_TOP_CTRL_2_PHY_GLOBAL_RESET; |
| 141 | brcm_sata_writereg(reg, p); |
| 142 | reg = brcm_sata_readreg(p); |
| 143 | reg &= ~SATA_TOP_CTRL_2_PHY_GLOBAL_RESET; |
| 144 | brcm_sata_writereg(reg, p); |
| 145 | (void)brcm_sata_readreg(p); |
| 146 | } |
| 147 | |
| 148 | static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port) |
| 149 | { |
| 150 | void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL + |
| 151 | (port * SATA_TOP_CTRL_PHY_OFFS); |
| 152 | void __iomem *p; |
| 153 | u32 reg; |
| 154 | |
Jaedon Shin | b46f79b | 2015-11-26 11:56:31 +0900 | [diff] [blame^] | 155 | if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE) |
| 156 | return; |
| 157 | |
Brian Norris | 766a2d9 | 2015-05-12 16:28:21 -0700 | [diff] [blame] | 158 | /* power-off the PHY digital logic */ |
| 159 | p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2; |
| 160 | reg = brcm_sata_readreg(p); |
| 161 | reg |= (SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB | |
| 162 | SATA_TOP_CTRL_2_SW_RST_RX | SATA_TOP_CTRL_2_SW_RST_TX | |
| 163 | SATA_TOP_CTRL_2_PHY_GLOBAL_RESET); |
| 164 | brcm_sata_writereg(reg, p); |
| 165 | |
| 166 | /* set PHY_DEFAULT_POWER_STATE */ |
| 167 | p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1; |
| 168 | reg = brcm_sata_readreg(p); |
| 169 | reg |= SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE; |
| 170 | brcm_sata_writereg(reg, p); |
| 171 | } |
| 172 | |
| 173 | static void brcm_sata_phys_enable(struct brcm_ahci_priv *priv) |
| 174 | { |
| 175 | int i; |
| 176 | |
| 177 | for (i = 0; i < SATA_TOP_MAX_PHYS; i++) |
| 178 | if (priv->port_mask & BIT(i)) |
| 179 | brcm_sata_phy_enable(priv, i); |
| 180 | } |
| 181 | |
| 182 | static void brcm_sata_phys_disable(struct brcm_ahci_priv *priv) |
| 183 | { |
| 184 | int i; |
| 185 | |
| 186 | for (i = 0; i < SATA_TOP_MAX_PHYS; i++) |
| 187 | if (priv->port_mask & BIT(i)) |
| 188 | brcm_sata_phy_disable(priv, i); |
| 189 | } |
| 190 | |
| 191 | static u32 brcm_ahci_get_portmask(struct platform_device *pdev, |
| 192 | struct brcm_ahci_priv *priv) |
| 193 | { |
| 194 | void __iomem *ahci; |
| 195 | struct resource *res; |
| 196 | u32 impl; |
| 197 | |
| 198 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ahci"); |
| 199 | ahci = devm_ioremap_resource(&pdev->dev, res); |
| 200 | if (IS_ERR(ahci)) |
| 201 | return 0; |
| 202 | |
| 203 | impl = readl(ahci + HOST_PORTS_IMPL); |
| 204 | |
| 205 | if (fls(impl) > SATA_TOP_MAX_PHYS) |
| 206 | dev_warn(priv->dev, "warning: more ports than PHYs (%#x)\n", |
| 207 | impl); |
| 208 | else if (!impl) |
| 209 | dev_info(priv->dev, "no ports found\n"); |
| 210 | |
| 211 | devm_iounmap(&pdev->dev, ahci); |
| 212 | devm_release_mem_region(&pdev->dev, res->start, resource_size(res)); |
| 213 | |
| 214 | return impl; |
| 215 | } |
| 216 | |
| 217 | static void brcm_sata_init(struct brcm_ahci_priv *priv) |
| 218 | { |
| 219 | /* Configure endianness */ |
| 220 | brcm_sata_writereg(BUS_CTRL_ENDIAN_CONF, |
| 221 | priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL); |
| 222 | } |
| 223 | |
Florian Fainelli | 8b34fe5 | 2015-07-14 13:03:33 -0700 | [diff] [blame] | 224 | #ifdef CONFIG_PM_SLEEP |
Brian Norris | 766a2d9 | 2015-05-12 16:28:21 -0700 | [diff] [blame] | 225 | static int brcm_ahci_suspend(struct device *dev) |
| 226 | { |
| 227 | struct ata_host *host = dev_get_drvdata(dev); |
| 228 | struct ahci_host_priv *hpriv = host->private_data; |
| 229 | struct brcm_ahci_priv *priv = hpriv->plat_data; |
| 230 | int ret; |
| 231 | |
| 232 | ret = ahci_platform_suspend(dev); |
| 233 | brcm_sata_phys_disable(priv); |
| 234 | return ret; |
| 235 | } |
| 236 | |
| 237 | static int brcm_ahci_resume(struct device *dev) |
| 238 | { |
| 239 | struct ata_host *host = dev_get_drvdata(dev); |
| 240 | struct ahci_host_priv *hpriv = host->private_data; |
| 241 | struct brcm_ahci_priv *priv = hpriv->plat_data; |
| 242 | |
| 243 | brcm_sata_init(priv); |
| 244 | brcm_sata_phys_enable(priv); |
| 245 | return ahci_platform_resume(dev); |
| 246 | } |
Florian Fainelli | 8b34fe5 | 2015-07-14 13:03:33 -0700 | [diff] [blame] | 247 | #endif |
Brian Norris | 766a2d9 | 2015-05-12 16:28:21 -0700 | [diff] [blame] | 248 | |
| 249 | static struct scsi_host_template ahci_platform_sht = { |
| 250 | AHCI_SHT(DRV_NAME), |
| 251 | }; |
| 252 | |
| 253 | static int brcm_ahci_probe(struct platform_device *pdev) |
| 254 | { |
| 255 | struct device *dev = &pdev->dev; |
| 256 | struct brcm_ahci_priv *priv; |
| 257 | struct ahci_host_priv *hpriv; |
| 258 | struct resource *res; |
| 259 | int ret; |
| 260 | |
| 261 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
| 262 | if (!priv) |
| 263 | return -ENOMEM; |
| 264 | priv->dev = dev; |
| 265 | |
| 266 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl"); |
| 267 | priv->top_ctrl = devm_ioremap_resource(dev, res); |
| 268 | if (IS_ERR(priv->top_ctrl)) |
| 269 | return PTR_ERR(priv->top_ctrl); |
| 270 | |
Jaedon Shin | b46f79b | 2015-11-26 11:56:31 +0900 | [diff] [blame^] | 271 | if (of_device_is_compatible(dev->of_node, "brcm,bcm7425-ahci")) { |
Jaedon Shin | 7de3244 | 2015-11-26 11:56:30 +0900 | [diff] [blame] | 272 | priv->quirks |= BRCM_AHCI_QUIRK_NO_NCQ; |
Jaedon Shin | b46f79b | 2015-11-26 11:56:31 +0900 | [diff] [blame^] | 273 | priv->quirks |= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE; |
| 274 | } |
Jaedon Shin | 7de3244 | 2015-11-26 11:56:30 +0900 | [diff] [blame] | 275 | |
Brian Norris | 766a2d9 | 2015-05-12 16:28:21 -0700 | [diff] [blame] | 276 | brcm_sata_init(priv); |
| 277 | |
| 278 | priv->port_mask = brcm_ahci_get_portmask(pdev, priv); |
| 279 | if (!priv->port_mask) |
| 280 | return -ENODEV; |
| 281 | |
| 282 | brcm_sata_phys_enable(priv); |
| 283 | |
| 284 | hpriv = ahci_platform_get_resources(pdev); |
| 285 | if (IS_ERR(hpriv)) |
| 286 | return PTR_ERR(hpriv); |
| 287 | hpriv->plat_data = priv; |
| 288 | |
| 289 | ret = ahci_platform_enable_resources(hpriv); |
| 290 | if (ret) |
| 291 | return ret; |
| 292 | |
Jaedon Shin | 7de3244 | 2015-11-26 11:56:30 +0900 | [diff] [blame] | 293 | if (priv->quirks & BRCM_AHCI_QUIRK_NO_NCQ) |
| 294 | hpriv->flags |= AHCI_HFLAG_NO_NCQ; |
| 295 | |
Brian Norris | 766a2d9 | 2015-05-12 16:28:21 -0700 | [diff] [blame] | 296 | ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info, |
| 297 | &ahci_platform_sht); |
| 298 | if (ret) |
| 299 | return ret; |
| 300 | |
| 301 | dev_info(dev, "Broadcom AHCI SATA3 registered\n"); |
| 302 | |
| 303 | return 0; |
| 304 | } |
| 305 | |
| 306 | static int brcm_ahci_remove(struct platform_device *pdev) |
| 307 | { |
| 308 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
| 309 | struct ahci_host_priv *hpriv = host->private_data; |
| 310 | struct brcm_ahci_priv *priv = hpriv->plat_data; |
| 311 | int ret; |
| 312 | |
| 313 | ret = ata_platform_remove_one(pdev); |
| 314 | if (ret) |
| 315 | return ret; |
| 316 | |
| 317 | brcm_sata_phys_disable(priv); |
| 318 | |
| 319 | return 0; |
| 320 | } |
| 321 | |
| 322 | static const struct of_device_id ahci_of_match[] = { |
| 323 | {.compatible = "brcm,bcm7445-ahci"}, |
| 324 | {}, |
| 325 | }; |
| 326 | MODULE_DEVICE_TABLE(of, ahci_of_match); |
| 327 | |
| 328 | static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume); |
| 329 | |
| 330 | static struct platform_driver brcm_ahci_driver = { |
| 331 | .probe = brcm_ahci_probe, |
| 332 | .remove = brcm_ahci_remove, |
| 333 | .driver = { |
| 334 | .name = DRV_NAME, |
| 335 | .of_match_table = ahci_of_match, |
| 336 | .pm = &ahci_brcm_pm_ops, |
| 337 | }, |
| 338 | }; |
| 339 | module_platform_driver(brcm_ahci_driver); |
| 340 | |
| 341 | MODULE_DESCRIPTION("Broadcom SATA3 AHCI Controller Driver"); |
| 342 | MODULE_AUTHOR("Brian Norris"); |
| 343 | MODULE_LICENSE("GPL"); |
| 344 | MODULE_ALIAS("platform:sata-brcmstb"); |