Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1 | /* |
| 2 | * hcd.h - DesignWare HS OTG Controller host-mode declarations |
| 3 | * |
| 4 | * Copyright (C) 2004-2013 Synopsys, Inc. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions, and the following disclaimer, |
| 11 | * without modification. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * 3. The names of the above-listed copyright holders may not be used |
| 16 | * to endorse or promote products derived from this software without |
| 17 | * specific prior written permission. |
| 18 | * |
| 19 | * ALTERNATIVELY, this software may be distributed under the terms of the |
| 20 | * GNU General Public License ("GPL") as published by the Free Software |
| 21 | * Foundation; either version 2 of the License, or (at your option) any |
| 22 | * later version. |
| 23 | * |
| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS |
| 25 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
| 26 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 27 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 28 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 29 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 30 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
| 31 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
| 32 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
| 33 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 34 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 35 | */ |
| 36 | #ifndef __DWC2_HCD_H__ |
| 37 | #define __DWC2_HCD_H__ |
| 38 | |
| 39 | /* |
| 40 | * This file contains the structures, constants, and interfaces for the |
| 41 | * Host Contoller Driver (HCD) |
| 42 | * |
| 43 | * The Host Controller Driver (HCD) is responsible for translating requests |
| 44 | * from the USB Driver into the appropriate actions on the DWC_otg controller. |
| 45 | * It isolates the USBD from the specifics of the controller by providing an |
| 46 | * API to the USBD. |
| 47 | */ |
| 48 | |
| 49 | struct dwc2_qh; |
| 50 | |
| 51 | /** |
| 52 | * struct dwc2_host_chan - Software host channel descriptor |
| 53 | * |
| 54 | * @hc_num: Host channel number, used for register address lookup |
| 55 | * @dev_addr: Address of the device |
| 56 | * @ep_num: Endpoint of the device |
| 57 | * @ep_is_in: Endpoint direction |
| 58 | * @speed: Device speed. One of the following values: |
| 59 | * - USB_SPEED_LOW |
| 60 | * - USB_SPEED_FULL |
| 61 | * - USB_SPEED_HIGH |
| 62 | * @ep_type: Endpoint type. One of the following values: |
| 63 | * - USB_ENDPOINT_XFER_CONTROL: 0 |
| 64 | * - USB_ENDPOINT_XFER_ISOC: 1 |
| 65 | * - USB_ENDPOINT_XFER_BULK: 2 |
| 66 | * - USB_ENDPOINT_XFER_INTR: 3 |
| 67 | * @max_packet: Max packet size in bytes |
| 68 | * @data_pid_start: PID for initial transaction. |
| 69 | * 0: DATA0 |
| 70 | * 1: DATA2 |
| 71 | * 2: DATA1 |
| 72 | * 3: MDATA (non-Control EP), |
| 73 | * SETUP (Control EP) |
| 74 | * @multi_count: Number of additional periodic transactions per |
| 75 | * (micro)frame |
| 76 | * @xfer_buf: Pointer to current transfer buffer position |
| 77 | * @xfer_dma: DMA address of xfer_buf |
| 78 | * @align_buf: In Buffer DMA mode this will be used if xfer_buf is not |
| 79 | * DWORD aligned |
| 80 | * @xfer_len: Total number of bytes to transfer |
| 81 | * @xfer_count: Number of bytes transferred so far |
| 82 | * @start_pkt_count: Packet count at start of transfer |
| 83 | * @xfer_started: True if the transfer has been started |
| 84 | * @ping: True if a PING request should be issued on this channel |
| 85 | * @error_state: True if the error count for this transaction is non-zero |
| 86 | * @halt_on_queue: True if this channel should be halted the next time a |
| 87 | * request is queued for the channel. This is necessary in |
| 88 | * slave mode if no request queue space is available when |
| 89 | * an attempt is made to halt the channel. |
| 90 | * @halt_pending: True if the host channel has been halted, but the core |
| 91 | * is not finished flushing queued requests |
| 92 | * @do_split: Enable split for the channel |
| 93 | * @complete_split: Enable complete split |
| 94 | * @hub_addr: Address of high speed hub for the split |
| 95 | * @hub_port: Port of the low/full speed device for the split |
| 96 | * @xact_pos: Split transaction position. One of the following values: |
| 97 | * - DWC2_HCSPLT_XACTPOS_MID |
| 98 | * - DWC2_HCSPLT_XACTPOS_BEGIN |
| 99 | * - DWC2_HCSPLT_XACTPOS_END |
| 100 | * - DWC2_HCSPLT_XACTPOS_ALL |
| 101 | * @requests: Number of requests issued for this channel since it was |
| 102 | * assigned to the current transfer (not counting PINGs) |
| 103 | * @schinfo: Scheduling micro-frame bitmap |
| 104 | * @ntd: Number of transfer descriptors for the transfer |
| 105 | * @halt_status: Reason for halting the host channel |
| 106 | * @hcint Contents of the HCINT register when the interrupt came |
| 107 | * @qh: QH for the transfer being processed by this channel |
| 108 | * @hc_list_entry: For linking to list of host channels |
| 109 | * @desc_list_addr: Current QH's descriptor list DMA address |
| 110 | * |
| 111 | * This structure represents the state of a single host channel when acting in |
| 112 | * host mode. It contains the data items needed to transfer packets to an |
| 113 | * endpoint via a host channel. |
| 114 | */ |
| 115 | struct dwc2_host_chan { |
| 116 | u8 hc_num; |
| 117 | |
| 118 | unsigned dev_addr:7; |
| 119 | unsigned ep_num:4; |
| 120 | unsigned ep_is_in:1; |
| 121 | unsigned speed:4; |
| 122 | unsigned ep_type:2; |
| 123 | unsigned max_packet:11; |
| 124 | unsigned data_pid_start:2; |
| 125 | #define DWC2_HC_PID_DATA0 (TSIZ_SC_MC_PID_DATA0 >> TSIZ_SC_MC_PID_SHIFT) |
| 126 | #define DWC2_HC_PID_DATA2 (TSIZ_SC_MC_PID_DATA2 >> TSIZ_SC_MC_PID_SHIFT) |
| 127 | #define DWC2_HC_PID_DATA1 (TSIZ_SC_MC_PID_DATA1 >> TSIZ_SC_MC_PID_SHIFT) |
| 128 | #define DWC2_HC_PID_MDATA (TSIZ_SC_MC_PID_MDATA >> TSIZ_SC_MC_PID_SHIFT) |
| 129 | #define DWC2_HC_PID_SETUP (TSIZ_SC_MC_PID_SETUP >> TSIZ_SC_MC_PID_SHIFT) |
| 130 | |
| 131 | unsigned multi_count:2; |
| 132 | |
| 133 | u8 *xfer_buf; |
| 134 | dma_addr_t xfer_dma; |
| 135 | dma_addr_t align_buf; |
| 136 | u32 xfer_len; |
| 137 | u32 xfer_count; |
| 138 | u16 start_pkt_count; |
| 139 | u8 xfer_started; |
| 140 | u8 do_ping; |
| 141 | u8 error_state; |
| 142 | u8 halt_on_queue; |
| 143 | u8 halt_pending; |
| 144 | u8 do_split; |
| 145 | u8 complete_split; |
| 146 | u8 hub_addr; |
| 147 | u8 hub_port; |
| 148 | u8 xact_pos; |
| 149 | #define DWC2_HCSPLT_XACTPOS_MID (HCSPLT_XACTPOS_MID >> HCSPLT_XACTPOS_SHIFT) |
| 150 | #define DWC2_HCSPLT_XACTPOS_END (HCSPLT_XACTPOS_END >> HCSPLT_XACTPOS_SHIFT) |
| 151 | #define DWC2_HCSPLT_XACTPOS_BEGIN (HCSPLT_XACTPOS_BEGIN >> HCSPLT_XACTPOS_SHIFT) |
| 152 | #define DWC2_HCSPLT_XACTPOS_ALL (HCSPLT_XACTPOS_ALL >> HCSPLT_XACTPOS_SHIFT) |
| 153 | |
| 154 | u8 requests; |
| 155 | u8 schinfo; |
| 156 | u16 ntd; |
| 157 | enum dwc2_halt_status halt_status; |
| 158 | u32 hcint; |
| 159 | struct dwc2_qh *qh; |
| 160 | struct list_head hc_list_entry; |
| 161 | dma_addr_t desc_list_addr; |
| 162 | }; |
| 163 | |
| 164 | struct dwc2_hcd_pipe_info { |
| 165 | u8 dev_addr; |
| 166 | u8 ep_num; |
| 167 | u8 pipe_type; |
| 168 | u8 pipe_dir; |
| 169 | u16 mps; |
| 170 | }; |
| 171 | |
| 172 | struct dwc2_hcd_iso_packet_desc { |
| 173 | u32 offset; |
| 174 | u32 length; |
| 175 | u32 actual_length; |
| 176 | u32 status; |
| 177 | }; |
| 178 | |
| 179 | struct dwc2_qtd; |
| 180 | |
| 181 | struct dwc2_hcd_urb { |
| 182 | void *priv; |
| 183 | struct dwc2_qtd *qtd; |
| 184 | void *buf; |
| 185 | dma_addr_t dma; |
| 186 | void *setup_packet; |
| 187 | dma_addr_t setup_dma; |
| 188 | u32 length; |
| 189 | u32 actual_length; |
| 190 | u32 status; |
| 191 | u32 error_count; |
| 192 | u32 packet_count; |
| 193 | u32 flags; |
| 194 | u16 interval; |
| 195 | struct dwc2_hcd_pipe_info pipe_info; |
| 196 | struct dwc2_hcd_iso_packet_desc iso_descs[0]; |
| 197 | }; |
| 198 | |
| 199 | /* Phases for control transfers */ |
| 200 | enum dwc2_control_phase { |
| 201 | DWC2_CONTROL_SETUP, |
| 202 | DWC2_CONTROL_DATA, |
| 203 | DWC2_CONTROL_STATUS, |
| 204 | }; |
| 205 | |
| 206 | /* Transaction types */ |
| 207 | enum dwc2_transaction_type { |
| 208 | DWC2_TRANSACTION_NONE, |
| 209 | DWC2_TRANSACTION_PERIODIC, |
| 210 | DWC2_TRANSACTION_NON_PERIODIC, |
| 211 | DWC2_TRANSACTION_ALL, |
| 212 | }; |
| 213 | |
| 214 | /** |
| 215 | * struct dwc2_qh - Software queue head structure |
| 216 | * |
| 217 | * @ep_type: Endpoint type. One of the following values: |
| 218 | * - USB_ENDPOINT_XFER_CONTROL |
| 219 | * - USB_ENDPOINT_XFER_BULK |
| 220 | * - USB_ENDPOINT_XFER_INT |
| 221 | * - USB_ENDPOINT_XFER_ISOC |
| 222 | * @ep_is_in: Endpoint direction |
| 223 | * @maxp: Value from wMaxPacketSize field of Endpoint Descriptor |
| 224 | * @dev_speed: Device speed. One of the following values: |
| 225 | * - USB_SPEED_LOW |
| 226 | * - USB_SPEED_FULL |
| 227 | * - USB_SPEED_HIGH |
| 228 | * @data_toggle: Determines the PID of the next data packet for |
| 229 | * non-controltransfers. Ignored for control transfers. |
| 230 | * One of the following values: |
| 231 | * - DWC2_HC_PID_DATA0 |
| 232 | * - DWC2_HC_PID_DATA1 |
| 233 | * @ping_state: Ping state |
| 234 | * @do_split: Full/low speed endpoint on high-speed hub requires split |
| 235 | * @qtd_list: List of QTDs for this QH |
| 236 | * @channel: Host channel currently processing transfers for this QH |
| 237 | * @usecs: Bandwidth in microseconds per (micro)frame |
| 238 | * @interval: Interval between transfers in (micro)frames |
| 239 | * @sched_frame: (micro)frame to initialize a periodic transfer. |
| 240 | * The transfer executes in the following (micro)frame. |
| 241 | * @start_split_frame: (Micro)frame at which last start split was initialized |
| 242 | * @dw_align_buf: Used instead of original buffer if its physical address |
| 243 | * is not dword-aligned |
| 244 | * @dw_align_buf_dma: DMA address for align_buf |
| 245 | * @qh_list_entry: Entry for QH in either the periodic or non-periodic |
| 246 | * schedule |
| 247 | * @desc_list: List of transfer descriptors |
| 248 | * @desc_list_dma: Physical address of desc_list |
| 249 | * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer |
| 250 | * descriptor and indicates original XferSize value for the |
| 251 | * descriptor |
| 252 | * @ntd: Actual number of transfer descriptors in a list |
| 253 | * @td_first: Index of first activated isochronous transfer descriptor |
| 254 | * @td_last: Index of last activated isochronous transfer descriptor |
| 255 | * @tt_buffer_dirty True if clear_tt_buffer_complete is pending |
| 256 | * |
| 257 | * A Queue Head (QH) holds the static characteristics of an endpoint and |
| 258 | * maintains a list of transfers (QTDs) for that endpoint. A QH structure may |
| 259 | * be entered in either the non-periodic or periodic schedule. |
| 260 | */ |
| 261 | struct dwc2_qh { |
| 262 | u8 ep_type; |
| 263 | u8 ep_is_in; |
| 264 | u16 maxp; |
| 265 | u8 dev_speed; |
| 266 | u8 data_toggle; |
| 267 | u8 ping_state; |
| 268 | u8 do_split; |
| 269 | struct list_head qtd_list; |
| 270 | struct dwc2_host_chan *channel; |
| 271 | u16 usecs; |
| 272 | u16 interval; |
| 273 | u16 sched_frame; |
| 274 | u16 start_split_frame; |
| 275 | u8 *dw_align_buf; |
| 276 | dma_addr_t dw_align_buf_dma; |
| 277 | struct list_head qh_list_entry; |
| 278 | struct dwc2_hcd_dma_desc *desc_list; |
| 279 | dma_addr_t desc_list_dma; |
| 280 | u32 *n_bytes; |
| 281 | u16 ntd; |
| 282 | u8 td_first; |
| 283 | u8 td_last; |
| 284 | unsigned tt_buffer_dirty:1; |
| 285 | }; |
| 286 | |
| 287 | /** |
| 288 | * struct dwc2_qtd - Software queue transfer descriptor (QTD) |
| 289 | * |
| 290 | * @control_phase: Current phase for control transfers (Setup, Data, or |
| 291 | * Status) |
| 292 | * @in_process: Indicates if this QTD is currently processed by HW |
| 293 | * @data_toggle: Determines the PID of the next data packet for the |
| 294 | * data phase of control transfers. Ignored for other |
| 295 | * transfer types. One of the following values: |
| 296 | * - DWC2_HC_PID_DATA0 |
| 297 | * - DWC2_HC_PID_DATA1 |
| 298 | * @complete_split: Keeps track of the current split type for FS/LS |
| 299 | * endpoints on a HS Hub |
| 300 | * @isoc_split_pos: Position of the ISOC split in full/low speed |
| 301 | * @isoc_frame_index: Index of the next frame descriptor for an isochronous |
| 302 | * transfer. A frame descriptor describes the buffer |
| 303 | * position and length of the data to be transferred in the |
| 304 | * next scheduled (micro)frame of an isochronous transfer. |
| 305 | * It also holds status for that transaction. The frame |
| 306 | * index starts at 0. |
| 307 | * @isoc_split_offset: Position of the ISOC split in the buffer for the |
| 308 | * current frame |
| 309 | * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT |
| 310 | * @error_count: Holds the number of bus errors that have occurred for |
| 311 | * a transaction within this transfer |
| 312 | * @n_desc: Number of DMA descriptors for this QTD |
| 313 | * @isoc_frame_index_last: Last activated frame (packet) index, used in |
| 314 | * descriptor DMA mode only |
| 315 | * @urb: URB for this transfer |
| 316 | * @qh: Queue head for this QTD |
| 317 | * @qtd_list_entry: For linking to the QH's list of QTDs |
| 318 | * |
| 319 | * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, |
| 320 | * interrupt, or isochronous transfer. A single QTD is created for each URB |
| 321 | * (of one of these types) submitted to the HCD. The transfer associated with |
| 322 | * a QTD may require one or multiple transactions. |
| 323 | * |
| 324 | * A QTD is linked to a Queue Head, which is entered in either the |
| 325 | * non-periodic or periodic schedule for execution. When a QTD is chosen for |
| 326 | * execution, some or all of its transactions may be executed. After |
| 327 | * execution, the state of the QTD is updated. The QTD may be retired if all |
| 328 | * its transactions are complete or if an error occurred. Otherwise, it |
| 329 | * remains in the schedule so more transactions can be executed later. |
| 330 | */ |
| 331 | struct dwc2_qtd { |
| 332 | enum dwc2_control_phase control_phase; |
| 333 | u8 in_process; |
| 334 | u8 data_toggle; |
| 335 | u8 complete_split; |
| 336 | u8 isoc_split_pos; |
| 337 | u16 isoc_frame_index; |
| 338 | u16 isoc_split_offset; |
| 339 | u32 ssplit_out_xfer_count; |
| 340 | u8 error_count; |
| 341 | u8 n_desc; |
| 342 | u16 isoc_frame_index_last; |
| 343 | struct dwc2_hcd_urb *urb; |
| 344 | struct dwc2_qh *qh; |
| 345 | struct list_head qtd_list_entry; |
| 346 | }; |
| 347 | |
| 348 | #ifdef DEBUG |
| 349 | struct hc_xfer_info { |
| 350 | struct dwc2_hsotg *hsotg; |
| 351 | struct dwc2_host_chan *chan; |
| 352 | }; |
| 353 | #endif |
| 354 | |
| 355 | /* Gets the struct usb_hcd that contains a struct dwc2_hsotg */ |
| 356 | static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg) |
| 357 | { |
| 358 | return (struct usb_hcd *)hsotg->priv; |
| 359 | } |
| 360 | |
| 361 | /* |
| 362 | * Inline used to disable one channel interrupt. Channel interrupts are |
| 363 | * disabled when the channel is halted or released by the interrupt handler. |
| 364 | * There is no need to handle further interrupts of that type until the |
| 365 | * channel is re-assigned. In fact, subsequent handling may cause crashes |
| 366 | * because the channel structures are cleaned up when the channel is released. |
| 367 | */ |
| 368 | static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr) |
| 369 | { |
| 370 | u32 mask = readl(hsotg->regs + HCINTMSK(chnum)); |
| 371 | |
| 372 | mask &= ~intr; |
| 373 | writel(mask, hsotg->regs + HCINTMSK(chnum)); |
| 374 | } |
| 375 | |
| 376 | /* |
| 377 | * Returns the mode of operation, host or device |
| 378 | */ |
| 379 | static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) |
| 380 | { |
| 381 | return (readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; |
| 382 | } |
| 383 | static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) |
| 384 | { |
| 385 | return (readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; |
| 386 | } |
| 387 | |
| 388 | /* |
| 389 | * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they |
| 390 | * are read as 1, they won't clear when written back. |
| 391 | */ |
| 392 | static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg) |
| 393 | { |
| 394 | u32 hprt0 = readl(hsotg->regs + HPRT0); |
| 395 | |
| 396 | hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG); |
| 397 | return hprt0; |
| 398 | } |
| 399 | |
| 400 | static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe) |
| 401 | { |
| 402 | return pipe->ep_num; |
| 403 | } |
| 404 | |
| 405 | static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe) |
| 406 | { |
| 407 | return pipe->pipe_type; |
| 408 | } |
| 409 | |
| 410 | static inline u16 dwc2_hcd_get_mps(struct dwc2_hcd_pipe_info *pipe) |
| 411 | { |
| 412 | return pipe->mps; |
| 413 | } |
| 414 | |
| 415 | static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe) |
| 416 | { |
| 417 | return pipe->dev_addr; |
| 418 | } |
| 419 | |
| 420 | static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe) |
| 421 | { |
| 422 | return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC; |
| 423 | } |
| 424 | |
| 425 | static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe) |
| 426 | { |
| 427 | return pipe->pipe_type == USB_ENDPOINT_XFER_INT; |
| 428 | } |
| 429 | |
| 430 | static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe) |
| 431 | { |
| 432 | return pipe->pipe_type == USB_ENDPOINT_XFER_BULK; |
| 433 | } |
| 434 | |
| 435 | static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe) |
| 436 | { |
| 437 | return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL; |
| 438 | } |
| 439 | |
| 440 | static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe) |
| 441 | { |
| 442 | return pipe->pipe_dir == USB_DIR_IN; |
| 443 | } |
| 444 | |
| 445 | static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe) |
| 446 | { |
| 447 | return !dwc2_hcd_is_pipe_in(pipe); |
| 448 | } |
| 449 | |
Paul Zimmerman | e62662c | 2013-03-25 17:03:35 -0700 | [diff] [blame] | 450 | extern int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq, |
| 451 | struct dwc2_core_params *params); |
| 452 | extern void dwc2_hcd_remove(struct dwc2_hsotg *hsotg); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 453 | extern int dwc2_set_parameters(struct dwc2_hsotg *hsotg, |
| 454 | struct dwc2_core_params *params); |
| 455 | |
| 456 | /* Transaction Execution Functions */ |
| 457 | extern enum dwc2_transaction_type dwc2_hcd_select_transactions( |
| 458 | struct dwc2_hsotg *hsotg); |
| 459 | extern void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, |
| 460 | enum dwc2_transaction_type tr_type); |
| 461 | |
| 462 | /* Schedule Queue Functions */ |
| 463 | /* Implemented in hcd_queue.c */ |
| 464 | extern void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); |
| 465 | extern int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); |
| 466 | extern void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); |
| 467 | extern void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, |
| 468 | int sched_csplit); |
| 469 | |
| 470 | extern void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb); |
| 471 | extern int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, |
| 472 | struct dwc2_qh **qh, gfp_t mem_flags); |
| 473 | |
| 474 | /* Unlinks and frees a QTD */ |
| 475 | static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, |
| 476 | struct dwc2_qtd *qtd, |
| 477 | struct dwc2_qh *qh) |
| 478 | { |
| 479 | list_del(&qtd->qtd_list_entry); |
| 480 | kfree(qtd); |
| 481 | } |
| 482 | |
| 483 | /* Descriptor DMA support functions */ |
| 484 | extern void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg, |
| 485 | struct dwc2_qh *qh); |
| 486 | extern void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg, |
| 487 | struct dwc2_host_chan *chan, int chnum, |
| 488 | enum dwc2_halt_status halt_status); |
| 489 | |
| 490 | extern int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, |
| 491 | gfp_t mem_flags); |
| 492 | extern void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); |
| 493 | |
| 494 | /* Check if QH is non-periodic */ |
| 495 | #define dwc2_qh_is_non_per(_qh_ptr_) \ |
| 496 | ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \ |
| 497 | (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL) |
| 498 | |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame^] | 499 | #ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC |
| 500 | static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; } |
| 501 | static inline bool dbg_qh(struct dwc2_qh *qh) { return true; } |
| 502 | static inline bool dbg_urb(struct urb *urb) { return true; } |
| 503 | static inline bool dbg_perio(void) { return true; } |
| 504 | #else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */ |
| 505 | static inline bool dbg_hc(struct dwc2_host_chan *hc) |
| 506 | { |
| 507 | return hc->ep_type == USB_ENDPOINT_XFER_BULK || |
| 508 | hc->ep_type == USB_ENDPOINT_XFER_CONTROL; |
| 509 | } |
| 510 | |
| 511 | static inline bool dbg_qh(struct dwc2_qh *qh) |
| 512 | { |
| 513 | return qh->ep_type == USB_ENDPOINT_XFER_BULK || |
| 514 | qh->ep_type == USB_ENDPOINT_XFER_CONTROL; |
| 515 | } |
| 516 | |
| 517 | static inline bool dbg_urb(struct urb *urb) |
| 518 | { |
| 519 | return usb_pipetype(urb->pipe) == PIPE_BULK || |
| 520 | usb_pipetype(urb->pipe) == PIPE_CONTROL; |
| 521 | } |
| 522 | |
| 523 | static inline bool dbg_perio(void) { return false; } |
| 524 | #endif |
| 525 | |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 526 | /* High bandwidth multiplier as encoded in highspeed endpoint descriptors */ |
| 527 | #define dwc2_hb_mult(wmaxpacketsize) (1 + (((wmaxpacketsize) >> 11) & 0x03)) |
| 528 | |
| 529 | /* Packet size for any kind of endpoint descriptor */ |
| 530 | #define dwc2_max_packet(wmaxpacketsize) ((wmaxpacketsize) & 0x07ff) |
| 531 | |
| 532 | /* |
| 533 | * Returns true if frame1 is less than or equal to frame2. The comparison is |
| 534 | * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the |
| 535 | * frame number when the max frame number is reached. |
| 536 | */ |
| 537 | static inline int dwc2_frame_num_le(u16 frame1, u16 frame2) |
| 538 | { |
| 539 | return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1); |
| 540 | } |
| 541 | |
| 542 | /* |
| 543 | * Returns true if frame1 is greater than frame2. The comparison is done |
| 544 | * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame |
| 545 | * number when the max frame number is reached. |
| 546 | */ |
| 547 | static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2) |
| 548 | { |
| 549 | return (frame1 != frame2) && |
| 550 | ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1); |
| 551 | } |
| 552 | |
| 553 | /* |
| 554 | * Increments frame by the amount specified by inc. The addition is done |
| 555 | * modulo HFNUM_MAX_FRNUM. Returns the incremented value. |
| 556 | */ |
| 557 | static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc) |
| 558 | { |
| 559 | return (frame + inc) & HFNUM_MAX_FRNUM; |
| 560 | } |
| 561 | |
| 562 | static inline u16 dwc2_full_frame_num(u16 frame) |
| 563 | { |
| 564 | return (frame & HFNUM_MAX_FRNUM) >> 3; |
| 565 | } |
| 566 | |
| 567 | static inline u16 dwc2_micro_frame_num(u16 frame) |
| 568 | { |
| 569 | return frame & 0x7; |
| 570 | } |
| 571 | |
| 572 | /* |
| 573 | * Returns the Core Interrupt Status register contents, ANDed with the Core |
| 574 | * Interrupt Mask register contents |
| 575 | */ |
| 576 | static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg) |
| 577 | { |
| 578 | return readl(hsotg->regs + GINTSTS) & readl(hsotg->regs + GINTMSK); |
| 579 | } |
| 580 | |
| 581 | static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb) |
| 582 | { |
| 583 | return dwc2_urb->status; |
| 584 | } |
| 585 | |
| 586 | static inline u32 dwc2_hcd_urb_get_actual_length( |
| 587 | struct dwc2_hcd_urb *dwc2_urb) |
| 588 | { |
| 589 | return dwc2_urb->actual_length; |
| 590 | } |
| 591 | |
| 592 | static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb) |
| 593 | { |
| 594 | return dwc2_urb->error_count; |
| 595 | } |
| 596 | |
| 597 | static inline void dwc2_hcd_urb_set_iso_desc_params( |
| 598 | struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset, |
| 599 | u32 length) |
| 600 | { |
| 601 | dwc2_urb->iso_descs[desc_num].offset = offset; |
| 602 | dwc2_urb->iso_descs[desc_num].length = length; |
| 603 | } |
| 604 | |
| 605 | static inline u32 dwc2_hcd_urb_get_iso_desc_status( |
| 606 | struct dwc2_hcd_urb *dwc2_urb, int desc_num) |
| 607 | { |
| 608 | return dwc2_urb->iso_descs[desc_num].status; |
| 609 | } |
| 610 | |
| 611 | static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length( |
| 612 | struct dwc2_hcd_urb *dwc2_urb, int desc_num) |
| 613 | { |
| 614 | return dwc2_urb->iso_descs[desc_num].actual_length; |
| 615 | } |
| 616 | |
| 617 | static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg, |
| 618 | struct usb_host_endpoint *ep) |
| 619 | { |
| 620 | struct dwc2_qh *qh = ep->hcpriv; |
| 621 | |
| 622 | if (qh && !list_empty(&qh->qh_list_entry)) |
| 623 | return 1; |
| 624 | |
| 625 | return 0; |
| 626 | } |
| 627 | |
| 628 | static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg, |
| 629 | struct usb_host_endpoint *ep) |
| 630 | { |
| 631 | struct dwc2_qh *qh = ep->hcpriv; |
| 632 | |
| 633 | if (!qh) { |
| 634 | WARN_ON(1); |
| 635 | return 0; |
| 636 | } |
| 637 | |
| 638 | return qh->usecs; |
| 639 | } |
| 640 | |
| 641 | extern void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, |
| 642 | struct dwc2_host_chan *chan, int chnum, |
| 643 | struct dwc2_qtd *qtd); |
| 644 | |
| 645 | /* HCD Core API */ |
| 646 | |
| 647 | /** |
| 648 | * dwc2_hcd_intr() - Called on every hardware interrupt |
| 649 | * |
| 650 | * @hsotg: The DWC2 HCD |
| 651 | * |
| 652 | * Returns non zero if interrupt is handled |
| 653 | * Return 0 if interrupt is not handled |
| 654 | */ |
| 655 | extern int dwc2_hcd_intr(struct dwc2_hsotg *hsotg); |
| 656 | |
| 657 | /** |
| 658 | * dwc2_hcd_stop() - Halts the DWC_otg host mode operation |
| 659 | * |
| 660 | * @hsotg: The DWC2 HCD |
| 661 | */ |
| 662 | extern void dwc2_hcd_stop(struct dwc2_hsotg *hsotg); |
| 663 | |
| 664 | extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg); |
| 665 | extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg); |
| 666 | |
| 667 | /** |
| 668 | * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host, |
| 669 | * and 0 otherwise |
| 670 | * |
| 671 | * @hsotg: The DWC2 HCD |
| 672 | */ |
| 673 | extern int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg); |
| 674 | |
| 675 | /** |
| 676 | * dwc2_hcd_get_frame_number() - Returns current frame number |
| 677 | * |
| 678 | * @hsotg: The DWC2 HCD |
| 679 | */ |
| 680 | extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); |
| 681 | |
| 682 | /** |
| 683 | * dwc2_hcd_dump_state() - Dumps hsotg state |
| 684 | * |
| 685 | * @hsotg: The DWC2 HCD |
| 686 | * |
| 687 | * NOTE: This function will be removed once the peripheral controller code |
| 688 | * is integrated and the driver is stable |
| 689 | */ |
| 690 | extern void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg); |
| 691 | |
| 692 | /** |
| 693 | * dwc2_hcd_dump_frrem() - Dumps the average frame remaining at SOF |
| 694 | * |
| 695 | * @hsotg: The DWC2 HCD |
| 696 | * |
| 697 | * This can be used to determine average interrupt latency. Frame remaining is |
| 698 | * also shown for start transfer and two additional sample points. |
| 699 | * |
| 700 | * NOTE: This function will be removed once the peripheral controller code |
| 701 | * is integrated and the driver is stable |
| 702 | */ |
| 703 | extern void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg); |
| 704 | |
| 705 | /* URB interface */ |
| 706 | |
| 707 | /* Transfer flags */ |
| 708 | #define URB_GIVEBACK_ASAP 0x1 |
| 709 | #define URB_SEND_ZERO_PACKET 0x2 |
| 710 | |
| 711 | /* Host driver callbacks */ |
| 712 | |
| 713 | extern void dwc2_host_start(struct dwc2_hsotg *hsotg); |
| 714 | extern void dwc2_host_disconnect(struct dwc2_hsotg *hsotg); |
| 715 | extern void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, |
| 716 | int *hub_addr, int *hub_port); |
| 717 | extern int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context); |
| 718 | extern void dwc2_host_complete(struct dwc2_hsotg *hsotg, void *context, |
| 719 | struct dwc2_hcd_urb *dwc2_urb, int status); |
| 720 | |
| 721 | #ifdef DEBUG |
| 722 | /* |
| 723 | * Macro to sample the remaining PHY clocks left in the current frame. This |
| 724 | * may be used during debugging to determine the average time it takes to |
| 725 | * execute sections of code. There are two possible sample points, "a" and |
| 726 | * "b", so the _letter_ argument must be one of these values. |
| 727 | * |
| 728 | * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For |
| 729 | * example, "cat /sys/devices/lm0/hcd_frrem". |
| 730 | */ |
| 731 | #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) \ |
| 732 | do { \ |
| 733 | struct hfnum_data _hfnum_; \ |
| 734 | struct dwc2_qtd *_qtd_; \ |
| 735 | \ |
| 736 | _qtd_ = list_entry((_qh_)->qtd_list.next, struct dwc2_qtd, \ |
| 737 | qtd_list_entry); \ |
| 738 | if (usb_pipeint(_qtd_->urb->pipe) && \ |
| 739 | (_qh_)->start_split_frame != 0 && !_qtd_->complete_split) { \ |
| 740 | _hfnum_.d32 = readl((_hcd_)->regs + HFNUM); \ |
| 741 | switch (_hfnum_.b.frnum & 0x7) { \ |
| 742 | case 7: \ |
| 743 | (_hcd_)->hfnum_7_samples_##_letter_++; \ |
| 744 | (_hcd_)->hfnum_7_frrem_accum_##_letter_ += \ |
| 745 | _hfnum_.b.frrem; \ |
| 746 | break; \ |
| 747 | case 0: \ |
| 748 | (_hcd_)->hfnum_0_samples_##_letter_++; \ |
| 749 | (_hcd_)->hfnum_0_frrem_accum_##_letter_ += \ |
| 750 | _hfnum_.b.frrem; \ |
| 751 | break; \ |
| 752 | default: \ |
| 753 | (_hcd_)->hfnum_other_samples_##_letter_++; \ |
| 754 | (_hcd_)->hfnum_other_frrem_accum_##_letter_ += \ |
| 755 | _hfnum_.b.frrem; \ |
| 756 | break; \ |
| 757 | } \ |
| 758 | } \ |
| 759 | } while (0) |
| 760 | #else |
| 761 | #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) do {} while (0) |
| 762 | #endif |
| 763 | |
| 764 | #endif /* __DWC2_HCD_H__ */ |