David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 1 | /* |
Paul Gortmaker | 3396c78 | 2012-01-27 13:36:01 +0000 | [diff] [blame] | 2 | * drivers/net/ethernet/ibm/emac/mal.c |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 3 | * |
| 4 | * Memory Access Layer (MAL) support |
| 5 | * |
Benjamin Herrenschmidt | 17cf803 | 2007-12-05 11:14:33 +1100 | [diff] [blame] | 6 | * Copyright 2007 Benjamin Herrenschmidt, IBM Corp. |
| 7 | * <benh@kernel.crashing.org> |
| 8 | * |
| 9 | * Based on the arch/ppc version of the driver: |
| 10 | * |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 11 | * Copyright (c) 2004, 2005 Zultys Technologies. |
| 12 | * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> |
| 13 | * |
| 14 | * Based on original work by |
| 15 | * Benjamin Herrenschmidt <benh@kernel.crashing.org>, |
| 16 | * David Gibson <hermes@gibson.dropbear.id.au>, |
| 17 | * |
| 18 | * Armin Kuster <akuster@mvista.com> |
| 19 | * Copyright 2002 MontaVista Softare Inc. |
| 20 | * |
| 21 | * This program is free software; you can redistribute it and/or modify it |
| 22 | * under the terms of the GNU General Public License as published by the |
| 23 | * Free Software Foundation; either version 2 of the License, or (at your |
| 24 | * option) any later version. |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include <linux/delay.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 30 | |
| 31 | #include "core.h" |
Josh Boyer | fbcc4ba | 2008-09-04 04:08:20 +0000 | [diff] [blame] | 32 | #include <asm/dcr-regs.h> |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 33 | |
| 34 | static int mal_count; |
| 35 | |
Greg Kroah-Hartman | 1dd06ae | 2012-12-06 14:30:56 +0000 | [diff] [blame] | 36 | int mal_register_commac(struct mal_instance *mal, struct mal_commac *commac) |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 37 | { |
| 38 | unsigned long flags; |
| 39 | |
| 40 | spin_lock_irqsave(&mal->lock, flags); |
| 41 | |
| 42 | MAL_DBG(mal, "reg(%08x, %08x)" NL, |
| 43 | commac->tx_chan_mask, commac->rx_chan_mask); |
| 44 | |
| 45 | /* Don't let multiple commacs claim the same channel(s) */ |
| 46 | if ((mal->tx_chan_mask & commac->tx_chan_mask) || |
| 47 | (mal->rx_chan_mask & commac->rx_chan_mask)) { |
| 48 | spin_unlock_irqrestore(&mal->lock, flags); |
| 49 | printk(KERN_WARNING "mal%d: COMMAC channels conflict!\n", |
| 50 | mal->index); |
| 51 | return -EBUSY; |
| 52 | } |
| 53 | |
Benjamin Herrenschmidt | b3e441c | 2007-10-16 15:40:50 +1000 | [diff] [blame] | 54 | if (list_empty(&mal->list)) |
| 55 | napi_enable(&mal->napi); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 56 | mal->tx_chan_mask |= commac->tx_chan_mask; |
| 57 | mal->rx_chan_mask |= commac->rx_chan_mask; |
| 58 | list_add(&commac->list, &mal->list); |
| 59 | |
| 60 | spin_unlock_irqrestore(&mal->lock, flags); |
| 61 | |
| 62 | return 0; |
| 63 | } |
| 64 | |
Josh Boyer | 51d4a1c | 2008-04-22 10:46:43 +1000 | [diff] [blame] | 65 | void mal_unregister_commac(struct mal_instance *mal, |
| 66 | struct mal_commac *commac) |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 67 | { |
| 68 | unsigned long flags; |
| 69 | |
| 70 | spin_lock_irqsave(&mal->lock, flags); |
| 71 | |
| 72 | MAL_DBG(mal, "unreg(%08x, %08x)" NL, |
| 73 | commac->tx_chan_mask, commac->rx_chan_mask); |
| 74 | |
| 75 | mal->tx_chan_mask &= ~commac->tx_chan_mask; |
| 76 | mal->rx_chan_mask &= ~commac->rx_chan_mask; |
| 77 | list_del_init(&commac->list); |
Benjamin Herrenschmidt | b3e441c | 2007-10-16 15:40:50 +1000 | [diff] [blame] | 78 | if (list_empty(&mal->list)) |
| 79 | napi_disable(&mal->napi); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 80 | |
| 81 | spin_unlock_irqrestore(&mal->lock, flags); |
| 82 | } |
| 83 | |
| 84 | int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size) |
| 85 | { |
| 86 | BUG_ON(channel < 0 || channel >= mal->num_rx_chans || |
| 87 | size > MAL_MAX_RX_SIZE); |
| 88 | |
| 89 | MAL_DBG(mal, "set_rbcs(%d, %lu)" NL, channel, size); |
| 90 | |
| 91 | if (size & 0xf) { |
| 92 | printk(KERN_WARNING |
| 93 | "mal%d: incorrect RX size %lu for the channel %d\n", |
| 94 | mal->index, size, channel); |
| 95 | return -EINVAL; |
| 96 | } |
| 97 | |
| 98 | set_mal_dcrn(mal, MAL_RCBS(channel), size >> 4); |
| 99 | return 0; |
| 100 | } |
| 101 | |
| 102 | int mal_tx_bd_offset(struct mal_instance *mal, int channel) |
| 103 | { |
| 104 | BUG_ON(channel < 0 || channel >= mal->num_tx_chans); |
| 105 | |
| 106 | return channel * NUM_TX_BUFF; |
| 107 | } |
| 108 | |
| 109 | int mal_rx_bd_offset(struct mal_instance *mal, int channel) |
| 110 | { |
| 111 | BUG_ON(channel < 0 || channel >= mal->num_rx_chans); |
| 112 | return mal->num_tx_chans * NUM_TX_BUFF + channel * NUM_RX_BUFF; |
| 113 | } |
| 114 | |
| 115 | void mal_enable_tx_channel(struct mal_instance *mal, int channel) |
| 116 | { |
| 117 | unsigned long flags; |
| 118 | |
| 119 | spin_lock_irqsave(&mal->lock, flags); |
| 120 | |
| 121 | MAL_DBG(mal, "enable_tx(%d)" NL, channel); |
| 122 | |
| 123 | set_mal_dcrn(mal, MAL_TXCASR, |
| 124 | get_mal_dcrn(mal, MAL_TXCASR) | MAL_CHAN_MASK(channel)); |
| 125 | |
| 126 | spin_unlock_irqrestore(&mal->lock, flags); |
| 127 | } |
| 128 | |
| 129 | void mal_disable_tx_channel(struct mal_instance *mal, int channel) |
| 130 | { |
| 131 | set_mal_dcrn(mal, MAL_TXCARR, MAL_CHAN_MASK(channel)); |
| 132 | |
| 133 | MAL_DBG(mal, "disable_tx(%d)" NL, channel); |
| 134 | } |
| 135 | |
| 136 | void mal_enable_rx_channel(struct mal_instance *mal, int channel) |
| 137 | { |
| 138 | unsigned long flags; |
| 139 | |
Stefan Roese | afd1dee | 2008-04-22 10:46:42 +1000 | [diff] [blame] | 140 | /* |
| 141 | * On some 4xx PPC's (e.g. 460EX/GT), the rx channel is a multiple |
| 142 | * of 8, but enabling in MAL_RXCASR needs the divided by 8 value |
| 143 | * for the bitmask |
| 144 | */ |
| 145 | if (!(channel % 8)) |
| 146 | channel >>= 3; |
| 147 | |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 148 | spin_lock_irqsave(&mal->lock, flags); |
| 149 | |
| 150 | MAL_DBG(mal, "enable_rx(%d)" NL, channel); |
| 151 | |
| 152 | set_mal_dcrn(mal, MAL_RXCASR, |
| 153 | get_mal_dcrn(mal, MAL_RXCASR) | MAL_CHAN_MASK(channel)); |
| 154 | |
| 155 | spin_unlock_irqrestore(&mal->lock, flags); |
| 156 | } |
| 157 | |
| 158 | void mal_disable_rx_channel(struct mal_instance *mal, int channel) |
| 159 | { |
Stefan Roese | afd1dee | 2008-04-22 10:46:42 +1000 | [diff] [blame] | 160 | /* |
| 161 | * On some 4xx PPC's (e.g. 460EX/GT), the rx channel is a multiple |
| 162 | * of 8, but enabling in MAL_RXCASR needs the divided by 8 value |
| 163 | * for the bitmask |
| 164 | */ |
| 165 | if (!(channel % 8)) |
| 166 | channel >>= 3; |
| 167 | |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 168 | set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel)); |
| 169 | |
| 170 | MAL_DBG(mal, "disable_rx(%d)" NL, channel); |
| 171 | } |
| 172 | |
| 173 | void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac) |
| 174 | { |
| 175 | unsigned long flags; |
| 176 | |
| 177 | spin_lock_irqsave(&mal->lock, flags); |
| 178 | |
| 179 | MAL_DBG(mal, "poll_add(%p)" NL, commac); |
| 180 | |
| 181 | /* starts disabled */ |
| 182 | set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags); |
| 183 | |
| 184 | list_add_tail(&commac->poll_list, &mal->poll_list); |
| 185 | |
| 186 | spin_unlock_irqrestore(&mal->lock, flags); |
| 187 | } |
| 188 | |
| 189 | void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac) |
| 190 | { |
| 191 | unsigned long flags; |
| 192 | |
| 193 | spin_lock_irqsave(&mal->lock, flags); |
| 194 | |
| 195 | MAL_DBG(mal, "poll_del(%p)" NL, commac); |
| 196 | |
| 197 | list_del(&commac->poll_list); |
| 198 | |
| 199 | spin_unlock_irqrestore(&mal->lock, flags); |
| 200 | } |
| 201 | |
| 202 | /* synchronized by mal_poll() */ |
| 203 | static inline void mal_enable_eob_irq(struct mal_instance *mal) |
| 204 | { |
| 205 | MAL_DBG2(mal, "enable_irq" NL); |
| 206 | |
| 207 | // XXX might want to cache MAL_CFG as the DCR read can be slooooow |
| 208 | set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) | MAL_CFG_EOPIE); |
| 209 | } |
| 210 | |
Benjamin Herrenschmidt | b3e441c | 2007-10-16 15:40:50 +1000 | [diff] [blame] | 211 | /* synchronized by NAPI state */ |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 212 | static inline void mal_disable_eob_irq(struct mal_instance *mal) |
| 213 | { |
| 214 | // XXX might want to cache MAL_CFG as the DCR read can be slooooow |
| 215 | set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) & ~MAL_CFG_EOPIE); |
| 216 | |
| 217 | MAL_DBG2(mal, "disable_irq" NL); |
| 218 | } |
| 219 | |
| 220 | static irqreturn_t mal_serr(int irq, void *dev_instance) |
| 221 | { |
| 222 | struct mal_instance *mal = dev_instance; |
| 223 | |
| 224 | u32 esr = get_mal_dcrn(mal, MAL_ESR); |
| 225 | |
| 226 | /* Clear the error status register */ |
| 227 | set_mal_dcrn(mal, MAL_ESR, esr); |
| 228 | |
| 229 | MAL_DBG(mal, "SERR %08x" NL, esr); |
| 230 | |
| 231 | if (esr & MAL_ESR_EVB) { |
| 232 | if (esr & MAL_ESR_DE) { |
| 233 | /* We ignore Descriptor error, |
| 234 | * TXDE or RXDE interrupt will be generated anyway. |
| 235 | */ |
| 236 | return IRQ_HANDLED; |
| 237 | } |
| 238 | |
| 239 | if (esr & MAL_ESR_PEIN) { |
| 240 | /* PLB error, it's probably buggy hardware or |
| 241 | * incorrect physical address in BD (i.e. bug) |
| 242 | */ |
| 243 | if (net_ratelimit()) |
| 244 | printk(KERN_ERR |
| 245 | "mal%d: system error, " |
| 246 | "PLB (ESR = 0x%08x)\n", |
| 247 | mal->index, esr); |
| 248 | return IRQ_HANDLED; |
| 249 | } |
| 250 | |
| 251 | /* OPB error, it's probably buggy hardware or incorrect |
| 252 | * EBC setup |
| 253 | */ |
| 254 | if (net_ratelimit()) |
| 255 | printk(KERN_ERR |
| 256 | "mal%d: system error, OPB (ESR = 0x%08x)\n", |
| 257 | mal->index, esr); |
| 258 | } |
| 259 | return IRQ_HANDLED; |
| 260 | } |
| 261 | |
| 262 | static inline void mal_schedule_poll(struct mal_instance *mal) |
| 263 | { |
Roland Dreier | 59e90b2 | 2007-10-09 15:48:56 -0700 | [diff] [blame] | 264 | if (likely(napi_schedule_prep(&mal->napi))) { |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 265 | MAL_DBG2(mal, "schedule_poll" NL); |
| 266 | mal_disable_eob_irq(mal); |
Roland Dreier | 59e90b2 | 2007-10-09 15:48:56 -0700 | [diff] [blame] | 267 | __napi_schedule(&mal->napi); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 268 | } else |
| 269 | MAL_DBG2(mal, "already in poll" NL); |
| 270 | } |
| 271 | |
| 272 | static irqreturn_t mal_txeob(int irq, void *dev_instance) |
| 273 | { |
| 274 | struct mal_instance *mal = dev_instance; |
| 275 | |
| 276 | u32 r = get_mal_dcrn(mal, MAL_TXEOBISR); |
| 277 | |
| 278 | MAL_DBG2(mal, "txeob %08x" NL, r); |
| 279 | |
| 280 | mal_schedule_poll(mal); |
| 281 | set_mal_dcrn(mal, MAL_TXEOBISR, r); |
| 282 | |
Josh Boyer | 1ff0fcf | 2008-10-16 04:38:40 +0000 | [diff] [blame] | 283 | #ifdef CONFIG_PPC_DCR_NATIVE |
Josh Boyer | fbcc4ba | 2008-09-04 04:08:20 +0000 | [diff] [blame] | 284 | if (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT)) |
| 285 | mtdcri(SDR0, DCRN_SDR_ICINTSTAT, |
| 286 | (mfdcri(SDR0, DCRN_SDR_ICINTSTAT) | ICINTSTAT_ICTX)); |
Josh Boyer | 1ff0fcf | 2008-10-16 04:38:40 +0000 | [diff] [blame] | 287 | #endif |
Josh Boyer | fbcc4ba | 2008-09-04 04:08:20 +0000 | [diff] [blame] | 288 | |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 289 | return IRQ_HANDLED; |
| 290 | } |
| 291 | |
| 292 | static irqreturn_t mal_rxeob(int irq, void *dev_instance) |
| 293 | { |
| 294 | struct mal_instance *mal = dev_instance; |
| 295 | |
| 296 | u32 r = get_mal_dcrn(mal, MAL_RXEOBISR); |
| 297 | |
| 298 | MAL_DBG2(mal, "rxeob %08x" NL, r); |
| 299 | |
| 300 | mal_schedule_poll(mal); |
| 301 | set_mal_dcrn(mal, MAL_RXEOBISR, r); |
| 302 | |
Josh Boyer | 1ff0fcf | 2008-10-16 04:38:40 +0000 | [diff] [blame] | 303 | #ifdef CONFIG_PPC_DCR_NATIVE |
Josh Boyer | fbcc4ba | 2008-09-04 04:08:20 +0000 | [diff] [blame] | 304 | if (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT)) |
| 305 | mtdcri(SDR0, DCRN_SDR_ICINTSTAT, |
| 306 | (mfdcri(SDR0, DCRN_SDR_ICINTSTAT) | ICINTSTAT_ICRX)); |
Josh Boyer | 1ff0fcf | 2008-10-16 04:38:40 +0000 | [diff] [blame] | 307 | #endif |
Josh Boyer | fbcc4ba | 2008-09-04 04:08:20 +0000 | [diff] [blame] | 308 | |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 309 | return IRQ_HANDLED; |
| 310 | } |
| 311 | |
| 312 | static irqreturn_t mal_txde(int irq, void *dev_instance) |
| 313 | { |
| 314 | struct mal_instance *mal = dev_instance; |
| 315 | |
| 316 | u32 deir = get_mal_dcrn(mal, MAL_TXDEIR); |
| 317 | set_mal_dcrn(mal, MAL_TXDEIR, deir); |
| 318 | |
| 319 | MAL_DBG(mal, "txde %08x" NL, deir); |
| 320 | |
| 321 | if (net_ratelimit()) |
| 322 | printk(KERN_ERR |
| 323 | "mal%d: TX descriptor error (TXDEIR = 0x%08x)\n", |
| 324 | mal->index, deir); |
| 325 | |
| 326 | return IRQ_HANDLED; |
| 327 | } |
| 328 | |
| 329 | static irqreturn_t mal_rxde(int irq, void *dev_instance) |
| 330 | { |
| 331 | struct mal_instance *mal = dev_instance; |
| 332 | struct list_head *l; |
| 333 | |
| 334 | u32 deir = get_mal_dcrn(mal, MAL_RXDEIR); |
| 335 | |
| 336 | MAL_DBG(mal, "rxde %08x" NL, deir); |
| 337 | |
| 338 | list_for_each(l, &mal->list) { |
| 339 | struct mal_commac *mc = list_entry(l, struct mal_commac, list); |
| 340 | if (deir & mc->rx_chan_mask) { |
| 341 | set_bit(MAL_COMMAC_RX_STOPPED, &mc->flags); |
| 342 | mc->ops->rxde(mc->dev); |
| 343 | } |
| 344 | } |
| 345 | |
| 346 | mal_schedule_poll(mal); |
| 347 | set_mal_dcrn(mal, MAL_RXDEIR, deir); |
| 348 | |
| 349 | return IRQ_HANDLED; |
| 350 | } |
| 351 | |
Josh Boyer | fbcc4ba | 2008-09-04 04:08:20 +0000 | [diff] [blame] | 352 | static irqreturn_t mal_int(int irq, void *dev_instance) |
| 353 | { |
| 354 | struct mal_instance *mal = dev_instance; |
| 355 | u32 esr = get_mal_dcrn(mal, MAL_ESR); |
| 356 | |
| 357 | if (esr & MAL_ESR_EVB) { |
| 358 | /* descriptor error */ |
| 359 | if (esr & MAL_ESR_DE) { |
| 360 | if (esr & MAL_ESR_CIDT) |
| 361 | return mal_rxde(irq, dev_instance); |
| 362 | else |
| 363 | return mal_txde(irq, dev_instance); |
| 364 | } else { /* SERR */ |
| 365 | return mal_serr(irq, dev_instance); |
| 366 | } |
| 367 | } |
| 368 | return IRQ_HANDLED; |
| 369 | } |
| 370 | |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 371 | void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac) |
| 372 | { |
| 373 | /* Spinlock-type semantics: only one caller disable poll at a time */ |
| 374 | while (test_and_set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags)) |
| 375 | msleep(1); |
| 376 | |
Benjamin Herrenschmidt | b3e441c | 2007-10-16 15:40:50 +1000 | [diff] [blame] | 377 | /* Synchronize with the MAL NAPI poller */ |
Benjamin Herrenschmidt | e30d422 | 2007-10-18 09:14:03 +1000 | [diff] [blame] | 378 | napi_synchronize(&mal->napi); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 379 | } |
| 380 | |
| 381 | void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac) |
| 382 | { |
| 383 | smp_wmb(); |
| 384 | clear_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags); |
| 385 | |
Benjamin Herrenschmidt | b3e441c | 2007-10-16 15:40:50 +1000 | [diff] [blame] | 386 | /* Feels better to trigger a poll here to catch up with events that |
| 387 | * may have happened on this channel while disabled. It will most |
| 388 | * probably be delayed until the next interrupt but that's mostly a |
| 389 | * non-issue in the context where this is called. |
| 390 | */ |
| 391 | napi_schedule(&mal->napi); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 392 | } |
| 393 | |
Roland Dreier | 59e90b2 | 2007-10-09 15:48:56 -0700 | [diff] [blame] | 394 | static int mal_poll(struct napi_struct *napi, int budget) |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 395 | { |
Roland Dreier | 59e90b2 | 2007-10-09 15:48:56 -0700 | [diff] [blame] | 396 | struct mal_instance *mal = container_of(napi, struct mal_instance, napi); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 397 | struct list_head *l; |
Roland Dreier | 59e90b2 | 2007-10-09 15:48:56 -0700 | [diff] [blame] | 398 | int received = 0; |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 399 | unsigned long flags; |
| 400 | |
Benjamin Herrenschmidt | b3e441c | 2007-10-16 15:40:50 +1000 | [diff] [blame] | 401 | MAL_DBG2(mal, "poll(%d)" NL, budget); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 402 | again: |
| 403 | /* Process TX skbs */ |
| 404 | list_for_each(l, &mal->poll_list) { |
| 405 | struct mal_commac *mc = |
| 406 | list_entry(l, struct mal_commac, poll_list); |
| 407 | mc->ops->poll_tx(mc->dev); |
| 408 | } |
| 409 | |
| 410 | /* Process RX skbs. |
| 411 | * |
| 412 | * We _might_ need something more smart here to enforce polling |
| 413 | * fairness. |
| 414 | */ |
| 415 | list_for_each(l, &mal->poll_list) { |
| 416 | struct mal_commac *mc = |
| 417 | list_entry(l, struct mal_commac, poll_list); |
| 418 | int n; |
| 419 | if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags))) |
| 420 | continue; |
Roland Dreier | 59e90b2 | 2007-10-09 15:48:56 -0700 | [diff] [blame] | 421 | n = mc->ops->poll_rx(mc->dev, budget); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 422 | if (n) { |
| 423 | received += n; |
Roland Dreier | 59e90b2 | 2007-10-09 15:48:56 -0700 | [diff] [blame] | 424 | budget -= n; |
| 425 | if (budget <= 0) |
| 426 | goto more_work; // XXX What if this is the last one ? |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 427 | } |
| 428 | } |
| 429 | |
| 430 | /* We need to disable IRQs to protect from RXDE IRQ here */ |
| 431 | spin_lock_irqsave(&mal->lock, flags); |
Roland Dreier | 59e90b2 | 2007-10-09 15:48:56 -0700 | [diff] [blame] | 432 | __napi_complete(napi); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 433 | mal_enable_eob_irq(mal); |
| 434 | spin_unlock_irqrestore(&mal->lock, flags); |
| 435 | |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 436 | /* Check for "rotting" packet(s) */ |
| 437 | list_for_each(l, &mal->poll_list) { |
| 438 | struct mal_commac *mc = |
| 439 | list_entry(l, struct mal_commac, poll_list); |
| 440 | if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags))) |
| 441 | continue; |
| 442 | if (unlikely(mc->ops->peek_rx(mc->dev) || |
| 443 | test_bit(MAL_COMMAC_RX_STOPPED, &mc->flags))) { |
| 444 | MAL_DBG2(mal, "rotting packet" NL); |
Alistair Popple | b4dfd32 | 2013-10-30 10:50:37 +1100 | [diff] [blame^] | 445 | if (!napi_reschedule(napi)) |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 446 | goto more_work; |
Alistair Popple | b4dfd32 | 2013-10-30 10:50:37 +1100 | [diff] [blame^] | 447 | |
| 448 | mal_disable_eob_irq(mal); |
| 449 | goto again; |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 450 | } |
| 451 | mc->ops->poll_tx(mc->dev); |
| 452 | } |
| 453 | |
| 454 | more_work: |
Roland Dreier | 59e90b2 | 2007-10-09 15:48:56 -0700 | [diff] [blame] | 455 | MAL_DBG2(mal, "poll() %d <- %d" NL, budget, received); |
| 456 | return received; |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 457 | } |
| 458 | |
| 459 | static void mal_reset(struct mal_instance *mal) |
| 460 | { |
| 461 | int n = 10; |
| 462 | |
| 463 | MAL_DBG(mal, "reset" NL); |
| 464 | |
| 465 | set_mal_dcrn(mal, MAL_CFG, MAL_CFG_SR); |
| 466 | |
| 467 | /* Wait for reset to complete (1 system clock) */ |
| 468 | while ((get_mal_dcrn(mal, MAL_CFG) & MAL_CFG_SR) && n) |
| 469 | --n; |
| 470 | |
| 471 | if (unlikely(!n)) |
| 472 | printk(KERN_ERR "mal%d: reset timeout\n", mal->index); |
| 473 | } |
| 474 | |
| 475 | int mal_get_regs_len(struct mal_instance *mal) |
| 476 | { |
| 477 | return sizeof(struct emac_ethtool_regs_subhdr) + |
| 478 | sizeof(struct mal_regs); |
| 479 | } |
| 480 | |
| 481 | void *mal_dump_regs(struct mal_instance *mal, void *buf) |
| 482 | { |
| 483 | struct emac_ethtool_regs_subhdr *hdr = buf; |
| 484 | struct mal_regs *regs = (struct mal_regs *)(hdr + 1); |
| 485 | int i; |
| 486 | |
| 487 | hdr->version = mal->version; |
| 488 | hdr->index = mal->index; |
| 489 | |
| 490 | regs->tx_count = mal->num_tx_chans; |
| 491 | regs->rx_count = mal->num_rx_chans; |
| 492 | |
| 493 | regs->cfg = get_mal_dcrn(mal, MAL_CFG); |
| 494 | regs->esr = get_mal_dcrn(mal, MAL_ESR); |
| 495 | regs->ier = get_mal_dcrn(mal, MAL_IER); |
| 496 | regs->tx_casr = get_mal_dcrn(mal, MAL_TXCASR); |
| 497 | regs->tx_carr = get_mal_dcrn(mal, MAL_TXCARR); |
| 498 | regs->tx_eobisr = get_mal_dcrn(mal, MAL_TXEOBISR); |
| 499 | regs->tx_deir = get_mal_dcrn(mal, MAL_TXDEIR); |
| 500 | regs->rx_casr = get_mal_dcrn(mal, MAL_RXCASR); |
| 501 | regs->rx_carr = get_mal_dcrn(mal, MAL_RXCARR); |
| 502 | regs->rx_eobisr = get_mal_dcrn(mal, MAL_RXEOBISR); |
| 503 | regs->rx_deir = get_mal_dcrn(mal, MAL_RXDEIR); |
| 504 | |
| 505 | for (i = 0; i < regs->tx_count; ++i) |
| 506 | regs->tx_ctpr[i] = get_mal_dcrn(mal, MAL_TXCTPR(i)); |
| 507 | |
| 508 | for (i = 0; i < regs->rx_count; ++i) { |
| 509 | regs->rx_ctpr[i] = get_mal_dcrn(mal, MAL_RXCTPR(i)); |
| 510 | regs->rcbs[i] = get_mal_dcrn(mal, MAL_RCBS(i)); |
| 511 | } |
| 512 | return regs + 1; |
| 513 | } |
| 514 | |
Bill Pemberton | fe17dc1 | 2012-12-03 09:23:13 -0500 | [diff] [blame] | 515 | static int mal_probe(struct platform_device *ofdev) |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 516 | { |
| 517 | struct mal_instance *mal; |
| 518 | int err = 0, i, bd_size; |
| 519 | int index = mal_count++; |
Michael Ellerman | 7920369 | 2007-10-15 19:34:34 +1000 | [diff] [blame] | 520 | unsigned int dcr_base; |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 521 | const u32 *prop; |
| 522 | u32 cfg; |
Josh Boyer | fbcc4ba | 2008-09-04 04:08:20 +0000 | [diff] [blame] | 523 | unsigned long irqflags; |
| 524 | irq_handler_t hdlr_serr, hdlr_txde, hdlr_rxde; |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 525 | |
| 526 | mal = kzalloc(sizeof(struct mal_instance), GFP_KERNEL); |
Joe Perches | b2adaca | 2013-02-03 17:43:58 +0000 | [diff] [blame] | 527 | if (!mal) |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 528 | return -ENOMEM; |
Joe Perches | b2adaca | 2013-02-03 17:43:58 +0000 | [diff] [blame] | 529 | |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 530 | mal->index = index; |
| 531 | mal->ofdev = ofdev; |
Grant Likely | 61c7a08 | 2010-04-13 16:12:29 -0700 | [diff] [blame] | 532 | mal->version = of_device_is_compatible(ofdev->dev.of_node, "ibm,mcmal2") ? 2 : 1; |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 533 | |
| 534 | MAL_DBG(mal, "probe" NL); |
| 535 | |
Grant Likely | 61c7a08 | 2010-04-13 16:12:29 -0700 | [diff] [blame] | 536 | prop = of_get_property(ofdev->dev.of_node, "num-tx-chans", NULL); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 537 | if (prop == NULL) { |
| 538 | printk(KERN_ERR |
| 539 | "mal%d: can't find MAL num-tx-chans property!\n", |
| 540 | index); |
| 541 | err = -ENODEV; |
| 542 | goto fail; |
| 543 | } |
| 544 | mal->num_tx_chans = prop[0]; |
| 545 | |
Grant Likely | 61c7a08 | 2010-04-13 16:12:29 -0700 | [diff] [blame] | 546 | prop = of_get_property(ofdev->dev.of_node, "num-rx-chans", NULL); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 547 | if (prop == NULL) { |
| 548 | printk(KERN_ERR |
| 549 | "mal%d: can't find MAL num-rx-chans property!\n", |
| 550 | index); |
| 551 | err = -ENODEV; |
| 552 | goto fail; |
| 553 | } |
| 554 | mal->num_rx_chans = prop[0]; |
| 555 | |
Grant Likely | 61c7a08 | 2010-04-13 16:12:29 -0700 | [diff] [blame] | 556 | dcr_base = dcr_resource_start(ofdev->dev.of_node, 0); |
Michael Ellerman | 7920369 | 2007-10-15 19:34:34 +1000 | [diff] [blame] | 557 | if (dcr_base == 0) { |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 558 | printk(KERN_ERR |
| 559 | "mal%d: can't find DCR resource!\n", index); |
| 560 | err = -ENODEV; |
| 561 | goto fail; |
| 562 | } |
Grant Likely | 61c7a08 | 2010-04-13 16:12:29 -0700 | [diff] [blame] | 563 | mal->dcr_host = dcr_map(ofdev->dev.of_node, dcr_base, 0x100); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 564 | if (!DCR_MAP_OK(mal->dcr_host)) { |
| 565 | printk(KERN_ERR |
| 566 | "mal%d: failed to map DCRs !\n", index); |
| 567 | err = -ENODEV; |
| 568 | goto fail; |
| 569 | } |
| 570 | |
Grant Likely | 61c7a08 | 2010-04-13 16:12:29 -0700 | [diff] [blame] | 571 | if (of_device_is_compatible(ofdev->dev.of_node, "ibm,mcmal-405ez")) { |
Tony Breeds | 3b3bceef | 2011-08-18 21:33:49 -0700 | [diff] [blame] | 572 | #if defined(CONFIG_IBM_EMAC_MAL_CLR_ICINTSTAT) && \ |
| 573 | defined(CONFIG_IBM_EMAC_MAL_COMMON_ERR) |
Josh Boyer | fbcc4ba | 2008-09-04 04:08:20 +0000 | [diff] [blame] | 574 | mal->features |= (MAL_FTR_CLEAR_ICINTSTAT | |
| 575 | MAL_FTR_COMMON_ERR_INT); |
Josh Boyer | 1ff0fcf | 2008-10-16 04:38:40 +0000 | [diff] [blame] | 576 | #else |
| 577 | printk(KERN_ERR "%s: Support for 405EZ not enabled!\n", |
Grant Likely | 61c7a08 | 2010-04-13 16:12:29 -0700 | [diff] [blame] | 578 | ofdev->dev.of_node->full_name); |
Josh Boyer | 1ff0fcf | 2008-10-16 04:38:40 +0000 | [diff] [blame] | 579 | err = -ENODEV; |
| 580 | goto fail; |
| 581 | #endif |
| 582 | } |
Josh Boyer | fbcc4ba | 2008-09-04 04:08:20 +0000 | [diff] [blame] | 583 | |
Grant Likely | 61c7a08 | 2010-04-13 16:12:29 -0700 | [diff] [blame] | 584 | mal->txeob_irq = irq_of_parse_and_map(ofdev->dev.of_node, 0); |
| 585 | mal->rxeob_irq = irq_of_parse_and_map(ofdev->dev.of_node, 1); |
| 586 | mal->serr_irq = irq_of_parse_and_map(ofdev->dev.of_node, 2); |
Josh Boyer | fbcc4ba | 2008-09-04 04:08:20 +0000 | [diff] [blame] | 587 | |
| 588 | if (mal_has_feature(mal, MAL_FTR_COMMON_ERR_INT)) { |
| 589 | mal->txde_irq = mal->rxde_irq = mal->serr_irq; |
| 590 | } else { |
Grant Likely | 61c7a08 | 2010-04-13 16:12:29 -0700 | [diff] [blame] | 591 | mal->txde_irq = irq_of_parse_and_map(ofdev->dev.of_node, 3); |
| 592 | mal->rxde_irq = irq_of_parse_and_map(ofdev->dev.of_node, 4); |
Josh Boyer | fbcc4ba | 2008-09-04 04:08:20 +0000 | [diff] [blame] | 593 | } |
| 594 | |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 595 | if (mal->txeob_irq == NO_IRQ || mal->rxeob_irq == NO_IRQ || |
| 596 | mal->serr_irq == NO_IRQ || mal->txde_irq == NO_IRQ || |
| 597 | mal->rxde_irq == NO_IRQ) { |
| 598 | printk(KERN_ERR |
| 599 | "mal%d: failed to map interrupts !\n", index); |
| 600 | err = -ENODEV; |
| 601 | goto fail_unmap; |
| 602 | } |
| 603 | |
| 604 | INIT_LIST_HEAD(&mal->poll_list); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 605 | INIT_LIST_HEAD(&mal->list); |
| 606 | spin_lock_init(&mal->lock); |
| 607 | |
Benjamin Herrenschmidt | 937f1ba | 2009-01-14 21:05:05 -0800 | [diff] [blame] | 608 | init_dummy_netdev(&mal->dummy_dev); |
| 609 | |
| 610 | netif_napi_add(&mal->dummy_dev, &mal->napi, mal_poll, |
Tony Breeds | 3b3bceef | 2011-08-18 21:33:49 -0700 | [diff] [blame] | 611 | CONFIG_IBM_EMAC_POLL_WEIGHT); |
Benjamin Herrenschmidt | b3e441c | 2007-10-16 15:40:50 +1000 | [diff] [blame] | 612 | |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 613 | /* Load power-on reset defaults */ |
| 614 | mal_reset(mal); |
| 615 | |
| 616 | /* Set the MAL configuration register */ |
| 617 | cfg = (mal->version == 2) ? MAL2_CFG_DEFAULT : MAL1_CFG_DEFAULT; |
| 618 | cfg |= MAL_CFG_PLBB | MAL_CFG_OPBBL | MAL_CFG_LEA; |
| 619 | |
| 620 | /* Current Axon is not happy with priority being non-0, it can |
| 621 | * deadlock, fix it up here |
| 622 | */ |
Grant Likely | 61c7a08 | 2010-04-13 16:12:29 -0700 | [diff] [blame] | 623 | if (of_device_is_compatible(ofdev->dev.of_node, "ibm,mcmal-axon")) |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 624 | cfg &= ~(MAL2_CFG_RPP_10 | MAL2_CFG_WPP_10); |
| 625 | |
| 626 | /* Apply configuration */ |
| 627 | set_mal_dcrn(mal, MAL_CFG, cfg); |
| 628 | |
| 629 | /* Allocate space for BD rings */ |
| 630 | BUG_ON(mal->num_tx_chans <= 0 || mal->num_tx_chans > 32); |
| 631 | BUG_ON(mal->num_rx_chans <= 0 || mal->num_rx_chans > 32); |
| 632 | |
| 633 | bd_size = sizeof(struct mal_descriptor) * |
| 634 | (NUM_TX_BUFF * mal->num_tx_chans + |
| 635 | NUM_RX_BUFF * mal->num_rx_chans); |
Joe Perches | ede23fa | 2013-08-26 22:45:23 -0700 | [diff] [blame] | 636 | mal->bd_virt = dma_zalloc_coherent(&ofdev->dev, bd_size, &mal->bd_dma, |
| 637 | GFP_KERNEL); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 638 | if (mal->bd_virt == NULL) { |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 639 | err = -ENOMEM; |
| 640 | goto fail_unmap; |
| 641 | } |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 642 | |
| 643 | for (i = 0; i < mal->num_tx_chans; ++i) |
| 644 | set_mal_dcrn(mal, MAL_TXCTPR(i), mal->bd_dma + |
| 645 | sizeof(struct mal_descriptor) * |
| 646 | mal_tx_bd_offset(mal, i)); |
| 647 | |
| 648 | for (i = 0; i < mal->num_rx_chans; ++i) |
| 649 | set_mal_dcrn(mal, MAL_RXCTPR(i), mal->bd_dma + |
| 650 | sizeof(struct mal_descriptor) * |
| 651 | mal_rx_bd_offset(mal, i)); |
| 652 | |
Josh Boyer | fbcc4ba | 2008-09-04 04:08:20 +0000 | [diff] [blame] | 653 | if (mal_has_feature(mal, MAL_FTR_COMMON_ERR_INT)) { |
| 654 | irqflags = IRQF_SHARED; |
| 655 | hdlr_serr = hdlr_txde = hdlr_rxde = mal_int; |
| 656 | } else { |
| 657 | irqflags = 0; |
| 658 | hdlr_serr = mal_serr; |
| 659 | hdlr_txde = mal_txde; |
| 660 | hdlr_rxde = mal_rxde; |
| 661 | } |
| 662 | |
| 663 | err = request_irq(mal->serr_irq, hdlr_serr, irqflags, "MAL SERR", mal); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 664 | if (err) |
| 665 | goto fail2; |
Josh Boyer | fbcc4ba | 2008-09-04 04:08:20 +0000 | [diff] [blame] | 666 | err = request_irq(mal->txde_irq, hdlr_txde, irqflags, "MAL TX DE", mal); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 667 | if (err) |
| 668 | goto fail3; |
| 669 | err = request_irq(mal->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal); |
| 670 | if (err) |
| 671 | goto fail4; |
Josh Boyer | fbcc4ba | 2008-09-04 04:08:20 +0000 | [diff] [blame] | 672 | err = request_irq(mal->rxde_irq, hdlr_rxde, irqflags, "MAL RX DE", mal); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 673 | if (err) |
| 674 | goto fail5; |
| 675 | err = request_irq(mal->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal); |
| 676 | if (err) |
| 677 | goto fail6; |
| 678 | |
| 679 | /* Enable all MAL SERR interrupt sources */ |
| 680 | if (mal->version == 2) |
| 681 | set_mal_dcrn(mal, MAL_IER, MAL2_IER_EVENTS); |
| 682 | else |
| 683 | set_mal_dcrn(mal, MAL_IER, MAL1_IER_EVENTS); |
| 684 | |
| 685 | /* Enable EOB interrupt */ |
| 686 | mal_enable_eob_irq(mal); |
| 687 | |
| 688 | printk(KERN_INFO |
| 689 | "MAL v%d %s, %d TX channels, %d RX channels\n", |
Grant Likely | 61c7a08 | 2010-04-13 16:12:29 -0700 | [diff] [blame] | 690 | mal->version, ofdev->dev.of_node->full_name, |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 691 | mal->num_tx_chans, mal->num_rx_chans); |
| 692 | |
| 693 | /* Advertise this instance to the rest of the world */ |
| 694 | wmb(); |
Jingoo Han | 8513fbd | 2013-05-23 00:52:31 +0000 | [diff] [blame] | 695 | platform_set_drvdata(ofdev, mal); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 696 | |
| 697 | mal_dbg_register(mal); |
| 698 | |
| 699 | return 0; |
| 700 | |
| 701 | fail6: |
| 702 | free_irq(mal->rxde_irq, mal); |
| 703 | fail5: |
| 704 | free_irq(mal->txeob_irq, mal); |
| 705 | fail4: |
| 706 | free_irq(mal->txde_irq, mal); |
| 707 | fail3: |
| 708 | free_irq(mal->serr_irq, mal); |
| 709 | fail2: |
| 710 | dma_free_coherent(&ofdev->dev, bd_size, mal->bd_virt, mal->bd_dma); |
| 711 | fail_unmap: |
Michael Ellerman | cdbd386 | 2007-10-15 19:34:37 +1000 | [diff] [blame] | 712 | dcr_unmap(mal->dcr_host, 0x100); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 713 | fail: |
| 714 | kfree(mal); |
| 715 | |
| 716 | return err; |
| 717 | } |
| 718 | |
Bill Pemberton | fe17dc1 | 2012-12-03 09:23:13 -0500 | [diff] [blame] | 719 | static int mal_remove(struct platform_device *ofdev) |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 720 | { |
Jingoo Han | 8513fbd | 2013-05-23 00:52:31 +0000 | [diff] [blame] | 721 | struct mal_instance *mal = platform_get_drvdata(ofdev); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 722 | |
| 723 | MAL_DBG(mal, "remove" NL); |
| 724 | |
Roland Dreier | 59e90b2 | 2007-10-09 15:48:56 -0700 | [diff] [blame] | 725 | /* Synchronize with scheduled polling */ |
| 726 | napi_disable(&mal->napi); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 727 | |
Julia Lawall | f7c3f96 | 2012-11-03 00:58:31 +0000 | [diff] [blame] | 728 | if (!list_empty(&mal->list)) |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 729 | /* This is *very* bad */ |
Julia Lawall | f7c3f96 | 2012-11-03 00:58:31 +0000 | [diff] [blame] | 730 | WARN(1, KERN_EMERG |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 731 | "mal%d: commac list is not empty on remove!\n", |
| 732 | mal->index); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 733 | |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 734 | free_irq(mal->serr_irq, mal); |
| 735 | free_irq(mal->txde_irq, mal); |
| 736 | free_irq(mal->txeob_irq, mal); |
| 737 | free_irq(mal->rxde_irq, mal); |
| 738 | free_irq(mal->rxeob_irq, mal); |
| 739 | |
| 740 | mal_reset(mal); |
| 741 | |
| 742 | mal_dbg_unregister(mal); |
| 743 | |
| 744 | dma_free_coherent(&ofdev->dev, |
| 745 | sizeof(struct mal_descriptor) * |
| 746 | (NUM_TX_BUFF * mal->num_tx_chans + |
| 747 | NUM_RX_BUFF * mal->num_rx_chans), mal->bd_virt, |
| 748 | mal->bd_dma); |
| 749 | kfree(mal); |
| 750 | |
| 751 | return 0; |
| 752 | } |
| 753 | |
| 754 | static struct of_device_id mal_platform_match[] = |
| 755 | { |
| 756 | { |
| 757 | .compatible = "ibm,mcmal", |
| 758 | }, |
| 759 | { |
| 760 | .compatible = "ibm,mcmal2", |
| 761 | }, |
| 762 | /* Backward compat */ |
| 763 | { |
| 764 | .type = "mcmal-dma", |
| 765 | .compatible = "ibm,mcmal", |
| 766 | }, |
| 767 | { |
| 768 | .type = "mcmal-dma", |
| 769 | .compatible = "ibm,mcmal2", |
| 770 | }, |
| 771 | {}, |
| 772 | }; |
| 773 | |
Grant Likely | 7488876 | 2011-02-22 21:05:51 -0700 | [diff] [blame] | 774 | static struct platform_driver mal_of_driver = { |
Grant Likely | 4018294 | 2010-04-13 16:13:02 -0700 | [diff] [blame] | 775 | .driver = { |
| 776 | .name = "mcmal", |
| 777 | .owner = THIS_MODULE, |
| 778 | .of_match_table = mal_platform_match, |
| 779 | }, |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 780 | .probe = mal_probe, |
| 781 | .remove = mal_remove, |
| 782 | }; |
| 783 | |
| 784 | int __init mal_init(void) |
| 785 | { |
Grant Likely | 7488876 | 2011-02-22 21:05:51 -0700 | [diff] [blame] | 786 | return platform_driver_register(&mal_of_driver); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 787 | } |
| 788 | |
| 789 | void mal_exit(void) |
| 790 | { |
Grant Likely | 7488876 | 2011-02-22 21:05:51 -0700 | [diff] [blame] | 791 | platform_driver_unregister(&mal_of_driver); |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 792 | } |