| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-at91/include/mach/debug-macro.S |
| 3 | * |
| 4 | * Copyright (C) 2003-2005 SAN People |
| 5 | * |
| 6 | * Debugging macro include header |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #include <mach/hardware.h> |
| 15 | #include <mach/at91_dbgu.h> |
| 16 | |
| Jean-Christophe PLAGNIOL-VILLARD | 13079a7 | 2011-11-02 01:43:31 +0800 | [diff] [blame] | 17 | #if defined(CONFIG_AT91_DEBUG_LL_DBGU0) |
| 18 | #define AT91_DBGU AT91_BASE_DBGU0 |
| 19 | #else |
| 20 | #define AT91_DBGU AT91_BASE_DBGU1 |
| 21 | #endif |
| 22 | |
| Nicolas Pitre | 639da5e | 2011-08-31 22:55:46 -0400 | [diff] [blame] | 23 | .macro addruart, rp, rv, tmp |
| Jean-Christophe PLAGNIOL-VILLARD | 13079a7 | 2011-11-02 01:43:31 +0800 | [diff] [blame] | 24 | ldr \rp, =AT91_DBGU @ System peripherals (phys address) |
| 25 | ldr \rv, =AT91_IO_P2V(AT91_DBGU) @ System peripherals (virt address) |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 26 | .endm |
| 27 | |
| 28 | .macro senduart,rd,rx |
| Jean-Christophe PLAGNIOL-VILLARD | 1ff5b1b | 2011-05-03 01:11:25 +0800 | [diff] [blame] | 29 | strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 30 | .endm |
| 31 | |
| 32 | .macro waituart,rd,rx |
| Jean-Christophe PLAGNIOL-VILLARD | 1ff5b1b | 2011-05-03 01:11:25 +0800 | [diff] [blame] | 33 | 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register |
| 34 | tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 35 | beq 1001b |
| 36 | .endm |
| 37 | |
| 38 | .macro busyuart,rd,rx |
| Jean-Christophe PLAGNIOL-VILLARD | 1ff5b1b | 2011-05-03 01:11:25 +0800 | [diff] [blame] | 39 | 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register |
| 40 | tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 41 | beq 1001b |
| 42 | .endm |
| 43 | |