Magnus Damm | f411fad | 2011-12-14 01:36:12 +0900 | [diff] [blame] | 1 | /* |
| 2 | * r8a7779 clock framework support |
| 3 | * |
| 4 | * Copyright (C) 2011 Renesas Solutions Corp. |
| 5 | * Copyright (C) 2011 Magnus Damm |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | */ |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/kernel.h> |
| 22 | #include <linux/io.h> |
| 23 | #include <linux/sh_clk.h> |
| 24 | #include <linux/clkdev.h> |
| 25 | #include <mach/common.h> |
| 26 | |
| 27 | #define FRQMR 0xffc80014 |
| 28 | #define MSTPCR0 0xffc80030 |
| 29 | #define MSTPCR1 0xffc80034 |
| 30 | #define MSTPCR3 0xffc8003c |
| 31 | #define MSTPSR1 0xffc80044 |
| 32 | #define MSTPSR4 0xffc80048 |
| 33 | #define MSTPSR6 0xffc8004c |
| 34 | #define MSTPCR4 0xffc80050 |
| 35 | #define MSTPCR5 0xffc80054 |
| 36 | #define MSTPCR6 0xffc80058 |
| 37 | #define MSTPCR7 0xffc80040 |
| 38 | |
| 39 | /* ioremap() through clock mapping mandatory to avoid |
| 40 | * collision with ARM coherent DMA virtual memory range. |
| 41 | */ |
| 42 | |
| 43 | static struct clk_mapping cpg_mapping = { |
| 44 | .phys = 0xffc80000, |
| 45 | .len = 0x80, |
| 46 | }; |
| 47 | |
Kuninori Morimoto | b5813c7 | 2011-12-20 00:52:06 -0800 | [diff] [blame^] | 48 | /* |
| 49 | * Default rate for the root input clock, reset this with clk_set_rate() |
| 50 | * from the platform code. |
| 51 | */ |
| 52 | static struct clk plla_clk = { |
| 53 | .rate = 1500000000, |
| 54 | .mapping = &cpg_mapping, |
Magnus Damm | f411fad | 2011-12-14 01:36:12 +0900 | [diff] [blame] | 55 | }; |
| 56 | |
| 57 | static struct clk *main_clks[] = { |
Kuninori Morimoto | b5813c7 | 2011-12-20 00:52:06 -0800 | [diff] [blame^] | 58 | &plla_clk, |
| 59 | }; |
| 60 | |
| 61 | static int divisors[] = { 0, 0, 0, 6, 8, 12, 16, 0, 24, 32, 36, 0, 0, 0, 0, 0 }; |
| 62 | |
| 63 | static struct clk_div_mult_table div4_div_mult_table = { |
| 64 | .divisors = divisors, |
| 65 | .nr_divisors = ARRAY_SIZE(divisors), |
| 66 | }; |
| 67 | |
| 68 | static struct clk_div4_table div4_table = { |
| 69 | .div_mult_table = &div4_div_mult_table, |
| 70 | }; |
| 71 | |
| 72 | enum { DIV4_S, DIV4_OUT, DIV4_S4, DIV4_S3, DIV4_S1, DIV4_P, DIV4_NR }; |
| 73 | |
| 74 | static struct clk div4_clks[DIV4_NR] = { |
| 75 | [DIV4_S] = SH_CLK_DIV4(&plla_clk, FRQMR, 20, |
| 76 | 0x0018, CLK_ENABLE_ON_INIT), |
| 77 | [DIV4_OUT] = SH_CLK_DIV4(&plla_clk, FRQMR, 16, |
| 78 | 0x0700, CLK_ENABLE_ON_INIT), |
| 79 | [DIV4_S4] = SH_CLK_DIV4(&plla_clk, FRQMR, 12, |
| 80 | 0x0040, CLK_ENABLE_ON_INIT), |
| 81 | [DIV4_S3] = SH_CLK_DIV4(&plla_clk, FRQMR, 8, |
| 82 | 0x0010, CLK_ENABLE_ON_INIT), |
| 83 | [DIV4_S1] = SH_CLK_DIV4(&plla_clk, FRQMR, 4, |
| 84 | 0x0060, CLK_ENABLE_ON_INIT), |
| 85 | [DIV4_P] = SH_CLK_DIV4(&plla_clk, FRQMR, 0, |
| 86 | 0x0300, CLK_ENABLE_ON_INIT), |
Magnus Damm | f411fad | 2011-12-14 01:36:12 +0900 | [diff] [blame] | 87 | }; |
| 88 | |
| 89 | enum { MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, |
| 90 | MSTP016, MSTP015, MSTP014, |
| 91 | MSTP_NR }; |
| 92 | |
Magnus Damm | f411fad | 2011-12-14 01:36:12 +0900 | [diff] [blame] | 93 | static struct clk mstp_clks[MSTP_NR] = { |
Kuninori Morimoto | b5813c7 | 2011-12-20 00:52:06 -0800 | [diff] [blame^] | 94 | [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */ |
| 95 | [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */ |
| 96 | [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */ |
| 97 | [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), /* SCIF3 */ |
| 98 | [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), /* SCIF4 */ |
| 99 | [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), /* SCIF5 */ |
| 100 | [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), /* TMU0 */ |
| 101 | [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), /* TMU1 */ |
| 102 | [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), /* TMU2 */ |
Magnus Damm | f411fad | 2011-12-14 01:36:12 +0900 | [diff] [blame] | 103 | }; |
| 104 | |
| 105 | static struct clk_lookup lookups[] = { |
Kuninori Morimoto | b5813c7 | 2011-12-20 00:52:06 -0800 | [diff] [blame^] | 106 | /* main clocks */ |
| 107 | CLKDEV_CON_ID("plla_clk", &plla_clk), |
| 108 | |
| 109 | /* DIV4 clocks */ |
| 110 | CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]), |
| 111 | CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_OUT]), |
| 112 | CLKDEV_CON_ID("shyway4_clk", &div4_clks[DIV4_S4]), |
| 113 | CLKDEV_CON_ID("shyway3_clk", &div4_clks[DIV4_S3]), |
| 114 | CLKDEV_CON_ID("shyway1_clk", &div4_clks[DIV4_S1]), |
| 115 | CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), |
| 116 | |
Magnus Damm | f411fad | 2011-12-14 01:36:12 +0900 | [diff] [blame] | 117 | /* MSTP32 clocks */ |
| 118 | CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */ |
| 119 | CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */ |
| 120 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ |
| 121 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ |
| 122 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ |
| 123 | CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */ |
| 124 | CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */ |
| 125 | CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */ |
| 126 | }; |
| 127 | |
| 128 | void __init r8a7779_clock_init(void) |
| 129 | { |
| 130 | int k, ret = 0; |
| 131 | |
| 132 | for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) |
| 133 | ret = clk_register(main_clks[k]); |
| 134 | |
| 135 | if (!ret) |
Kuninori Morimoto | b5813c7 | 2011-12-20 00:52:06 -0800 | [diff] [blame^] | 136 | ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); |
| 137 | |
| 138 | if (!ret) |
Magnus Damm | f411fad | 2011-12-14 01:36:12 +0900 | [diff] [blame] | 139 | ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); |
| 140 | |
| 141 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); |
| 142 | |
| 143 | if (!ret) |
| 144 | clk_init(); |
| 145 | else |
| 146 | panic("failed to setup r8a7779 clocks\n"); |
| 147 | } |