blob: b047bf48750638539c343971c0871043ec6e1cc3 [file] [log] [blame]
Neil Zhang75b1bdf2012-05-03 14:19:13 +08001/*
2 * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#ifndef __ASM_ARCH_REGS_USB_H
11#define __ASM_ARCH_REGS_USB_H
12
13#define PXA168_U2O_REGBASE (0xd4208000)
14#define PXA168_U2O_PHYBASE (0xd4207000)
15
16#define PXA168_U2H_REGBASE (0xd4209000)
17#define PXA168_U2H_PHYBASE (0xd4206000)
18
19#define MMP3_HSIC1_REGBASE (0xf0001000)
20#define MMP3_HSIC1_PHYBASE (0xf0001800)
21
22#define MMP3_HSIC2_REGBASE (0xf0002000)
23#define MMP3_HSIC2_PHYBASE (0xf0002800)
24
25#define MMP3_FSIC_REGBASE (0xf0003000)
26#define MMP3_FSIC_PHYBASE (0xf0003800)
27
28
29#define USB_REG_RANGE (0x1ff)
30#define USB_PHY_RANGE (0xff)
31
32/* registers */
33#define U2x_CAPREGS_OFFSET 0x100
34
35/* phy regs */
36#define UTMI_REVISION 0x0
37#define UTMI_CTRL 0x4
38#define UTMI_PLL 0x8
39#define UTMI_TX 0xc
40#define UTMI_RX 0x10
41#define UTMI_IVREF 0x14
42#define UTMI_T0 0x18
43#define UTMI_T1 0x1c
44#define UTMI_T2 0x20
45#define UTMI_T3 0x24
46#define UTMI_T4 0x28
47#define UTMI_T5 0x2c
48#define UTMI_RESERVE 0x30
49#define UTMI_USB_INT 0x34
50#define UTMI_DBG_CTL 0x38
51#define UTMI_OTG_ADDON 0x3c
52
53/* For UTMICTRL Register */
54#define UTMI_CTRL_USB_CLK_EN (1 << 31)
55/* pxa168 */
56#define UTMI_CTRL_SUSPEND_SET1 (1 << 30)
57#define UTMI_CTRL_SUSPEND_SET2 (1 << 29)
58#define UTMI_CTRL_RXBUF_PDWN (1 << 24)
59#define UTMI_CTRL_TXBUF_PDWN (1 << 11)
60
61#define UTMI_CTRL_INPKT_DELAY_SHIFT 30
62#define UTMI_CTRL_INPKT_DELAY_SOF_SHIFT 28
63#define UTMI_CTRL_PU_REF_SHIFT 20
64#define UTMI_CTRL_ARC_PULLDN_SHIFT 12
65#define UTMI_CTRL_PLL_PWR_UP_SHIFT 1
66#define UTMI_CTRL_PWR_UP_SHIFT 0
67
68/* For UTMI_PLL Register */
69#define UTMI_PLL_PLLCALI12_SHIFT 29
70#define UTMI_PLL_PLLCALI12_MASK (0x3 << 29)
71
72#define UTMI_PLL_PLLVDD18_SHIFT 27
73#define UTMI_PLL_PLLVDD18_MASK (0x3 << 27)
74
75#define UTMI_PLL_PLLVDD12_SHIFT 25
76#define UTMI_PLL_PLLVDD12_MASK (0x3 << 25)
77
78#define UTMI_PLL_CLK_BLK_EN_SHIFT 24
79#define CLK_BLK_EN (0x1 << 24)
80#define PLL_READY (0x1 << 23)
81#define KVCO_EXT (0x1 << 22)
82#define VCOCAL_START (0x1 << 21)
83
84#define UTMI_PLL_KVCO_SHIFT 15
85#define UTMI_PLL_KVCO_MASK (0x7 << 15)
86
87#define UTMI_PLL_ICP_SHIFT 12
88#define UTMI_PLL_ICP_MASK (0x7 << 12)
89
90#define UTMI_PLL_FBDIV_SHIFT 4
91#define UTMI_PLL_FBDIV_MASK (0xFF << 4)
92
93#define UTMI_PLL_REFDIV_SHIFT 0
94#define UTMI_PLL_REFDIV_MASK (0xF << 0)
95
96/* For UTMI_TX Register */
97#define UTMI_TX_REG_EXT_FS_RCAL_SHIFT 27
98#define UTMI_TX_REG_EXT_FS_RCAL_MASK (0xf << 27)
99
100#define UTMI_TX_REG_EXT_FS_RCAL_EN_SHIFT 26
101#define UTMI_TX_REG_EXT_FS_RCAL_EN_MASK (0x1 << 26)
102
103#define UTMI_TX_TXVDD12_SHIFT 22
104#define UTMI_TX_TXVDD12_MASK (0x3 << 22)
105
106#define UTMI_TX_CK60_PHSEL_SHIFT 17
107#define UTMI_TX_CK60_PHSEL_MASK (0xf << 17)
108
109#define UTMI_TX_IMPCAL_VTH_SHIFT 14
110#define UTMI_TX_IMPCAL_VTH_MASK (0x7 << 14)
111
112#define REG_RCAL_START (0x1 << 12)
113
114#define UTMI_TX_LOW_VDD_EN_SHIFT 11
115
116#define UTMI_TX_AMP_SHIFT 0
117#define UTMI_TX_AMP_MASK (0x7 << 0)
118
119/* For UTMI_RX Register */
120#define UTMI_REG_SQ_LENGTH_SHIFT 15
121#define UTMI_REG_SQ_LENGTH_MASK (0x3 << 15)
122
123#define UTMI_RX_SQ_THRESH_SHIFT 4
124#define UTMI_RX_SQ_THRESH_MASK (0xf << 4)
125
126#define UTMI_OTG_ADDON_OTG_ON (1 << 0)
127
128/* For MMP3 USB Phy */
129#define USB2_PLL_REG0 0x4
130#define USB2_PLL_REG1 0x8
131#define USB2_TX_REG0 0x10
132#define USB2_TX_REG1 0x14
133#define USB2_TX_REG2 0x18
134#define USB2_RX_REG0 0x20
135#define USB2_RX_REG1 0x24
136#define USB2_RX_REG2 0x28
137#define USB2_ANA_REG0 0x30
138#define USB2_ANA_REG1 0x34
139#define USB2_ANA_REG2 0x38
140#define USB2_DIG_REG0 0x3C
141#define USB2_DIG_REG1 0x40
142#define USB2_DIG_REG2 0x44
143#define USB2_DIG_REG3 0x48
144#define USB2_TEST_REG0 0x4C
145#define USB2_TEST_REG1 0x50
146#define USB2_TEST_REG2 0x54
147#define USB2_CHARGER_REG0 0x58
148#define USB2_OTG_REG0 0x5C
149#define USB2_PHY_MON0 0x60
150#define USB2_RESETVE_REG0 0x64
151#define USB2_ICID_REG0 0x78
152#define USB2_ICID_REG1 0x7C
153
154/* USB2_PLL_REG0 */
155/* This is for Ax stepping */
156#define USB2_PLL_FBDIV_SHIFT_MMP3 0
157#define USB2_PLL_FBDIV_MASK_MMP3 (0xFF << 0)
158
159#define USB2_PLL_REFDIV_SHIFT_MMP3 8
160#define USB2_PLL_REFDIV_MASK_MMP3 (0xF << 8)
161
162#define USB2_PLL_VDD12_SHIFT_MMP3 12
163#define USB2_PLL_VDD18_SHIFT_MMP3 14
164
165/* This is for B0 stepping */
166#define USB2_PLL_FBDIV_SHIFT_MMP3_B0 0
167#define USB2_PLL_REFDIV_SHIFT_MMP3_B0 9
168#define USB2_PLL_VDD18_SHIFT_MMP3_B0 14
169#define USB2_PLL_FBDIV_MASK_MMP3_B0 0x01FF
170#define USB2_PLL_REFDIV_MASK_MMP3_B0 0x3E00
171
172#define USB2_PLL_CAL12_SHIFT_MMP3 0
173#define USB2_PLL_CALI12_MASK_MMP3 (0x3 << 0)
174
175#define USB2_PLL_VCOCAL_START_SHIFT_MMP3 2
176
177#define USB2_PLL_KVCO_SHIFT_MMP3 4
178#define USB2_PLL_KVCO_MASK_MMP3 (0x7<<4)
179
180#define USB2_PLL_ICP_SHIFT_MMP3 8
181#define USB2_PLL_ICP_MASK_MMP3 (0x7<<8)
182
183#define USB2_PLL_LOCK_BYPASS_SHIFT_MMP3 12
184
185#define USB2_PLL_PU_PLL_SHIFT_MMP3 13
186#define USB2_PLL_PU_PLL_MASK (0x1 << 13)
187
188#define USB2_PLL_READY_MASK_MMP3 (0x1 << 15)
189
190/* USB2_TX_REG0 */
191#define USB2_TX_IMPCAL_VTH_SHIFT_MMP3 8
192#define USB2_TX_IMPCAL_VTH_MASK_MMP3 (0x7 << 8)
193
194#define USB2_TX_RCAL_START_SHIFT_MMP3 13
195
196/* USB2_TX_REG1 */
197#define USB2_TX_CK60_PHSEL_SHIFT_MMP3 0
198#define USB2_TX_CK60_PHSEL_MASK_MMP3 (0xf << 0)
199
200#define USB2_TX_AMP_SHIFT_MMP3 4
201#define USB2_TX_AMP_MASK_MMP3 (0x7 << 4)
202
203#define USB2_TX_VDD12_SHIFT_MMP3 8
204#define USB2_TX_VDD12_MASK_MMP3 (0x3 << 8)
205
206/* USB2_TX_REG2 */
207#define USB2_TX_DRV_SLEWRATE_SHIFT 10
208
209/* USB2_RX_REG0 */
210#define USB2_RX_SQ_THRESH_SHIFT_MMP3 4
211#define USB2_RX_SQ_THRESH_MASK_MMP3 (0xf << 4)
212
213#define USB2_RX_SQ_LENGTH_SHIFT_MMP3 10
214#define USB2_RX_SQ_LENGTH_MASK_MMP3 (0x3 << 10)
215
216/* USB2_ANA_REG1*/
217#define USB2_ANA_PU_ANA_SHIFT_MMP3 14
218
219/* USB2_OTG_REG0 */
220#define USB2_OTG_PU_OTG_SHIFT_MMP3 3
221
222/* fsic registers */
223#define FSIC_MISC 0x4
224#define FSIC_INT 0x28
225#define FSIC_CTRL 0x30
226
227/* HSIC registers */
228#define HSIC_PAD_CTRL 0x4
229
230#define HSIC_CTRL 0x8
231#define HSIC_CTRL_HSIC_ENABLE (1<<7)
232#define HSIC_CTRL_PLL_BYPASS (1<<4)
233
234#define TEST_GRP_0 0xc
235#define TEST_GRP_1 0x10
236
237#define HSIC_INT 0x14
238#define HSIC_INT_READY_INT_EN (1<<10)
239#define HSIC_INT_CONNECT_INT_EN (1<<9)
240#define HSIC_INT_CORE_INT_EN (1<<8)
241#define HSIC_INT_HS_READY (1<<2)
242#define HSIC_INT_CONNECT (1<<1)
243#define HSIC_INT_CORE (1<<0)
244
245#define HSIC_CONFIG 0x18
246#define USBHSIC_CTRL 0x20
247
248#define HSIC_USB_CTRL 0x28
249#define HSIC_USB_CTRL_CLKEN 1
250#define HSIC_USB_CLK_PHY 0x0
251#define HSIC_USB_CLK_PMU 0x1
252
253#endif /* __ASM_ARCH_PXA_U2O_H */