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Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +00001/*
2 * Renesas SuperH DMA Engine support
3 *
4 * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
5 * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
6 *
7 * This is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#ifndef __DMA_SHDMA_H
14#define __DMA_SHDMA_H
15
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000016#include <linux/dmaengine.h>
Guennadi Liakhovetski3542a112009-12-17 09:41:39 -070017#include <linux/interrupt.h>
18#include <linux/list.h>
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000019
Magnus Dammd026e002011-05-24 10:31:28 +000020#define SH_DMAC_MAX_CHANNELS 20
Magnus Damm02ca5082010-03-19 04:46:47 +000021#define SH_DMA_SLAVE_NUMBER 256
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000022#define SH_DMA_TCR_MAX 0x00FFFFFF /* 16MB */
23
Guennadi Liakhovetski3542a112009-12-17 09:41:39 -070024struct device;
25
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000026struct sh_dmae_chan {
27 dma_cookie_t completed_cookie; /* The maximum cookie completed */
Guennadi Liakhovetski86d61b32009-12-10 18:35:07 +010028 spinlock_t desc_lock; /* Descriptor operation lock */
29 struct list_head ld_queue; /* Link descriptors queue */
30 struct list_head ld_free; /* Link descriptors free */
31 struct dma_chan common; /* DMA common channel */
32 struct device *dev; /* Channel device */
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000033 struct tasklet_struct tasklet; /* Tasklet */
Guennadi Liakhovetski86d61b32009-12-10 18:35:07 +010034 int descs_allocated; /* desc count */
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +000035 int xmit_shift; /* log_2(bytes_per_xfer) */
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +000036 int irq;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000037 int id; /* Raw id of this channel */
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +000038 u32 __iomem *base;
Guennadi Liakhovetski86d61b32009-12-10 18:35:07 +010039 char dev_id[16]; /* unique name per DMAC of channel */
Guennadi Liakhovetski467017b2011-04-29 17:09:25 +000040 int pm_error;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000041};
42
43struct sh_dmae_device {
44 struct dma_device common;
Guennadi Liakhovetski8b1935e2010-02-11 16:50:14 +000045 struct sh_dmae_chan *chan[SH_DMAC_MAX_CHANNELS];
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +000046 struct sh_dmae_pdata *pdata;
Paul Mundt03aa18f2010-12-17 19:16:10 +090047 struct list_head node;
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +000048 u32 __iomem *chan_reg;
49 u16 __iomem *dmars;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000050};
51
52#define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, common)
53#define to_sh_desc(lh) container_of(lh, struct sh_desc, node)
54#define tx_to_sh_desc(tx) container_of(tx, struct sh_desc, async_tx)
55
56#endif /* __DMA_SHDMA_H */