blob: 9ca4ca70c1bcb8f680fde33b924045eb6666839d [file] [log] [blame]
Shawn Guo2954ff32012-05-04 21:33:42 +08001/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 interrupt-parent = <&icoll>;
16
Shawn Guoce4c6f92012-05-04 14:32:35 +080017 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
Shawn Guoa4508392012-06-28 11:45:00 +080021 serial0 = &auart0;
22 serial1 = &auart1;
Shawn Guoce4c6f92012-05-04 14:32:35 +080023 };
24
Shawn Guo2954ff32012-05-04 21:33:42 +080025 cpus {
26 cpu@0 {
27 compatible = "arm,arm926ejs";
28 };
29 };
30
31 apb@80000000 {
32 compatible = "simple-bus";
33 #address-cells = <1>;
34 #size-cells = <1>;
35 reg = <0x80000000 0x80000>;
36 ranges;
37
38 apbh@80000000 {
39 compatible = "simple-bus";
40 #address-cells = <1>;
41 #size-cells = <1>;
42 reg = <0x80000000 0x40000>;
43 ranges;
44
45 icoll: interrupt-controller@80000000 {
Shawn Guo83a84ef2012-08-20 21:34:56 +080046 compatible = "fsl,imx23-icoll", "fsl,icoll";
Shawn Guo2954ff32012-05-04 21:33:42 +080047 interrupt-controller;
48 #interrupt-cells = <1>;
49 reg = <0x80000000 0x2000>;
50 };
51
52 dma-apbh@80004000 {
Dong Aisheng84f35702012-05-04 20:12:19 +080053 compatible = "fsl,imx23-dma-apbh";
Fabio Estevam640bf062012-07-30 21:29:18 -030054 reg = <0x80004000 0x2000>;
Shawn Guo53f94432012-08-22 21:36:30 +080055 clocks = <&clks 15>;
Shawn Guo2954ff32012-05-04 21:33:42 +080056 };
57
58 ecc@80008000 {
Fabio Estevam640bf062012-07-30 21:29:18 -030059 reg = <0x80008000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +080060 status = "disabled";
61 };
62
Marek Vasuta217c462012-06-09 01:21:55 +020063 gpmi-nand@8000c000 {
Huang Shijieb9f25f82012-07-03 12:58:13 +080064 compatible = "fsl,imx23-gpmi-nand";
65 #address-cells = <1>;
66 #size-cells = <1>;
Fabio Estevam640bf062012-07-30 21:29:18 -030067 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
Huang Shijieb9f25f82012-07-03 12:58:13 +080068 reg-names = "gpmi-nand", "bch";
69 interrupts = <13>, <56>;
70 interrupt-names = "gpmi-dma", "bch";
Shawn Guo53f94432012-08-22 21:36:30 +080071 clocks = <&clks 34>;
Huang Shijieb9f25f82012-07-03 12:58:13 +080072 fsl,gpmi-dma-channel = <4>;
Shawn Guo2954ff32012-05-04 21:33:42 +080073 status = "disabled";
74 };
75
76 ssp0: ssp@80010000 {
Fabio Estevam640bf062012-07-30 21:29:18 -030077 reg = <0x80010000 0x2000>;
Shawn Guobe1ce302012-05-06 16:29:36 +080078 interrupts = <15 14>;
Shawn Guo53f94432012-08-22 21:36:30 +080079 clocks = <&clks 33>;
Shawn Guobe1ce302012-05-06 16:29:36 +080080 fsl,ssp-dma-channel = <1>;
Shawn Guo2954ff32012-05-04 21:33:42 +080081 status = "disabled";
82 };
83
84 etm@80014000 {
Fabio Estevam640bf062012-07-30 21:29:18 -030085 reg = <0x80014000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +080086 status = "disabled";
87 };
88
89 pinctrl@80018000 {
90 #address-cells = <1>;
91 #size-cells = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +080092 compatible = "fsl,imx23-pinctrl", "simple-bus";
Fabio Estevam640bf062012-07-30 21:29:18 -030093 reg = <0x80018000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +080094
Shawn Guoce4c6f92012-05-04 14:32:35 +080095 gpio0: gpio@0 {
96 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
97 interrupts = <16>;
98 gpio-controller;
99 #gpio-cells = <2>;
100 interrupt-controller;
101 #interrupt-cells = <2>;
102 };
103
104 gpio1: gpio@1 {
105 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
106 interrupts = <17>;
107 gpio-controller;
108 #gpio-cells = <2>;
109 interrupt-controller;
110 #interrupt-cells = <2>;
111 };
112
113 gpio2: gpio@2 {
114 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
115 interrupts = <18>;
116 gpio-controller;
117 #gpio-cells = <2>;
118 interrupt-controller;
119 #interrupt-cells = <2>;
120 };
121
Shawn Guo2954ff32012-05-04 21:33:42 +0800122 duart_pins_a: duart@0 {
123 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800124 fsl,pinmux-ids = <
125 0x11a2 /* MX23_PAD_PWM0__DUART_RX */
126 0x11b2 /* MX23_PAD_PWM1__DUART_TX */
127 >;
Shawn Guo2954ff32012-05-04 21:33:42 +0800128 fsl,drive-strength = <0>;
129 fsl,voltage = <1>;
130 fsl,pull-up = <0>;
131 };
Shawn Guobe1ce302012-05-06 16:29:36 +0800132
Shawn Guoa4508392012-06-28 11:45:00 +0800133 auart0_pins_a: auart0@0 {
134 reg = <0>;
135 fsl,pinmux-ids = <
136 0x01c0 /* MX23_PAD_AUART1_RX__AUART1_RX */
137 0x01d0 /* MX23_PAD_AUART1_TX__AUART1_TX */
138 0x01a0 /* MX23_PAD_AUART1_CTS__AUART1_CTS */
139 0x01b0 /* MX23_PAD_AUART1_RTS__AUART1_RTS */
140 >;
141 fsl,drive-strength = <0>;
142 fsl,voltage = <1>;
143 fsl,pull-up = <0>;
144 };
145
Fabio Estevam98916a22012-07-30 16:33:44 -0300146 auart0_2pins_a: auart0-2pins@0 {
147 reg = <0>;
148 fsl,pinmux-ids = <
149 0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */
150 0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */
151 >;
152 fsl,drive-strength = <0>;
153 fsl,voltage = <1>;
154 fsl,pull-up = <0>;
155 };
156
Huang Shijieb9f25f82012-07-03 12:58:13 +0800157 gpmi_pins_a: gpmi-nand@0 {
158 reg = <0>;
159 fsl,pinmux-ids = <
160 0x0000 /* MX23_PAD_GPMI_D00__GPMI_D00 */
161 0x0010 /* MX23_PAD_GPMI_D01__GPMI_D01 */
162 0x0020 /* MX23_PAD_GPMI_D02__GPMI_D02 */
163 0x0030 /* MX23_PAD_GPMI_D03__GPMI_D03 */
164 0x0040 /* MX23_PAD_GPMI_D04__GPMI_D04 */
165 0x0050 /* MX23_PAD_GPMI_D05__GPMI_D05 */
166 0x0060 /* MX23_PAD_GPMI_D06__GPMI_D06 */
167 0x0070 /* MX23_PAD_GPMI_D07__GPMI_D07 */
168 0x0100 /* MX23_PAD_GPMI_CLE__GPMI_CLE */
169 0x0110 /* MX23_PAD_GPMI_ALE__GPMI_ALE */
170 0x0130 /* MX23_PAD_GPMI_RDY0__GPMI_RDY0 */
171 0x0140 /* MX23_PAD_GPMI_RDY1__GPMI_RDY1 */
172 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */
173 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */
174 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */
175 0x21b0 /* MX23_PAD_GPMI_CE1N__GPMI_CE1N */
176 0x21c0 /* MX23_PAD_GPMI_CE0N__GPMI_CE0N */
177 >;
178 fsl,drive-strength = <0>;
179 fsl,voltage = <1>;
180 fsl,pull-up = <0>;
181 };
182
183 gpmi_pins_fixup: gpmi-pins-fixup {
184 fsl,pinmux-ids = <
185 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */
186 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */
187 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */
188 >;
189 fsl,drive-strength = <2>;
190 };
191
Shawn Guo72beaba2012-06-28 11:44:59 +0800192 mmc0_4bit_pins_a: mmc0-4bit@0 {
193 reg = <0>;
194 fsl,pinmux-ids = <
195 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
196 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
197 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
198 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
199 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
Shawn Guo72beaba2012-06-28 11:44:59 +0800200 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
201 >;
202 fsl,drive-strength = <1>;
203 fsl,voltage = <1>;
204 fsl,pull-up = <1>;
205 };
206
Shawn Guobe1ce302012-05-06 16:29:36 +0800207 mmc0_8bit_pins_a: mmc0-8bit@0 {
208 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800209 fsl,pinmux-ids = <
210 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
211 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
212 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
213 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
214 0x0082 /* MX23_PAD_GPMI_D08__SSP1_DATA4 */
215 0x0092 /* MX23_PAD_GPMI_D09__SSP1_DATA5 */
216 0x00a2 /* MX23_PAD_GPMI_D10__SSP1_DATA6 */
217 0x00b2 /* MX23_PAD_GPMI_D11__SSP1_DATA7 */
218 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
219 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
220 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
221 >;
Shawn Guobe1ce302012-05-06 16:29:36 +0800222 fsl,drive-strength = <1>;
223 fsl,voltage = <1>;
224 fsl,pull-up = <1>;
225 };
226
227 mmc0_pins_fixup: mmc0-pins-fixup {
Shawn Guof14da762012-06-28 11:44:57 +0800228 fsl,pinmux-ids = <
229 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
230 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
231 >;
Shawn Guobe1ce302012-05-06 16:29:36 +0800232 fsl,pull-up = <0>;
233 };
Shawn Guo52f71762012-06-28 11:45:06 +0800234
235 pwm2_pins_a: pwm2@0 {
236 reg = <0>;
237 fsl,pinmux-ids = <
238 0x11c0 /* MX23_PAD_PWM2__PWM2 */
239 >;
240 fsl,drive-strength = <0>;
241 fsl,voltage = <1>;
242 fsl,pull-up = <0>;
243 };
Shawn Guoa915ee42012-06-28 11:45:07 +0800244
245 lcdif_24bit_pins_a: lcdif-24bit@0 {
246 reg = <0>;
247 fsl,pinmux-ids = <
248 0x1000 /* MX23_PAD_LCD_D00__LCD_D0 */
249 0x1010 /* MX23_PAD_LCD_D01__LCD_D1 */
250 0x1020 /* MX23_PAD_LCD_D02__LCD_D2 */
251 0x1030 /* MX23_PAD_LCD_D03__LCD_D3 */
252 0x1040 /* MX23_PAD_LCD_D04__LCD_D4 */
253 0x1050 /* MX23_PAD_LCD_D05__LCD_D5 */
254 0x1060 /* MX23_PAD_LCD_D06__LCD_D6 */
255 0x1070 /* MX23_PAD_LCD_D07__LCD_D7 */
256 0x1080 /* MX23_PAD_LCD_D08__LCD_D8 */
257 0x1090 /* MX23_PAD_LCD_D09__LCD_D9 */
258 0x10a0 /* MX23_PAD_LCD_D10__LCD_D10 */
259 0x10b0 /* MX23_PAD_LCD_D11__LCD_D11 */
260 0x10c0 /* MX23_PAD_LCD_D12__LCD_D12 */
261 0x10d0 /* MX23_PAD_LCD_D13__LCD_D13 */
262 0x10e0 /* MX23_PAD_LCD_D14__LCD_D14 */
263 0x10f0 /* MX23_PAD_LCD_D15__LCD_D15 */
264 0x1100 /* MX23_PAD_LCD_D16__LCD_D16 */
265 0x1110 /* MX23_PAD_LCD_D17__LCD_D17 */
266 0x0081 /* MX23_PAD_GPMI_D08__LCD_D18 */
267 0x0091 /* MX23_PAD_GPMI_D09__LCD_D19 */
268 0x00a1 /* MX23_PAD_GPMI_D10__LCD_D20 */
269 0x00b1 /* MX23_PAD_GPMI_D11__LCD_D21 */
270 0x00c1 /* MX23_PAD_GPMI_D12__LCD_D22 */
271 0x00d1 /* MX23_PAD_GPMI_D13__LCD_D23 */
272 0x1160 /* MX23_PAD_LCD_DOTCK__LCD_DOTCK */
273 0x1170 /* MX23_PAD_LCD_ENABLE__LCD_ENABLE */
274 0x1180 /* MX23_PAD_LCD_HSYNC__LCD_HSYNC */
275 0x1190 /* MX23_PAD_LCD_VSYNC__LCD_VSYNC */
276 >;
277 fsl,drive-strength = <0>;
278 fsl,voltage = <1>;
279 fsl,pull-up = <0>;
280 };
Shawn Guo2954ff32012-05-04 21:33:42 +0800281 };
282
283 digctl@8001c000 {
284 reg = <0x8001c000 2000>;
285 status = "disabled";
286 };
287
288 emi@80020000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300289 reg = <0x80020000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800290 status = "disabled";
291 };
292
293 dma-apbx@80024000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800294 compatible = "fsl,imx23-dma-apbx";
Fabio Estevam640bf062012-07-30 21:29:18 -0300295 reg = <0x80024000 0x2000>;
Shawn Guo53f94432012-08-22 21:36:30 +0800296 clocks = <&clks 16>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800297 };
298
299 dcp@80028000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300300 reg = <0x80028000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800301 status = "disabled";
302 };
303
304 pxp@8002a000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300305 reg = <0x8002a000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800306 status = "disabled";
307 };
308
309 ocotp@8002c000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300310 reg = <0x8002c000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800311 status = "disabled";
312 };
313
314 axi-ahb@8002e000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300315 reg = <0x8002e000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800316 status = "disabled";
317 };
318
319 lcdif@80030000 {
Shawn Guoa915ee42012-06-28 11:45:07 +0800320 compatible = "fsl,imx23-lcdif";
Shawn Guo2954ff32012-05-04 21:33:42 +0800321 reg = <0x80030000 2000>;
Shawn Guoa915ee42012-06-28 11:45:07 +0800322 interrupts = <46 45>;
Shawn Guo53f94432012-08-22 21:36:30 +0800323 clocks = <&clks 38>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800324 status = "disabled";
325 };
326
327 ssp1: ssp@80034000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300328 reg = <0x80034000 0x2000>;
Shawn Guobe1ce302012-05-06 16:29:36 +0800329 interrupts = <2 20>;
Shawn Guo53f94432012-08-22 21:36:30 +0800330 clocks = <&clks 33>;
Shawn Guobe1ce302012-05-06 16:29:36 +0800331 fsl,ssp-dma-channel = <2>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800332 status = "disabled";
333 };
334
335 tvenc@80038000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300336 reg = <0x80038000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800337 status = "disabled";
338 };
339 };
340
341 apbx@80040000 {
342 compatible = "simple-bus";
343 #address-cells = <1>;
344 #size-cells = <1>;
345 reg = <0x80040000 0x40000>;
346 ranges;
347
Shawn Guo53f94432012-08-22 21:36:30 +0800348 clks: clkctrl@80040000 {
349 compatible = "fsl,imx23-clkctrl";
Fabio Estevam640bf062012-07-30 21:29:18 -0300350 reg = <0x80040000 0x2000>;
Shawn Guo53f94432012-08-22 21:36:30 +0800351 #clock-cells = <1>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800352 };
353
354 saif0: saif@80042000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300355 reg = <0x80042000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800356 status = "disabled";
357 };
358
359 power@80044000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300360 reg = <0x80044000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800361 status = "disabled";
362 };
363
364 saif1: saif@80046000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300365 reg = <0x80046000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800366 status = "disabled";
367 };
368
369 audio-out@80048000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300370 reg = <0x80048000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800371 status = "disabled";
372 };
373
374 audio-in@8004c000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300375 reg = <0x8004c000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800376 status = "disabled";
377 };
378
379 lradc@80050000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300380 reg = <0x80050000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800381 status = "disabled";
382 };
383
384 spdif@80054000 {
385 reg = <0x80054000 2000>;
386 status = "disabled";
387 };
388
389 i2c@80058000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300390 reg = <0x80058000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800391 status = "disabled";
392 };
393
394 rtc@8005c000 {
Shawn Guof98c9902012-06-28 11:45:05 +0800395 compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
Fabio Estevam640bf062012-07-30 21:29:18 -0300396 reg = <0x8005c000 0x2000>;
Shawn Guof98c9902012-06-28 11:45:05 +0800397 interrupts = <22>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800398 };
399
Shawn Guo52f71762012-06-28 11:45:06 +0800400 pwm: pwm@80064000 {
401 compatible = "fsl,imx23-pwm";
Fabio Estevam640bf062012-07-30 21:29:18 -0300402 reg = <0x80064000 0x2000>;
Shawn Guo53f94432012-08-22 21:36:30 +0800403 clocks = <&clks 30>;
Shawn Guo52f71762012-06-28 11:45:06 +0800404 #pwm-cells = <2>;
405 fsl,pwm-number = <5>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800406 status = "disabled";
407 };
408
409 timrot@80068000 {
Shawn Guoeeca6e62012-08-20 08:51:45 +0800410 compatible = "fsl,imx23-timrot", "fsl,timrot";
Fabio Estevam640bf062012-07-30 21:29:18 -0300411 reg = <0x80068000 0x2000>;
Shawn Guoeeca6e62012-08-20 08:51:45 +0800412 interrupts = <28 29 30 31>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800413 };
414
415 auart0: serial@8006c000 {
Shawn Guoa4508392012-06-28 11:45:00 +0800416 compatible = "fsl,imx23-auart";
Shawn Guo2954ff32012-05-04 21:33:42 +0800417 reg = <0x8006c000 0x2000>;
Shawn Guoa4508392012-06-28 11:45:00 +0800418 interrupts = <24 25 23>;
Shawn Guo53f94432012-08-22 21:36:30 +0800419 clocks = <&clks 32>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800420 status = "disabled";
421 };
422
423 auart1: serial@8006e000 {
Shawn Guoa4508392012-06-28 11:45:00 +0800424 compatible = "fsl,imx23-auart";
Shawn Guo2954ff32012-05-04 21:33:42 +0800425 reg = <0x8006e000 0x2000>;
Shawn Guoa4508392012-06-28 11:45:00 +0800426 interrupts = <59 60 58>;
Shawn Guo53f94432012-08-22 21:36:30 +0800427 clocks = <&clks 32>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800428 status = "disabled";
429 };
430
431 duart: serial@80070000 {
432 compatible = "arm,pl011", "arm,primecell";
433 reg = <0x80070000 0x2000>;
434 interrupts = <0>;
Shawn Guo53f94432012-08-22 21:36:30 +0800435 clocks = <&clks 32>, <&clks 16>;
436 clock-names = "uart", "apb_pclk";
Shawn Guo2954ff32012-05-04 21:33:42 +0800437 status = "disabled";
438 };
439
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300440 usbphy0: usbphy@8007c000 {
441 compatible = "fsl,imx23-usbphy";
Shawn Guo2954ff32012-05-04 21:33:42 +0800442 reg = <0x8007c000 0x2000>;
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300443 clocks = <&clks 41>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800444 status = "disabled";
445 };
446 };
447 };
448
449 ahb@80080000 {
450 compatible = "simple-bus";
451 #address-cells = <1>;
452 #size-cells = <1>;
453 reg = <0x80080000 0x80000>;
454 ranges;
455
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300456 usb0: usb@80080000 {
457 compatible = "fsl,imx23-usb", "fsl,imx27-usb";
Fabio Estevam640bf062012-07-30 21:29:18 -0300458 reg = <0x80080000 0x40000>;
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300459 interrupts = <11>;
460 fsl,usbphy = <&usbphy0>;
461 clocks = <&clks 40>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800462 status = "disabled";
463 };
464 };
465};