Paul Burton | 9f98f3d | 2014-01-15 10:31:51 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Imagination Technologies |
| 3 | * Author: Paul Burton <paul.burton@imgtec.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License as published by the |
| 7 | * Free Software Foundation; either version 2 of the License, or (at your |
| 8 | * option) any later version. |
| 9 | */ |
| 10 | |
| 11 | #ifndef __MIPS_ASM_MIPS_CM_H__ |
| 12 | #define __MIPS_ASM_MIPS_CM_H__ |
| 13 | |
Paul Burton | 47b26a4 | 2015-09-22 10:26:41 -0700 | [diff] [blame] | 14 | #include <linux/bitops.h> |
Paul Burton | 56d4c99 | 2015-05-22 16:51:01 +0100 | [diff] [blame] | 15 | #include <linux/errno.h> |
Paul Burton | 9f98f3d | 2014-01-15 10:31:51 +0000 | [diff] [blame] | 16 | #include <linux/io.h> |
| 17 | #include <linux/types.h> |
| 18 | |
| 19 | /* The base address of the CM GCR block */ |
| 20 | extern void __iomem *mips_cm_base; |
| 21 | |
| 22 | /* The base address of the CM L2-only sync region */ |
| 23 | extern void __iomem *mips_cm_l2sync_base; |
| 24 | |
| 25 | /** |
| 26 | * __mips_cm_phys_base - retrieve the physical base address of the CM |
| 27 | * |
| 28 | * This function returns the physical base address of the Coherence Manager |
| 29 | * global control block, or 0 if no Coherence Manager is present. It provides |
| 30 | * a default implementation which reads the CMGCRBase register where available, |
Adam Buchbinder | 92a76f6 | 2016-02-25 00:44:58 -0800 | [diff] [blame] | 31 | * and may be overridden by platforms which determine this address in a |
Paul Burton | 9f98f3d | 2014-01-15 10:31:51 +0000 | [diff] [blame] | 32 | * different way by defining a function with the same prototype except for the |
| 33 | * name mips_cm_phys_base (without underscores). |
| 34 | */ |
Ralf Baechle | 15d45cc | 2014-11-22 00:22:09 +0100 | [diff] [blame] | 35 | extern phys_addr_t __mips_cm_phys_base(void); |
Paul Burton | 9f98f3d | 2014-01-15 10:31:51 +0000 | [diff] [blame] | 36 | |
Markos Chandras | c0b584a | 2015-07-14 09:14:12 +0100 | [diff] [blame] | 37 | /* |
| 38 | * mips_cm_is64 - determine CM register width |
| 39 | * |
Paul Burton | 7784494 | 2015-09-22 10:26:37 -0700 | [diff] [blame] | 40 | * The CM register width is determined by the version of the CM, with CM3 |
| 41 | * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs. |
| 42 | * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs, |
| 43 | * or vice-versa. This variable indicates the width of the memory accesses |
| 44 | * that the kernel will perform to GCRs, which may differ from the actual |
| 45 | * width of the GCRs. |
Markos Chandras | c0b584a | 2015-07-14 09:14:12 +0100 | [diff] [blame] | 46 | * |
| 47 | * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses. |
| 48 | */ |
| 49 | extern int mips_cm_is64; |
| 50 | |
Paul Burton | 9f98f3d | 2014-01-15 10:31:51 +0000 | [diff] [blame] | 51 | /** |
Markos Chandras | 3885c2b | 2015-07-09 10:40:47 +0100 | [diff] [blame] | 52 | * mips_cm_error_report - Report CM cache errors |
| 53 | */ |
| 54 | #ifdef CONFIG_MIPS_CM |
| 55 | extern void mips_cm_error_report(void); |
| 56 | #else |
| 57 | static inline void mips_cm_error_report(void) {} |
| 58 | #endif |
| 59 | |
| 60 | /** |
Paul Burton | 9f98f3d | 2014-01-15 10:31:51 +0000 | [diff] [blame] | 61 | * mips_cm_probe - probe for a Coherence Manager |
| 62 | * |
| 63 | * Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM |
| 64 | * is successfully detected, else -errno. |
| 65 | */ |
| 66 | #ifdef CONFIG_MIPS_CM |
| 67 | extern int mips_cm_probe(void); |
| 68 | #else |
| 69 | static inline int mips_cm_probe(void) |
| 70 | { |
| 71 | return -ENODEV; |
| 72 | } |
| 73 | #endif |
| 74 | |
| 75 | /** |
| 76 | * mips_cm_present - determine whether a Coherence Manager is present |
| 77 | * |
| 78 | * Returns true if a CM is present in the system, else false. |
| 79 | */ |
| 80 | static inline bool mips_cm_present(void) |
| 81 | { |
| 82 | #ifdef CONFIG_MIPS_CM |
| 83 | return mips_cm_base != NULL; |
| 84 | #else |
| 85 | return false; |
| 86 | #endif |
| 87 | } |
| 88 | |
| 89 | /** |
| 90 | * mips_cm_has_l2sync - determine whether an L2-only sync region is present |
| 91 | * |
| 92 | * Returns true if the system implements an L2-only sync region, else false. |
| 93 | */ |
| 94 | static inline bool mips_cm_has_l2sync(void) |
| 95 | { |
| 96 | #ifdef CONFIG_MIPS_CM |
| 97 | return mips_cm_l2sync_base != NULL; |
| 98 | #else |
| 99 | return false; |
| 100 | #endif |
| 101 | } |
| 102 | |
| 103 | /* Offsets to register blocks from the CM base address */ |
| 104 | #define MIPS_CM_GCB_OFS 0x0000 /* Global Control Block */ |
| 105 | #define MIPS_CM_CLCB_OFS 0x2000 /* Core Local Control Block */ |
| 106 | #define MIPS_CM_COCB_OFS 0x4000 /* Core Other Control Block */ |
| 107 | #define MIPS_CM_GDB_OFS 0x6000 /* Global Debug Block */ |
| 108 | |
| 109 | /* Total size of the CM memory mapped registers */ |
| 110 | #define MIPS_CM_GCR_SIZE 0x8000 |
| 111 | |
| 112 | /* Size of the L2-only sync region */ |
| 113 | #define MIPS_CM_L2SYNC_SIZE 0x1000 |
| 114 | |
| 115 | /* Macros to ease the creation of register access functions */ |
| 116 | #define BUILD_CM_R_(name, off) \ |
Markos Chandras | c0b584a | 2015-07-14 09:14:12 +0100 | [diff] [blame] | 117 | static inline unsigned long __iomem *addr_gcr_##name(void) \ |
Paul Burton | 9f98f3d | 2014-01-15 10:31:51 +0000 | [diff] [blame] | 118 | { \ |
Markos Chandras | c0b584a | 2015-07-14 09:14:12 +0100 | [diff] [blame] | 119 | return (unsigned long __iomem *)(mips_cm_base + (off)); \ |
Paul Burton | 9f98f3d | 2014-01-15 10:31:51 +0000 | [diff] [blame] | 120 | } \ |
| 121 | \ |
Markos Chandras | c0b584a | 2015-07-14 09:14:12 +0100 | [diff] [blame] | 122 | static inline u32 read32_gcr_##name(void) \ |
Paul Burton | 9f98f3d | 2014-01-15 10:31:51 +0000 | [diff] [blame] | 123 | { \ |
Paul Burton | cd21754 | 2014-03-24 10:19:34 +0000 | [diff] [blame] | 124 | return __raw_readl(addr_gcr_##name()); \ |
Markos Chandras | c0b584a | 2015-07-14 09:14:12 +0100 | [diff] [blame] | 125 | } \ |
| 126 | \ |
| 127 | static inline u64 read64_gcr_##name(void) \ |
| 128 | { \ |
Paul Burton | b657a62 | 2015-09-22 10:26:40 -0700 | [diff] [blame] | 129 | void __iomem *addr = addr_gcr_##name(); \ |
| 130 | u64 ret; \ |
| 131 | \ |
| 132 | if (mips_cm_is64) { \ |
| 133 | ret = __raw_readq(addr); \ |
| 134 | } else { \ |
| 135 | ret = __raw_readl(addr); \ |
| 136 | ret |= (u64)__raw_readl(addr + 0x4) << 32; \ |
| 137 | } \ |
| 138 | \ |
| 139 | return ret; \ |
Markos Chandras | c0b584a | 2015-07-14 09:14:12 +0100 | [diff] [blame] | 140 | } \ |
| 141 | \ |
| 142 | static inline unsigned long read_gcr_##name(void) \ |
| 143 | { \ |
| 144 | if (mips_cm_is64) \ |
| 145 | return read64_gcr_##name(); \ |
| 146 | else \ |
| 147 | return read32_gcr_##name(); \ |
Paul Burton | 9f98f3d | 2014-01-15 10:31:51 +0000 | [diff] [blame] | 148 | } |
| 149 | |
| 150 | #define BUILD_CM__W(name, off) \ |
Markos Chandras | c0b584a | 2015-07-14 09:14:12 +0100 | [diff] [blame] | 151 | static inline void write32_gcr_##name(u32 value) \ |
Paul Burton | 9f98f3d | 2014-01-15 10:31:51 +0000 | [diff] [blame] | 152 | { \ |
Paul Burton | cd21754 | 2014-03-24 10:19:34 +0000 | [diff] [blame] | 153 | __raw_writel(value, addr_gcr_##name()); \ |
Markos Chandras | c0b584a | 2015-07-14 09:14:12 +0100 | [diff] [blame] | 154 | } \ |
| 155 | \ |
| 156 | static inline void write64_gcr_##name(u64 value) \ |
| 157 | { \ |
| 158 | __raw_writeq(value, addr_gcr_##name()); \ |
| 159 | } \ |
| 160 | \ |
| 161 | static inline void write_gcr_##name(unsigned long value) \ |
| 162 | { \ |
| 163 | if (mips_cm_is64) \ |
| 164 | write64_gcr_##name(value); \ |
| 165 | else \ |
| 166 | write32_gcr_##name(value); \ |
Paul Burton | 9f98f3d | 2014-01-15 10:31:51 +0000 | [diff] [blame] | 167 | } |
| 168 | |
| 169 | #define BUILD_CM_RW(name, off) \ |
| 170 | BUILD_CM_R_(name, off) \ |
| 171 | BUILD_CM__W(name, off) |
| 172 | |
| 173 | #define BUILD_CM_Cx_R_(name, off) \ |
| 174 | BUILD_CM_R_(cl_##name, MIPS_CM_CLCB_OFS + (off)) \ |
| 175 | BUILD_CM_R_(co_##name, MIPS_CM_COCB_OFS + (off)) |
| 176 | |
| 177 | #define BUILD_CM_Cx__W(name, off) \ |
| 178 | BUILD_CM__W(cl_##name, MIPS_CM_CLCB_OFS + (off)) \ |
| 179 | BUILD_CM__W(co_##name, MIPS_CM_COCB_OFS + (off)) |
| 180 | |
| 181 | #define BUILD_CM_Cx_RW(name, off) \ |
| 182 | BUILD_CM_Cx_R_(name, off) \ |
| 183 | BUILD_CM_Cx__W(name, off) |
| 184 | |
| 185 | /* GCB register accessor functions */ |
| 186 | BUILD_CM_R_(config, MIPS_CM_GCB_OFS + 0x00) |
| 187 | BUILD_CM_RW(base, MIPS_CM_GCB_OFS + 0x08) |
| 188 | BUILD_CM_RW(access, MIPS_CM_GCB_OFS + 0x20) |
| 189 | BUILD_CM_R_(rev, MIPS_CM_GCB_OFS + 0x30) |
| 190 | BUILD_CM_RW(error_mask, MIPS_CM_GCB_OFS + 0x40) |
| 191 | BUILD_CM_RW(error_cause, MIPS_CM_GCB_OFS + 0x48) |
| 192 | BUILD_CM_RW(error_addr, MIPS_CM_GCB_OFS + 0x50) |
| 193 | BUILD_CM_RW(error_mult, MIPS_CM_GCB_OFS + 0x58) |
| 194 | BUILD_CM_RW(l2_only_sync_base, MIPS_CM_GCB_OFS + 0x70) |
| 195 | BUILD_CM_RW(gic_base, MIPS_CM_GCB_OFS + 0x80) |
| 196 | BUILD_CM_RW(cpc_base, MIPS_CM_GCB_OFS + 0x88) |
| 197 | BUILD_CM_RW(reg0_base, MIPS_CM_GCB_OFS + 0x90) |
| 198 | BUILD_CM_RW(reg0_mask, MIPS_CM_GCB_OFS + 0x98) |
| 199 | BUILD_CM_RW(reg1_base, MIPS_CM_GCB_OFS + 0xa0) |
| 200 | BUILD_CM_RW(reg1_mask, MIPS_CM_GCB_OFS + 0xa8) |
| 201 | BUILD_CM_RW(reg2_base, MIPS_CM_GCB_OFS + 0xb0) |
| 202 | BUILD_CM_RW(reg2_mask, MIPS_CM_GCB_OFS + 0xb8) |
| 203 | BUILD_CM_RW(reg3_base, MIPS_CM_GCB_OFS + 0xc0) |
| 204 | BUILD_CM_RW(reg3_mask, MIPS_CM_GCB_OFS + 0xc8) |
| 205 | BUILD_CM_R_(gic_status, MIPS_CM_GCB_OFS + 0xd0) |
| 206 | BUILD_CM_R_(cpc_status, MIPS_CM_GCB_OFS + 0xf0) |
Paul Burton | 0ba3c12 | 2015-07-09 10:40:40 +0100 | [diff] [blame] | 207 | BUILD_CM_RW(l2_config, MIPS_CM_GCB_OFS + 0x130) |
Paul Burton | 7573b94 | 2015-09-22 11:29:09 -0700 | [diff] [blame] | 208 | BUILD_CM_RW(sys_config2, MIPS_CM_GCB_OFS + 0x150) |
Paul Burton | 4d03551 | 2015-09-22 10:10:54 -0700 | [diff] [blame] | 209 | BUILD_CM_RW(l2_pft_control, MIPS_CM_GCB_OFS + 0x300) |
| 210 | BUILD_CM_RW(l2_pft_control_b, MIPS_CM_GCB_OFS + 0x308) |
Paul Burton | 9f98f3d | 2014-01-15 10:31:51 +0000 | [diff] [blame] | 211 | |
| 212 | /* Core Local & Core Other register accessor functions */ |
| 213 | BUILD_CM_Cx_RW(reset_release, 0x00) |
| 214 | BUILD_CM_Cx_RW(coherence, 0x08) |
| 215 | BUILD_CM_Cx_R_(config, 0x10) |
| 216 | BUILD_CM_Cx_RW(other, 0x18) |
| 217 | BUILD_CM_Cx_RW(reset_base, 0x20) |
| 218 | BUILD_CM_Cx_R_(id, 0x28) |
| 219 | BUILD_CM_Cx_RW(reset_ext_base, 0x30) |
| 220 | BUILD_CM_Cx_R_(tcid_0_priority, 0x40) |
| 221 | BUILD_CM_Cx_R_(tcid_1_priority, 0x48) |
| 222 | BUILD_CM_Cx_R_(tcid_2_priority, 0x50) |
| 223 | BUILD_CM_Cx_R_(tcid_3_priority, 0x58) |
| 224 | BUILD_CM_Cx_R_(tcid_4_priority, 0x60) |
| 225 | BUILD_CM_Cx_R_(tcid_5_priority, 0x68) |
| 226 | BUILD_CM_Cx_R_(tcid_6_priority, 0x70) |
| 227 | BUILD_CM_Cx_R_(tcid_7_priority, 0x78) |
| 228 | BUILD_CM_Cx_R_(tcid_8_priority, 0x80) |
| 229 | |
| 230 | /* GCR_CONFIG register fields */ |
| 231 | #define CM_GCR_CONFIG_NUMIOCU_SHF 8 |
| 232 | #define CM_GCR_CONFIG_NUMIOCU_MSK (_ULCAST_(0xf) << 8) |
| 233 | #define CM_GCR_CONFIG_PCORES_SHF 0 |
| 234 | #define CM_GCR_CONFIG_PCORES_MSK (_ULCAST_(0xff) << 0) |
| 235 | |
| 236 | /* GCR_BASE register fields */ |
| 237 | #define CM_GCR_BASE_GCRBASE_SHF 15 |
| 238 | #define CM_GCR_BASE_GCRBASE_MSK (_ULCAST_(0x1ffff) << 15) |
| 239 | #define CM_GCR_BASE_CMDEFTGT_SHF 0 |
| 240 | #define CM_GCR_BASE_CMDEFTGT_MSK (_ULCAST_(0x3) << 0) |
| 241 | #define CM_GCR_BASE_CMDEFTGT_DISABLED 0 |
| 242 | #define CM_GCR_BASE_CMDEFTGT_MEM 1 |
| 243 | #define CM_GCR_BASE_CMDEFTGT_IOCU0 2 |
| 244 | #define CM_GCR_BASE_CMDEFTGT_IOCU1 3 |
| 245 | |
Matt Redfearn | 497e803e | 2015-12-18 12:47:00 +0000 | [diff] [blame] | 246 | /* GCR_RESET_EXT_BASE register fields */ |
| 247 | #define CM_GCR_RESET_EXT_BASE_EVARESET BIT(31) |
| 248 | #define CM_GCR_RESET_EXT_BASE_UEB BIT(30) |
| 249 | |
Paul Burton | 9f98f3d | 2014-01-15 10:31:51 +0000 | [diff] [blame] | 250 | /* GCR_ACCESS register fields */ |
| 251 | #define CM_GCR_ACCESS_ACCESSEN_SHF 0 |
| 252 | #define CM_GCR_ACCESS_ACCESSEN_MSK (_ULCAST_(0xff) << 0) |
| 253 | |
| 254 | /* GCR_REV register fields */ |
| 255 | #define CM_GCR_REV_MAJOR_SHF 8 |
| 256 | #define CM_GCR_REV_MAJOR_MSK (_ULCAST_(0xff) << 8) |
| 257 | #define CM_GCR_REV_MINOR_SHF 0 |
| 258 | #define CM_GCR_REV_MINOR_MSK (_ULCAST_(0xff) << 0) |
| 259 | |
Paul Burton | 197e89e | 2015-07-10 10:12:52 +0100 | [diff] [blame] | 260 | #define CM_ENCODE_REV(major, minor) \ |
| 261 | (((major) << CM_GCR_REV_MAJOR_SHF) | \ |
| 262 | ((minor) << CM_GCR_REV_MINOR_SHF)) |
| 263 | |
| 264 | #define CM_REV_CM2 CM_ENCODE_REV(6, 0) |
Paul Burton | 4d03551 | 2015-09-22 10:10:54 -0700 | [diff] [blame] | 265 | #define CM_REV_CM2_5 CM_ENCODE_REV(7, 0) |
Paul Burton | 197e89e | 2015-07-10 10:12:52 +0100 | [diff] [blame] | 266 | #define CM_REV_CM3 CM_ENCODE_REV(8, 0) |
| 267 | |
Paul Burton | 9f98f3d | 2014-01-15 10:31:51 +0000 | [diff] [blame] | 268 | /* GCR_ERROR_CAUSE register fields */ |
| 269 | #define CM_GCR_ERROR_CAUSE_ERRTYPE_SHF 27 |
| 270 | #define CM_GCR_ERROR_CAUSE_ERRTYPE_MSK (_ULCAST_(0x1f) << 27) |
Paul Burton | 47b26a4 | 2015-09-22 10:26:41 -0700 | [diff] [blame] | 271 | #define CM3_GCR_ERROR_CAUSE_ERRTYPE_SHF 58 |
| 272 | #define CM3_GCR_ERROR_CAUSE_ERRTYPE_MSK GENMASK_ULL(63, 58) |
Paul Burton | 9f98f3d | 2014-01-15 10:31:51 +0000 | [diff] [blame] | 273 | #define CM_GCR_ERROR_CAUSE_ERRINFO_SHF 0 |
| 274 | #define CM_GCR_ERROR_CAUSE_ERRINGO_MSK (_ULCAST_(0x7ffffff) << 0) |
| 275 | |
| 276 | /* GCR_ERROR_MULT register fields */ |
| 277 | #define CM_GCR_ERROR_MULT_ERR2ND_SHF 0 |
| 278 | #define CM_GCR_ERROR_MULT_ERR2ND_MSK (_ULCAST_(0x1f) << 0) |
| 279 | |
| 280 | /* GCR_L2_ONLY_SYNC_BASE register fields */ |
| 281 | #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_SHF 12 |
| 282 | #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK (_ULCAST_(0xfffff) << 12) |
| 283 | #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_SHF 0 |
| 284 | #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK (_ULCAST_(0x1) << 0) |
| 285 | |
| 286 | /* GCR_GIC_BASE register fields */ |
| 287 | #define CM_GCR_GIC_BASE_GICBASE_SHF 17 |
| 288 | #define CM_GCR_GIC_BASE_GICBASE_MSK (_ULCAST_(0x7fff) << 17) |
| 289 | #define CM_GCR_GIC_BASE_GICEN_SHF 0 |
| 290 | #define CM_GCR_GIC_BASE_GICEN_MSK (_ULCAST_(0x1) << 0) |
| 291 | |
| 292 | /* GCR_CPC_BASE register fields */ |
| 293 | #define CM_GCR_CPC_BASE_CPCBASE_SHF 17 |
| 294 | #define CM_GCR_CPC_BASE_CPCBASE_MSK (_ULCAST_(0x7fff) << 17) |
| 295 | #define CM_GCR_CPC_BASE_CPCEN_SHF 0 |
| 296 | #define CM_GCR_CPC_BASE_CPCEN_MSK (_ULCAST_(0x1) << 0) |
| 297 | |
Paul Burton | 921d55e | 2015-05-22 16:51:00 +0100 | [diff] [blame] | 298 | /* GCR_GIC_STATUS register fields */ |
| 299 | #define CM_GCR_GIC_STATUS_GICEX_SHF 0 |
| 300 | #define CM_GCR_GIC_STATUS_GICEX_MSK (_ULCAST_(0x1) << 0) |
| 301 | |
Paul Burton | 9f98f3d | 2014-01-15 10:31:51 +0000 | [diff] [blame] | 302 | /* GCR_REGn_BASE register fields */ |
| 303 | #define CM_GCR_REGn_BASE_BASEADDR_SHF 16 |
| 304 | #define CM_GCR_REGn_BASE_BASEADDR_MSK (_ULCAST_(0xffff) << 16) |
| 305 | |
| 306 | /* GCR_REGn_MASK register fields */ |
| 307 | #define CM_GCR_REGn_MASK_ADDRMASK_SHF 16 |
| 308 | #define CM_GCR_REGn_MASK_ADDRMASK_MSK (_ULCAST_(0xffff) << 16) |
| 309 | #define CM_GCR_REGn_MASK_CCAOVR_SHF 5 |
| 310 | #define CM_GCR_REGn_MASK_CCAOVR_MSK (_ULCAST_(0x3) << 5) |
| 311 | #define CM_GCR_REGn_MASK_CCAOVREN_SHF 4 |
| 312 | #define CM_GCR_REGn_MASK_CCAOVREN_MSK (_ULCAST_(0x1) << 4) |
| 313 | #define CM_GCR_REGn_MASK_DROPL2_SHF 2 |
| 314 | #define CM_GCR_REGn_MASK_DROPL2_MSK (_ULCAST_(0x1) << 2) |
| 315 | #define CM_GCR_REGn_MASK_CMTGT_SHF 0 |
| 316 | #define CM_GCR_REGn_MASK_CMTGT_MSK (_ULCAST_(0x3) << 0) |
| 317 | #define CM_GCR_REGn_MASK_CMTGT_DISABLED (_ULCAST_(0x0) << 0) |
| 318 | #define CM_GCR_REGn_MASK_CMTGT_MEM (_ULCAST_(0x1) << 0) |
| 319 | #define CM_GCR_REGn_MASK_CMTGT_IOCU0 (_ULCAST_(0x2) << 0) |
| 320 | #define CM_GCR_REGn_MASK_CMTGT_IOCU1 (_ULCAST_(0x3) << 0) |
| 321 | |
| 322 | /* GCR_GIC_STATUS register fields */ |
| 323 | #define CM_GCR_GIC_STATUS_EX_SHF 0 |
| 324 | #define CM_GCR_GIC_STATUS_EX_MSK (_ULCAST_(0x1) << 0) |
| 325 | |
| 326 | /* GCR_CPC_STATUS register fields */ |
| 327 | #define CM_GCR_CPC_STATUS_EX_SHF 0 |
| 328 | #define CM_GCR_CPC_STATUS_EX_MSK (_ULCAST_(0x1) << 0) |
| 329 | |
Paul Burton | 0ba3c12 | 2015-07-09 10:40:40 +0100 | [diff] [blame] | 330 | /* GCR_L2_CONFIG register fields */ |
| 331 | #define CM_GCR_L2_CONFIG_BYPASS_SHF 20 |
| 332 | #define CM_GCR_L2_CONFIG_BYPASS_MSK (_ULCAST_(0x1) << 20) |
| 333 | #define CM_GCR_L2_CONFIG_SET_SIZE_SHF 12 |
| 334 | #define CM_GCR_L2_CONFIG_SET_SIZE_MSK (_ULCAST_(0xf) << 12) |
| 335 | #define CM_GCR_L2_CONFIG_LINE_SIZE_SHF 8 |
| 336 | #define CM_GCR_L2_CONFIG_LINE_SIZE_MSK (_ULCAST_(0xf) << 8) |
| 337 | #define CM_GCR_L2_CONFIG_ASSOC_SHF 0 |
| 338 | #define CM_GCR_L2_CONFIG_ASSOC_MSK (_ULCAST_(0xff) << 0) |
| 339 | |
Paul Burton | 7573b94 | 2015-09-22 11:29:09 -0700 | [diff] [blame] | 340 | /* GCR_SYS_CONFIG2 register fields */ |
| 341 | #define CM_GCR_SYS_CONFIG2_MAXVPW_SHF 0 |
| 342 | #define CM_GCR_SYS_CONFIG2_MAXVPW_MSK (_ULCAST_(0xf) << 0) |
| 343 | |
Paul Burton | 4d03551 | 2015-09-22 10:10:54 -0700 | [diff] [blame] | 344 | /* GCR_L2_PFT_CONTROL register fields */ |
| 345 | #define CM_GCR_L2_PFT_CONTROL_PAGEMASK_SHF 12 |
| 346 | #define CM_GCR_L2_PFT_CONTROL_PAGEMASK_MSK (_ULCAST_(0xfffff) << 12) |
| 347 | #define CM_GCR_L2_PFT_CONTROL_PFTEN_SHF 8 |
| 348 | #define CM_GCR_L2_PFT_CONTROL_PFTEN_MSK (_ULCAST_(0x1) << 8) |
| 349 | #define CM_GCR_L2_PFT_CONTROL_NPFT_SHF 0 |
| 350 | #define CM_GCR_L2_PFT_CONTROL_NPFT_MSK (_ULCAST_(0xff) << 0) |
| 351 | |
| 352 | /* GCR_L2_PFT_CONTROL_B register fields */ |
| 353 | #define CM_GCR_L2_PFT_CONTROL_B_CEN_SHF 8 |
| 354 | #define CM_GCR_L2_PFT_CONTROL_B_CEN_MSK (_ULCAST_(0x1) << 8) |
| 355 | #define CM_GCR_L2_PFT_CONTROL_B_PORTID_SHF 0 |
| 356 | #define CM_GCR_L2_PFT_CONTROL_B_PORTID_MSK (_ULCAST_(0xff) << 0) |
| 357 | |
Paul Burton | 9f98f3d | 2014-01-15 10:31:51 +0000 | [diff] [blame] | 358 | /* GCR_Cx_COHERENCE register fields */ |
| 359 | #define CM_GCR_Cx_COHERENCE_COHDOMAINEN_SHF 0 |
| 360 | #define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK (_ULCAST_(0xff) << 0) |
| 361 | |
| 362 | /* GCR_Cx_CONFIG register fields */ |
| 363 | #define CM_GCR_Cx_CONFIG_IOCUTYPE_SHF 10 |
| 364 | #define CM_GCR_Cx_CONFIG_IOCUTYPE_MSK (_ULCAST_(0x3) << 10) |
| 365 | #define CM_GCR_Cx_CONFIG_PVPE_SHF 0 |
Paul Burton | 252d6aa | 2015-09-22 11:12:15 -0700 | [diff] [blame] | 366 | #define CM_GCR_Cx_CONFIG_PVPE_MSK (_ULCAST_(0x3ff) << 0) |
Paul Burton | 9f98f3d | 2014-01-15 10:31:51 +0000 | [diff] [blame] | 367 | |
| 368 | /* GCR_Cx_OTHER register fields */ |
| 369 | #define CM_GCR_Cx_OTHER_CORENUM_SHF 16 |
| 370 | #define CM_GCR_Cx_OTHER_CORENUM_MSK (_ULCAST_(0xffff) << 16) |
Paul Burton | 23d5de8 | 2015-09-22 11:12:16 -0700 | [diff] [blame] | 371 | #define CM3_GCR_Cx_OTHER_CORE_SHF 8 |
| 372 | #define CM3_GCR_Cx_OTHER_CORE_MSK (_ULCAST_(0x3f) << 8) |
| 373 | #define CM3_GCR_Cx_OTHER_VP_SHF 0 |
| 374 | #define CM3_GCR_Cx_OTHER_VP_MSK (_ULCAST_(0x7) << 0) |
Paul Burton | 9f98f3d | 2014-01-15 10:31:51 +0000 | [diff] [blame] | 375 | |
| 376 | /* GCR_Cx_RESET_BASE register fields */ |
| 377 | #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_SHF 12 |
| 378 | #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_MSK (_ULCAST_(0xfffff) << 12) |
| 379 | |
| 380 | /* GCR_Cx_RESET_EXT_BASE register fields */ |
| 381 | #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_SHF 31 |
| 382 | #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_MSK (_ULCAST_(0x1) << 31) |
| 383 | #define CM_GCR_Cx_RESET_EXT_BASE_UEB_SHF 30 |
| 384 | #define CM_GCR_Cx_RESET_EXT_BASE_UEB_MSK (_ULCAST_(0x1) << 30) |
| 385 | #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_SHF 20 |
| 386 | #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_MSK (_ULCAST_(0xff) << 20) |
| 387 | #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_SHF 1 |
| 388 | #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_MSK (_ULCAST_(0x7f) << 1) |
| 389 | #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_SHF 0 |
| 390 | #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_MSK (_ULCAST_(0x1) << 0) |
| 391 | |
| 392 | /** |
| 393 | * mips_cm_numcores - return the number of cores present in the system |
| 394 | * |
| 395 | * Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or |
| 396 | * zero if no Coherence Manager is present. |
| 397 | */ |
| 398 | static inline unsigned mips_cm_numcores(void) |
| 399 | { |
| 400 | if (!mips_cm_present()) |
| 401 | return 0; |
| 402 | |
| 403 | return ((read_gcr_config() & CM_GCR_CONFIG_PCORES_MSK) |
| 404 | >> CM_GCR_CONFIG_PCORES_SHF) + 1; |
| 405 | } |
| 406 | |
| 407 | /** |
| 408 | * mips_cm_numiocu - return the number of IOCUs present in the system |
| 409 | * |
| 410 | * Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero |
| 411 | * if no Coherence Manager is present. |
| 412 | */ |
| 413 | static inline unsigned mips_cm_numiocu(void) |
| 414 | { |
| 415 | if (!mips_cm_present()) |
| 416 | return 0; |
| 417 | |
| 418 | return (read_gcr_config() & CM_GCR_CONFIG_NUMIOCU_MSK) |
| 419 | >> CM_GCR_CONFIG_NUMIOCU_SHF; |
| 420 | } |
| 421 | |
| 422 | /** |
| 423 | * mips_cm_l2sync - perform an L2-only sync operation |
| 424 | * |
| 425 | * If an L2-only sync region is present in the system then this function |
| 426 | * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV. |
| 427 | */ |
| 428 | static inline int mips_cm_l2sync(void) |
| 429 | { |
| 430 | if (!mips_cm_has_l2sync()) |
| 431 | return -ENODEV; |
| 432 | |
| 433 | writel(0, mips_cm_l2sync_base); |
| 434 | return 0; |
| 435 | } |
| 436 | |
Paul Burton | 197e89e | 2015-07-10 10:12:52 +0100 | [diff] [blame] | 437 | /** |
| 438 | * mips_cm_revision() - return CM revision |
| 439 | * |
| 440 | * Return: The revision of the CM, from GCR_REV, or 0 if no CM is present. The |
| 441 | * return value should be checked against the CM_REV_* macros. |
| 442 | */ |
| 443 | static inline int mips_cm_revision(void) |
| 444 | { |
| 445 | if (!mips_cm_present()) |
| 446 | return 0; |
| 447 | |
| 448 | return read_gcr_rev(); |
| 449 | } |
| 450 | |
Paul Burton | 7573b94 | 2015-09-22 11:29:09 -0700 | [diff] [blame] | 451 | /** |
| 452 | * mips_cm_max_vp_width() - return the width in bits of VP indices |
| 453 | * |
| 454 | * Return: the width, in bits, of VP indices in fields that combine core & VP |
| 455 | * indices. |
| 456 | */ |
| 457 | static inline unsigned int mips_cm_max_vp_width(void) |
| 458 | { |
| 459 | extern int smp_num_siblings; |
| 460 | |
| 461 | if (mips_cm_revision() >= CM_REV_CM3) |
| 462 | return read_gcr_sys_config2() & CM_GCR_SYS_CONFIG2_MAXVPW_MSK; |
| 463 | |
| 464 | return smp_num_siblings; |
| 465 | } |
| 466 | |
| 467 | /** |
| 468 | * mips_cm_vp_id() - calculate the hardware VP ID for a CPU |
| 469 | * @cpu: the CPU whose VP ID to calculate |
| 470 | * |
| 471 | * Hardware such as the GIC uses identifiers for VPs which may not match the |
| 472 | * CPU numbers used by Linux. This function calculates the hardware VP |
| 473 | * identifier corresponding to a given CPU. |
| 474 | * |
| 475 | * Return: the VP ID for the CPU. |
| 476 | */ |
| 477 | static inline unsigned int mips_cm_vp_id(unsigned int cpu) |
| 478 | { |
| 479 | unsigned int core = cpu_data[cpu].core; |
| 480 | unsigned int vp = cpu_vpe_id(&cpu_data[cpu]); |
| 481 | |
| 482 | return (core * mips_cm_max_vp_width()) + vp; |
| 483 | } |
| 484 | |
Paul Burton | 23d5de8 | 2015-09-22 11:12:16 -0700 | [diff] [blame] | 485 | #ifdef CONFIG_MIPS_CM |
| 486 | |
| 487 | /** |
| 488 | * mips_cm_lock_other - lock access to another core |
| 489 | * @core: the other core to be accessed |
| 490 | * @vp: the VP within the other core to be accessed |
| 491 | * |
| 492 | * Call before operating upon a core via the 'other' register region in |
| 493 | * order to prevent the region being moved during access. Must be followed |
| 494 | * by a call to mips_cm_unlock_other. |
| 495 | */ |
| 496 | extern void mips_cm_lock_other(unsigned int core, unsigned int vp); |
| 497 | |
| 498 | /** |
| 499 | * mips_cm_unlock_other - unlock access to another core |
| 500 | * |
| 501 | * Call after operating upon another core via the 'other' register region. |
| 502 | * Must be called after mips_cm_lock_other. |
| 503 | */ |
| 504 | extern void mips_cm_unlock_other(void); |
| 505 | |
| 506 | #else /* !CONFIG_MIPS_CM */ |
| 507 | |
| 508 | static inline void mips_cm_lock_other(unsigned int core) { } |
| 509 | static inline void mips_cm_unlock_other(void) { } |
| 510 | |
| 511 | #endif /* !CONFIG_MIPS_CM */ |
| 512 | |
Paul Burton | 9f98f3d | 2014-01-15 10:31:51 +0000 | [diff] [blame] | 513 | #endif /* __MIPS_ASM_MIPS_CM_H__ */ |