blob: 52162d59407a4679eee5fce0f4d848a62b2ea182 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * The ARM LDRD and Thumb LDRSB instructions use bit 20/11 (ARM/Thumb)
3 * differently than every other instruction, so it is set to 0 (write)
4 * even though the instructions are read instructions. This means that
5 * during an abort the instructions will be treated as a write and the
6 * handler will raise a signal from unwriteable locations if they
7 * fault. We have to specifically check for these instructions
8 * from the abort handlers to treat them properly.
9 *
10 */
11
Russell Kingbe020f82011-06-26 13:42:01 +010012 .macro do_thumb_abort, fsr, pc, psr, tmp
13 tst \psr, #PSR_T_BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -070014 beq not_thumb
Russell Kingbe020f82011-06-26 13:42:01 +010015 ldrh \tmp, [\pc] @ Read aborted Thumb instruction
16 and \tmp, \tmp, # 0xfe00 @ Mask opcode field
17 cmp \tmp, # 0x5600 @ Is it ldrsb?
18 orreq \tmp, \tmp, #1 << 11 @ Set L-bit if yes
19 tst \tmp, #1 << 11 @ L = 0 -> write
20 orreq \psr, \psr, #1 << 11 @ yes.
Russell Kingda740472011-06-26 16:01:26 +010021 b do_DataAbort
Linus Torvalds1da177e2005-04-16 15:20:36 -070022not_thumb:
23 .endm
24
25/*
Russell Kingbe020f82011-06-26 13:42:01 +010026 * We check for the following instruction encoding for LDRD.
Linus Torvalds1da177e2005-04-16 15:20:36 -070027 *
Russell Kingbe020f82011-06-26 13:42:01 +010028 * [27:25] == 000
Linus Torvalds1da177e2005-04-16 15:20:36 -070029 * [7:4] == 1101
30 * [20] == 0
31 */
Russell Kingbe020f82011-06-26 13:42:01 +010032 .macro do_ldrd_abort, tmp, insn
Russell King198a0a92011-06-26 13:51:44 +010033 tst \insn, #0x0e100000 @ [27:25,20] == 0
Linus Torvalds1da177e2005-04-16 15:20:36 -070034 bne not_ldrd
Russell Kingbe020f82011-06-26 13:42:01 +010035 and \tmp, \insn, #0x000000f0 @ [7:4] == 1101
36 cmp \tmp, #0x000000d0
Russell Kingda740472011-06-26 16:01:26 +010037 beq do_DataAbort
Linus Torvalds1da177e2005-04-16 15:20:36 -070038not_ldrd:
39 .endm
40