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Ryan Mallon258249e2012-01-11 09:06:08 +11001/*
2 * arch/arm/mach-ep93xx/soc.h
3 *
4 * Copyright (C) 2012 Open Kernel Labs <www.ok-labs.com>
5 * Copyright (C) 2012 Ryan Mallon <rmallon@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or (at
10 * your option) any later version.
11 */
12
13#ifndef _EP93XX_SOC_H
14#define _EP93XX_SOC_H
15
Ryan Mallona6de3df2012-01-11 13:14:20 +110016#include <mach/ep93xx-regs.h>
17
Ryan Mallon258249e2012-01-11 09:06:08 +110018/*
19 * EP93xx Physical Memory Map:
20 *
21 * The ASDO pin is sampled at system reset to select a synchronous or
22 * asynchronous boot configuration. When ASDO is "1" (i.e. pulled-up)
23 * the synchronous boot mode is selected. When ASDO is "0" (i.e
24 * pulled-down) the asynchronous boot mode is selected.
25 *
26 * In synchronous boot mode nSDCE3 is decoded starting at physical address
27 * 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous
28 * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
29 * decoded at 0xf0000000.
30 *
31 * There is known errata for the EP93xx dealing with External Memory
32 * Configurations. Please refer to "AN273: EP93xx Silicon Rev E Design
33 * Guidelines" for more information. This document can be found at:
34 *
35 * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
36 */
37
38#define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */
39#define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin = 1 */
40#define EP93XX_CS1_PHYS_BASE 0x10000000
41#define EP93XX_CS2_PHYS_BASE 0x20000000
42#define EP93XX_CS3_PHYS_BASE 0x30000000
43#define EP93XX_PCMCIA_PHYS_BASE 0x40000000
44#define EP93XX_CS6_PHYS_BASE 0x60000000
45#define EP93XX_CS7_PHYS_BASE 0x70000000
46#define EP93XX_SDCE0_PHYS_BASE 0xc0000000
47#define EP93XX_SDCE1_PHYS_BASE 0xd0000000
48#define EP93XX_SDCE2_PHYS_BASE 0xe0000000
49#define EP93XX_SDCE3_PHYS_BASE_ASYNC 0xf0000000 /* ASDO Pin = 0 */
50#define EP93XX_CS0_PHYS_BASE_SYNC 0xf0000000 /* ASDO Pin = 1 */
51
Ryan Mallona05baf32012-01-11 09:29:26 +110052/* AHB peripherals */
53#define EP93XX_DMA_BASE EP93XX_AHB_IOMEM(0x00000000)
54
55#define EP93XX_ETHERNET_PHYS_BASE EP93XX_AHB_PHYS(0x00010000)
56#define EP93XX_ETHERNET_BASE EP93XX_AHB_IOMEM(0x00010000)
57
58#define EP93XX_USB_PHYS_BASE EP93XX_AHB_PHYS(0x00020000)
59#define EP93XX_USB_BASE EP93XX_AHB_IOMEM(0x00020000)
60
61#define EP93XX_RASTER_PHYS_BASE EP93XX_AHB_PHYS(0x00030000)
62#define EP93XX_RASTER_BASE EP93XX_AHB_IOMEM(0x00030000)
63
64#define EP93XX_GRAPHICS_ACCEL_BASE EP93XX_AHB_IOMEM(0x00040000)
65
66#define EP93XX_SDRAM_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00060000)
67
68#define EP93XX_PCMCIA_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00080000)
69
70#define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000)
71
Rafal Prylowskieb774a02012-04-12 14:14:12 +020072#define EP93XX_IDE_PHYS_BASE EP93XX_AHB_PHYS(0x000a0000)
Ryan Mallona05baf32012-01-11 09:29:26 +110073#define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000)
74
75#define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000)
76
77#define EP93XX_VIC2_BASE EP93XX_AHB_IOMEM(0x000c0000)
78
79/* APB peripherals */
80#define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000)
81
82#define EP93XX_I2S_PHYS_BASE EP93XX_APB_PHYS(0x00020000)
83#define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000)
84
85#define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000)
86
87#define EP93XX_AAC_PHYS_BASE EP93XX_APB_PHYS(0x00080000)
88#define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000)
89
90#define EP93XX_SPI_PHYS_BASE EP93XX_APB_PHYS(0x000a0000)
91#define EP93XX_SPI_BASE EP93XX_APB_IOMEM(0x000a0000)
92
93#define EP93XX_IRDA_BASE EP93XX_APB_IOMEM(0x000b0000)
94
95#define EP93XX_KEY_MATRIX_PHYS_BASE EP93XX_APB_PHYS(0x000f0000)
96#define EP93XX_KEY_MATRIX_BASE EP93XX_APB_IOMEM(0x000f0000)
97
98#define EP93XX_ADC_BASE EP93XX_APB_IOMEM(0x00100000)
99#define EP93XX_TOUCHSCREEN_BASE EP93XX_APB_IOMEM(0x00100000)
100
101#define EP93XX_PWM_PHYS_BASE EP93XX_APB_PHYS(0x00110000)
102#define EP93XX_PWM_BASE EP93XX_APB_IOMEM(0x00110000)
103
104#define EP93XX_RTC_PHYS_BASE EP93XX_APB_PHYS(0x00120000)
105#define EP93XX_RTC_BASE EP93XX_APB_IOMEM(0x00120000)
106
107#define EP93XX_WATCHDOG_PHYS_BASE EP93XX_APB_PHYS(0x00140000)
108#define EP93XX_WATCHDOG_BASE EP93XX_APB_IOMEM(0x00140000)
109
Ryan Mallon9aeec632012-01-11 12:53:33 +1100110/* System controller */
111#define EP93XX_SYSCON_BASE EP93XX_APB_IOMEM(0x00130000)
112#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x))
113#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00)
114#define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04)
115#define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31)
116#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29)
117#define EP93XX_SYSCON_PWRCNT_USH_EN (1<<28)
118#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 (1<<27)
119#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 (1<<26)
120#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 (1<<25)
121#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 (1<<24)
122#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 (1<<23)
123#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 (1<<22)
124#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 (1<<21)
125#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 (1<<20)
126#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 (1<<19)
127#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 (1<<18)
128#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 (1<<17)
129#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1<<16)
130#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
131#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
132#define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20)
133#define EP93XX_SYSCON_CLKSET1_NBYP1 (1<<23)
134#define EP93XX_SYSCON_CLKSET2 EP93XX_SYSCON_REG(0x24)
135#define EP93XX_SYSCON_CLKSET2_NBYP2 (1<<19)
136#define EP93XX_SYSCON_CLKSET2_PLL2_EN (1<<18)
137#define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80)
138#define EP93XX_SYSCON_DEVCFG_SWRST (1<<31)
139#define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30)
140#define EP93XX_SYSCON_DEVCFG_D0ONG (1<<29)
141#define EP93XX_SYSCON_DEVCFG_IONU2 (1<<28)
142#define EP93XX_SYSCON_DEVCFG_GONK (1<<27)
143#define EP93XX_SYSCON_DEVCFG_TONG (1<<26)
144#define EP93XX_SYSCON_DEVCFG_MONG (1<<25)
145#define EP93XX_SYSCON_DEVCFG_U3EN (1<<24)
146#define EP93XX_SYSCON_DEVCFG_CPENA (1<<23)
147#define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22)
148#define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21)
149#define EP93XX_SYSCON_DEVCFG_U2EN (1<<20)
150#define EP93XX_SYSCON_DEVCFG_EXVC (1<<19)
151#define EP93XX_SYSCON_DEVCFG_U1EN (1<<18)
152#define EP93XX_SYSCON_DEVCFG_TIN (1<<17)
153#define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15)
154#define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14)
155#define EP93XX_SYSCON_DEVCFG_HC1IN (1<<13)
156#define EP93XX_SYSCON_DEVCFG_HC1EN (1<<12)
157#define EP93XX_SYSCON_DEVCFG_HONIDE (1<<11)
158#define EP93XX_SYSCON_DEVCFG_GONIDE (1<<10)
159#define EP93XX_SYSCON_DEVCFG_PONG (1<<9)
160#define EP93XX_SYSCON_DEVCFG_EONIDE (1<<8)
161#define EP93XX_SYSCON_DEVCFG_I2SONSSP (1<<7)
162#define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1<<6)
163#define EP93XX_SYSCON_DEVCFG_RASONP3 (1<<4)
164#define EP93XX_SYSCON_DEVCFG_RAS (1<<3)
165#define EP93XX_SYSCON_DEVCFG_ADCPD (1<<2)
166#define EP93XX_SYSCON_DEVCFG_KEYS (1<<1)
167#define EP93XX_SYSCON_DEVCFG_SHENA (1<<0)
168#define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84)
169#define EP93XX_SYSCON_CLKDIV_ENABLE (1<<15)
170#define EP93XX_SYSCON_CLKDIV_ESEL (1<<14)
171#define EP93XX_SYSCON_CLKDIV_PSEL (1<<13)
172#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
173#define EP93XX_SYSCON_I2SCLKDIV EP93XX_SYSCON_REG(0x8c)
174#define EP93XX_SYSCON_I2SCLKDIV_SENA (1<<31)
175#define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1<<29)
176#define EP93XX_SYSCON_I2SCLKDIV_SPOL (1<<19)
177#define EP93XX_I2SCLKDIV_SDIV (1 << 16)
178#define EP93XX_I2SCLKDIV_LRDIV32 (0 << 17)
179#define EP93XX_I2SCLKDIV_LRDIV64 (1 << 17)
180#define EP93XX_I2SCLKDIV_LRDIV128 (2 << 17)
181#define EP93XX_I2SCLKDIV_LRDIV_MASK (3 << 17)
182#define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90)
183#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31)
184#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16)
185#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN (1<<15)
186#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
187#define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c)
188#define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000)
189#define EP93XX_SYSCON_SYSCFG_REV_SHIFT (28)
190#define EP93XX_SYSCON_SYSCFG_SBOOT (1<<8)
191#define EP93XX_SYSCON_SYSCFG_LCSN7 (1<<7)
192#define EP93XX_SYSCON_SYSCFG_LCSN6 (1<<6)
193#define EP93XX_SYSCON_SYSCFG_LASDO (1<<5)
194#define EP93XX_SYSCON_SYSCFG_LEEDA (1<<4)
195#define EP93XX_SYSCON_SYSCFG_LEECLK (1<<3)
196#define EP93XX_SYSCON_SYSCFG_LCSN2 (1<<1)
197#define EP93XX_SYSCON_SYSCFG_LCSN1 (1<<0)
198#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
199
Ryan Mallon999c53f2012-01-11 13:43:02 +1100200/* EP93xx System Controller software locked register write */
201void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
202void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
203
204static inline void ep93xx_devcfg_set_bits(unsigned int bits)
205{
206 ep93xx_devcfg_set_clear(bits, 0x00);
207}
208
209static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
210{
211 ep93xx_devcfg_set_clear(0x00, bits);
212}
213
Ryan Mallon258249e2012-01-11 09:06:08 +1100214#endif /* _EP93XX_SOC_H */