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Russell Kinga09e64f2008-08-05 16:14:15 +01001/*
Russell Kinga09e64f2008-08-05 16:14:15 +01002 * Copyright (C) 2008 ARM Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef __ASM_ARCH_BOARD_PB1176_H
20#define __ASM_ARCH_BOARD_PB1176_H
21
Arnd Bergmann6d407a62015-11-25 17:32:22 +010022#include "platform.h"
Russell Kinga09e64f2008-08-05 16:14:15 +010023
24/*
25 * Peripheral addresses
26 */
Linus Walleij48f1d5a2010-07-02 10:24:03 +010027#define REALVIEW_PB1176_UART4_BASE 0x10009000 /* UART 4 */
Russell Kinga09e64f2008-08-05 16:14:15 +010028#define REALVIEW_PB1176_SCTL_BASE 0x10100000 /* System controller */
29#define REALVIEW_PB1176_SMC_BASE 0x10111000 /* SMC */
30#define REALVIEW_PB1176_DMC_BASE 0x10109000 /* DMC configuration */
31#define REALVIEW_PB1176_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
32#define REALVIEW_PB1176_FLASH_BASE 0x30000000
33#define REALVIEW_PB1176_FLASH_SIZE SZ_64M
Catalin Marinasaf607742009-05-30 13:56:13 +010034#define REALVIEW_PB1176_SEC_FLASH_BASE 0x3C000000 /* Secure flash */
35#define REALVIEW_PB1176_SEC_FLASH_SIZE SZ_64M
Russell Kinga09e64f2008-08-05 16:14:15 +010036
37#define REALVIEW_PB1176_TIMER0_1_BASE 0x10104000 /* Timer 0 and 1 */
38#define REALVIEW_PB1176_TIMER2_3_BASE 0x10105000 /* Timer 2 and 3 */
39#define REALVIEW_PB1176_TIMER4_5_BASE 0x10106000 /* Timer 4 and 5 */
40#define REALVIEW_PB1176_WATCHDOG_BASE 0x10107000 /* watchdog interface */
41#define REALVIEW_PB1176_RTC_BASE 0x10108000 /* Real Time Clock */
42#define REALVIEW_PB1176_GPIO0_BASE 0x1010A000 /* GPIO port 0 */
43#define REALVIEW_PB1176_SSP_BASE 0x1010B000 /* Synchronous Serial Port */
44#define REALVIEW_PB1176_UART0_BASE 0x1010C000 /* UART 0 */
45#define REALVIEW_PB1176_UART1_BASE 0x1010D000 /* UART 1 */
46#define REALVIEW_PB1176_UART2_BASE 0x1010E000 /* UART 2 */
47#define REALVIEW_PB1176_UART3_BASE 0x1010F000 /* UART 3 */
48#define REALVIEW_PB1176_CLCD_BASE 0x10112000 /* CLCD */
49#define REALVIEW_PB1176_ETH_BASE 0x3A000000 /* Ethernet */
50#define REALVIEW_PB1176_USB_BASE 0x3B000000 /* USB */
51
52/*
53 * PCI regions
54 */
55#define REALVIEW_PB1176_PCI_BASE 0x60000000 /* PCI self config */
56#define REALVIEW_PB1176_PCI_CFG_BASE 0x61000000 /* PCI config */
57#define REALVIEW_PB1176_PCI_IO_BASE0 0x62000000 /* PCI IO region */
58#define REALVIEW_PB1176_PCI_MEM_BASE0 0x63000000 /* Memory region 1 */
59#define REALVIEW_PB1176_PCI_MEM_BASE1 0x64000000 /* Memory region 2 */
60#define REALVIEW_PB1176_PCI_MEM_BASE2 0x68000000 /* Memory region 3 */
61
62#define REALVIEW_PB1176_PCI_BASE_SIZE 0x01000000 /* 16MB */
63#define REALVIEW_PB1176_PCI_CFG_BASE_SIZE 0x01000000 /* 16MB */
64#define REALVIEW_PB1176_PCI_IO_BASE0_SIZE 0x01000000 /* 16MB */
65#define REALVIEW_PB1176_PCI_MEM_BASE0_SIZE 0x01000000 /* 16MB */
66#define REALVIEW_PB1176_PCI_MEM_BASE1_SIZE 0x04000000 /* 64MB */
67#define REALVIEW_PB1176_PCI_MEM_BASE2_SIZE 0x08000000 /* 128MB */
68
69#define REALVIEW_DC1176_GIC_CPU_BASE 0x10120000 /* GIC CPU interface, on devchip */
70#define REALVIEW_DC1176_GIC_DIST_BASE 0x10121000 /* GIC distributor, on devchip */
Linus Walleij0ec5a952011-09-06 07:50:20 +010071#define REALVIEW_DC1176_ROM_BASE 0x10200000 /* 16KiB NRAM preudo-ROM, on devchip */
Russell Kinga09e64f2008-08-05 16:14:15 +010072#define REALVIEW_PB1176_GIC_CPU_BASE 0x10040000 /* GIC CPU interface, on FPGA */
73#define REALVIEW_PB1176_GIC_DIST_BASE 0x10041000 /* GIC distributor, on FPGA */
74#define REALVIEW_PB1176_L220_BASE 0x10110000 /* L220 registers */
75
Philby John426fcd22009-10-28 19:09:12 +010076/*
Colin Tuckley4c9f8be2010-01-11 11:09:15 +010077 * Control register SYS_RESETCTL Bit 8 is set to 1 to force a soft reset
Philby John426fcd22009-10-28 19:09:12 +010078 */
Colin Tuckley4c9f8be2010-01-11 11:09:15 +010079#define REALVIEW_PB1176_SYS_SOFT_RESET 0x0100
Philby John426fcd22009-10-28 19:09:12 +010080
Russell Kinga09e64f2008-08-05 16:14:15 +010081#endif /* __ASM_ARCH_BOARD_PB1176_H */