Masahiro Yamada | b1e4006 | 2015-10-02 13:42:20 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #include <linux/linkage.h> |
| 16 | #include <asm/assembler.h> |
| 17 | #include <asm/cp15.h> |
| 18 | |
| 19 | ENTRY(uniphier_smp_trampoline) |
| 20 | ARM_BE8(setend be) @ ensure we are in BE8 mode |
| 21 | mrc p15, 0, r0, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Reg) |
| 22 | and r2, r0, #0x3 @ CPU ID |
| 23 | ldr r1, uniphier_smp_trampoline_jump |
| 24 | ldr r3, uniphier_smp_trampoline_poll_addr |
| 25 | mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) |
| 26 | orr r0, r0, #CR_I @ Enable ICache |
| 27 | bic r0, r0, #(CR_C | CR_M) @ Disable MMU and Dcache |
| 28 | mcr p15, 0, r0, c1, c0, 0 |
| 29 | b 1f @ cache the following 5 instructions |
| 30 | 0: wfe |
| 31 | 1: ldr r0, [r3] |
| 32 | cmp r0, r2 |
| 33 | bxeq r1 @ branch to secondary_startup |
| 34 | b 0b |
| 35 | .globl uniphier_smp_trampoline_jump |
| 36 | uniphier_smp_trampoline_jump: |
| 37 | .word 0 @ set virt_to_phys(secondary_startup) |
| 38 | .globl uniphier_smp_trampoline_poll_addr |
| 39 | uniphier_smp_trampoline_poll_addr: |
| 40 | .word 0 @ set CPU ID to be kicked to this reg |
| 41 | .globl uniphier_smp_trampoline_end |
| 42 | uniphier_smp_trampoline_end: |
| 43 | ENDPROC(uniphier_smp_trampoline) |