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Mika Westerberg7981c0012015-03-30 17:31:49 +03001/*
2 * Core pinctrl/GPIO driver for Intel GPIO controllers
3 *
4 * Copyright (C) 2015, Intel Corporation
5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Mika Westerberg <mika.westerberg@linux.intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef PINCTRL_INTEL_H
14#define PINCTRL_INTEL_H
15
16struct pinctrl_pin_desc;
17struct platform_device;
18struct device;
19
20/**
21 * struct intel_pingroup - Description about group of pins
22 * @name: Name of the groups
23 * @pins: All pins in this group
24 * @npins: Number of pins in this groups
25 * @mode: Native mode in which the group is muxed out @pins
26 */
27struct intel_pingroup {
28 const char *name;
29 const unsigned *pins;
30 size_t npins;
31 unsigned short mode;
32};
33
34/**
35 * struct intel_function - Description about a function
36 * @name: Name of the function
37 * @groups: An array of groups for this function
38 * @ngroups: Number of groups in @groups
39 */
40struct intel_function {
41 const char *name;
42 const char * const *groups;
43 size_t ngroups;
44};
45
46/**
47 * struct intel_community - Intel pin community description
48 * @barno: MMIO BAR number where registers for this community reside
49 * @padown_offset: Register offset of PAD_OWN register from @regs. If %0
50 * then there is no support for owner.
51 * @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then
52 * locking is not supported.
53 * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
54 * is assumed that the host owns the pin (rather than
55 * ACPI).
56 * @ie_offset: Register offset of GPI_IE from @regs.
57 * @pin_base: Starting pin of pins in this community
Qipeng Zha618a919b2015-11-26 01:09:51 +080058 * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
59 * HOSTSW_OWN, GPI_IS, GPI_IE, etc.
Mika Westerberg7981c0012015-03-30 17:31:49 +030060 * @npins: Number of pins in this community
61 * @regs: Community specific common registers (reserved for core driver)
62 * @pad_regs: Community specific pad registers (reserved for core driver)
63 * @ngpps: Number of groups (hw groups) in this community (reserved for
64 * core driver)
65 */
66struct intel_community {
67 unsigned barno;
68 unsigned padown_offset;
69 unsigned padcfglock_offset;
70 unsigned hostown_offset;
71 unsigned ie_offset;
72 unsigned pin_base;
Qipeng Zha618a919b2015-11-26 01:09:51 +080073 unsigned gpp_size;
Mika Westerberg7981c0012015-03-30 17:31:49 +030074 size_t npins;
75 void __iomem *regs;
76 void __iomem *pad_regs;
77 size_t ngpps;
78};
79
80#define PIN_GROUP(n, p, m) \
81 { \
82 .name = (n), \
83 .pins = (p), \
84 .npins = ARRAY_SIZE((p)), \
85 .mode = (m), \
86 }
87
88#define FUNCTION(n, g) \
89 { \
90 .name = (n), \
91 .groups = (g), \
92 .ngroups = ARRAY_SIZE((g)), \
93 }
94
95/**
96 * struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration
97 * @uid: ACPI _UID for the probe driver use if needed
98 * @pins: Array if pins this pinctrl controls
99 * @npins: Number of pins in the array
100 * @groups: Array of pin groups
101 * @ngroups: Number of groups in the array
102 * @functions: Array of functions
103 * @nfunctions: Number of functions in the array
104 * @communities: Array of communities this pinctrl handles
105 * @ncommunities: Number of communities in the array
106 *
107 * The @communities is used as a template by the core driver. It will make
108 * copy of all communities and fill in rest of the information.
109 */
110struct intel_pinctrl_soc_data {
111 const char *uid;
112 const struct pinctrl_pin_desc *pins;
113 size_t npins;
114 const struct intel_pingroup *groups;
115 size_t ngroups;
116 const struct intel_function *functions;
117 size_t nfunctions;
118 const struct intel_community *communities;
119 size_t ncommunities;
120};
121
122int intel_pinctrl_probe(struct platform_device *pdev,
123 const struct intel_pinctrl_soc_data *soc_data);
124int intel_pinctrl_remove(struct platform_device *pdev);
125
126#ifdef CONFIG_PM_SLEEP
127int intel_pinctrl_suspend(struct device *dev);
128int intel_pinctrl_resume(struct device *dev);
129#endif
130
131#endif /* PINCTRL_INTEL_H */