| Paul Mundt | b6d7b66 | 2007-11-22 16:29:10 +0900 | [diff] [blame^] | 1 | /* |
| 2 | * Support functions for the SH5 PCI hardware. |
| 3 | * |
| 4 | * Copyright (C) 2001 David J. Mckay (david.mckay@st.com) |
| 5 | * Copyright (C) 2003, 2004 Paul Mundt |
| 6 | * Copyright (C) 2004 Richard Curnow |
| 7 | * |
| 8 | * May be copied or modified under the terms of the GNU General Public |
| 9 | * License. See linux/COPYING for more information. |
| 10 | */ |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/rwsem.h> |
| 13 | #include <linux/smp.h> |
| 14 | #include <linux/interrupt.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/errno.h> |
| 17 | #include <linux/pci.h> |
| 18 | #include <linux/delay.h> |
| 19 | #include <linux/types.h> |
| 20 | #include <linux/irq.h> |
| 21 | #include <asm/pci.h> |
| 22 | #include <asm/io.h> |
| 23 | #include "pci-sh5.h" |
| 24 | |
| 25 | static void __init pci_fixup_ide_bases(struct pci_dev *d) |
| 26 | { |
| 27 | int i; |
| 28 | |
| 29 | /* |
| 30 | * PCI IDE controllers use non-standard I/O port decoding, respect it. |
| 31 | */ |
| 32 | if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE) |
| 33 | return; |
| 34 | printk("PCI: IDE base address fixup for %s\n", pci_name(d)); |
| 35 | for(i=0; i<4; i++) { |
| 36 | struct resource *r = &d->resource[i]; |
| 37 | if ((r->start & ~0x80) == 0x374) { |
| 38 | r->start |= 2; |
| 39 | r->end = r->start; |
| 40 | } |
| 41 | } |
| 42 | } |
| 43 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases); |
| 44 | |
| 45 | char * __devinit pcibios_setup(char *str) |
| 46 | { |
| 47 | return str; |
| 48 | } |
| 49 | |
| 50 | static int sh5pci_read(struct pci_bus *bus, unsigned int devfn, int where, |
| 51 | int size, u32 *val) |
| 52 | { |
| 53 | SH5PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where)); |
| 54 | |
| 55 | switch (size) { |
| 56 | case 1: |
| 57 | *val = (u8)SH5PCI_READ_BYTE(PDR + (where & 3)); |
| 58 | break; |
| 59 | case 2: |
| 60 | *val = (u16)SH5PCI_READ_SHORT(PDR + (where & 2)); |
| 61 | break; |
| 62 | case 4: |
| 63 | *val = SH5PCI_READ(PDR); |
| 64 | break; |
| 65 | } |
| 66 | |
| 67 | return PCIBIOS_SUCCESSFUL; |
| 68 | } |
| 69 | |
| 70 | static int sh5pci_write(struct pci_bus *bus, unsigned int devfn, int where, |
| 71 | int size, u32 val) |
| 72 | { |
| 73 | SH5PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where)); |
| 74 | |
| 75 | switch (size) { |
| 76 | case 1: |
| 77 | SH5PCI_WRITE_BYTE(PDR + (where & 3), (u8)val); |
| 78 | break; |
| 79 | case 2: |
| 80 | SH5PCI_WRITE_SHORT(PDR + (where & 2), (u16)val); |
| 81 | break; |
| 82 | case 4: |
| 83 | SH5PCI_WRITE(PDR, val); |
| 84 | break; |
| 85 | } |
| 86 | |
| 87 | return PCIBIOS_SUCCESSFUL; |
| 88 | } |
| 89 | |
| 90 | struct pci_ops sh5_pci_ops = { |
| 91 | .read = sh5pci_read, |
| 92 | .write = sh5pci_write, |
| 93 | }; |