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Dmitry Eremin-Solenikov5d8c6652011-06-29 05:07:56 +00001/*
2 * Copyright (C) 2011 Dmitry Eremin-Solenikov
3 * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 * and Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
11 * that is iMac G5 and latest single CPU desktop.
12 */
13
14#undef DEBUG
15
16#include <linux/module.h>
17#include <linux/types.h>
18#include <linux/errno.h>
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/sched.h>
22#include <linux/cpufreq.h>
23#include <linux/init.h>
24#include <linux/completion.h>
25#include <linux/mutex.h>
26#include <linux/time.h>
Sudeep KarkadaNagesha2421d4c2013-07-17 12:39:29 +010027#include <linux/of_device.h>
Dmitry Eremin-Solenikov5d8c6652011-06-29 05:07:56 +000028
29#define DBG(fmt...) pr_debug(fmt)
30
31/* see 970FX user manual */
32
33#define SCOM_PCR 0x0aa001 /* PCR scom addr */
34
35#define PCR_HILO_SELECT 0x80000000U /* 1 = PCR, 0 = PCRH */
36#define PCR_SPEED_FULL 0x00000000U /* 1:1 speed value */
37#define PCR_SPEED_HALF 0x00020000U /* 1:2 speed value */
38#define PCR_SPEED_QUARTER 0x00040000U /* 1:4 speed value */
39#define PCR_SPEED_MASK 0x000e0000U /* speed mask */
40#define PCR_SPEED_SHIFT 17
41#define PCR_FREQ_REQ_VALID 0x00010000U /* freq request valid */
42#define PCR_VOLT_REQ_VALID 0x00008000U /* volt request valid */
43#define PCR_TARGET_TIME_MASK 0x00006000U /* target time */
44#define PCR_STATLAT_MASK 0x00001f00U /* STATLAT value */
45#define PCR_SNOOPLAT_MASK 0x000000f0U /* SNOOPLAT value */
46#define PCR_SNOOPACC_MASK 0x0000000fU /* SNOOPACC value */
47
48#define SCOM_PSR 0x408001 /* PSR scom addr */
49/* warning: PSR is a 64 bits register */
50#define PSR_CMD_RECEIVED 0x2000000000000000U /* command received */
51#define PSR_CMD_COMPLETED 0x1000000000000000U /* command completed */
52#define PSR_CUR_SPEED_MASK 0x0300000000000000U /* current speed */
53#define PSR_CUR_SPEED_SHIFT (56)
54
55/*
56 * The G5 only supports two frequencies (Quarter speed is not supported)
57 */
58#define CPUFREQ_HIGH 0
59#define CPUFREQ_LOW 1
60
61static struct cpufreq_frequency_table maple_cpu_freqs[] = {
62 {CPUFREQ_HIGH, 0},
63 {CPUFREQ_LOW, 0},
64 {0, CPUFREQ_TABLE_END},
65};
66
Dmitry Eremin-Solenikov5d8c6652011-06-29 05:07:56 +000067/* Power mode data is an array of the 32 bits PCR values to use for
68 * the various frequencies, retrieved from the device-tree
69 */
70static int maple_pmode_cur;
71
72static DEFINE_MUTEX(maple_switch_mutex);
73
74static const u32 *maple_pmode_data;
75static int maple_pmode_max;
76
77/*
78 * SCOM based frequency switching for 970FX rev3
79 */
80static int maple_scom_switch_freq(int speed_mode)
81{
82 unsigned long flags;
83 int to;
84
85 local_irq_save(flags);
86
87 /* Clear PCR high */
88 scom970_write(SCOM_PCR, 0);
89 /* Clear PCR low */
90 scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
91 /* Set PCR low */
92 scom970_write(SCOM_PCR, PCR_HILO_SELECT |
93 maple_pmode_data[speed_mode]);
94
95 /* Wait for completion */
96 for (to = 0; to < 10; to++) {
97 unsigned long psr = scom970_read(SCOM_PSR);
98
99 if ((psr & PSR_CMD_RECEIVED) == 0 &&
100 (((psr >> PSR_CUR_SPEED_SHIFT) ^
101 (maple_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
102 == 0)
103 break;
104 if (psr & PSR_CMD_COMPLETED)
105 break;
106 udelay(100);
107 }
108
109 local_irq_restore(flags);
110
111 maple_pmode_cur = speed_mode;
112 ppc_proc_freq = maple_cpu_freqs[speed_mode].frequency * 1000ul;
113
114 return 0;
115}
116
117static int maple_scom_query_freq(void)
118{
119 unsigned long psr = scom970_read(SCOM_PSR);
120 int i;
121
122 for (i = 0; i <= maple_pmode_max; i++)
123 if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
124 (maple_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
125 break;
126 return i;
127}
128
129/*
130 * Common interface to the cpufreq core
131 */
132
Dmitry Eremin-Solenikov5d8c6652011-06-29 05:07:56 +0000133static int maple_cpufreq_target(struct cpufreq_policy *policy,
134 unsigned int target_freq, unsigned int relation)
135{
136 unsigned int newstate = 0;
137 struct cpufreq_freqs freqs;
138 int rc;
139
140 if (cpufreq_frequency_table_target(policy, maple_cpu_freqs,
141 target_freq, relation, &newstate))
142 return -EINVAL;
143
144 if (maple_pmode_cur == newstate)
145 return 0;
146
147 mutex_lock(&maple_switch_mutex);
148
149 freqs.old = maple_cpu_freqs[maple_pmode_cur].frequency;
150 freqs.new = maple_cpu_freqs[newstate].frequency;
Dmitry Eremin-Solenikov5d8c6652011-06-29 05:07:56 +0000151
Viresh Kumarb43a7ff2013-03-24 11:56:43 +0530152 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
Dmitry Eremin-Solenikov5d8c6652011-06-29 05:07:56 +0000153 rc = maple_scom_switch_freq(newstate);
Viresh Kumarb43a7ff2013-03-24 11:56:43 +0530154 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
Dmitry Eremin-Solenikov5d8c6652011-06-29 05:07:56 +0000155
156 mutex_unlock(&maple_switch_mutex);
157
158 return rc;
159}
160
161static unsigned int maple_cpufreq_get_speed(unsigned int cpu)
162{
163 return maple_cpu_freqs[maple_pmode_cur].frequency;
164}
165
166static int maple_cpufreq_cpu_init(struct cpufreq_policy *policy)
167{
168 policy->cpuinfo.transition_latency = 12000;
169 policy->cur = maple_cpu_freqs[maple_scom_query_freq()].frequency;
170 /* secondary CPUs are tied to the primary one by the
171 * cpufreq core if in the secondary policy we tell it that
172 * it actually must be one policy together with all others. */
Viresh Kumar4c738d02013-02-01 06:40:01 +0000173 cpumask_setall(policy->cpus);
Dmitry Eremin-Solenikov5d8c6652011-06-29 05:07:56 +0000174
Viresh Kumar05b16212013-09-16 18:56:22 +0530175 return cpufreq_table_validate_and_show(policy, maple_cpu_freqs);
Dmitry Eremin-Solenikov5d8c6652011-06-29 05:07:56 +0000176}
177
178
179static struct cpufreq_driver maple_cpufreq_driver = {
180 .name = "maple",
Dmitry Eremin-Solenikov5d8c6652011-06-29 05:07:56 +0000181 .flags = CPUFREQ_CONST_LOOPS,
182 .init = maple_cpufreq_cpu_init,
Viresh Kumarb766b902013-10-03 20:28:12 +0530183 .verify = cpufreq_generic_frequency_table_verify,
Dmitry Eremin-Solenikov5d8c6652011-06-29 05:07:56 +0000184 .target = maple_cpufreq_target,
185 .get = maple_cpufreq_get_speed,
Viresh Kumarb766b902013-10-03 20:28:12 +0530186 .attr = cpufreq_generic_attr,
Dmitry Eremin-Solenikov5d8c6652011-06-29 05:07:56 +0000187};
188
189static int __init maple_cpufreq_init(void)
190{
Dmitry Eremin-Solenikov5d8c6652011-06-29 05:07:56 +0000191 struct device_node *cpunode;
192 unsigned int psize;
193 unsigned long max_freq;
194 const u32 *valp;
195 u32 pvr_hi;
196 int rc = -ENODEV;
197
198 /*
199 * Behave here like powermac driver which checks machine compatibility
200 * to ease merging of two drivers in future.
201 */
202 if (!of_machine_is_compatible("Momentum,Maple") &&
203 !of_machine_is_compatible("Momentum,Apache"))
204 return 0;
205
Dmitry Eremin-Solenikov5d8c6652011-06-29 05:07:56 +0000206 /* Get first CPU node */
Sudeep KarkadaNagesha2421d4c2013-07-17 12:39:29 +0100207 cpunode = of_cpu_device_node_get(0);
Dmitry Eremin-Solenikov5d8c6652011-06-29 05:07:56 +0000208 if (cpunode == NULL) {
209 printk(KERN_ERR "cpufreq: Can't find any CPU 0 node\n");
Sudeep KarkadaNagesha2421d4c2013-07-17 12:39:29 +0100210 goto bail_noprops;
Dmitry Eremin-Solenikov5d8c6652011-06-29 05:07:56 +0000211 }
212
213 /* Check 970FX for now */
214 /* we actually don't care on which CPU to access PVR */
215 pvr_hi = PVR_VER(mfspr(SPRN_PVR));
216 if (pvr_hi != 0x3c && pvr_hi != 0x44) {
217 printk(KERN_ERR "cpufreq: Unsupported CPU version (%x)\n",
218 pvr_hi);
219 goto bail_noprops;
220 }
221
222 /* Look for the powertune data in the device-tree */
223 /*
224 * On Maple this property is provided by PIBS in dual-processor config,
225 * not provided by PIBS in CPU0 config and also not provided by SLOF,
226 * so YMMV
227 */
228 maple_pmode_data = of_get_property(cpunode, "power-mode-data", &psize);
229 if (!maple_pmode_data) {
230 DBG("No power-mode-data !\n");
231 goto bail_noprops;
232 }
233 maple_pmode_max = psize / sizeof(u32) - 1;
234
235 /*
236 * From what I see, clock-frequency is always the maximal frequency.
237 * The current driver can not slew sysclk yet, so we really only deal
238 * with powertune steps for now. We also only implement full freq and
239 * half freq in this version. So far, I haven't yet seen a machine
240 * supporting anything else.
241 */
242 valp = of_get_property(cpunode, "clock-frequency", NULL);
243 if (!valp)
244 return -ENODEV;
245 max_freq = (*valp)/1000;
246 maple_cpu_freqs[0].frequency = max_freq;
247 maple_cpu_freqs[1].frequency = max_freq/2;
248
249 /* Force apply current frequency to make sure everything is in
250 * sync (voltage is right for example). Firmware may leave us with
251 * a strange setting ...
252 */
253 msleep(10);
254 maple_pmode_cur = -1;
255 maple_scom_switch_freq(maple_scom_query_freq());
256
257 printk(KERN_INFO "Registering Maple CPU frequency driver\n");
258 printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
259 maple_cpu_freqs[1].frequency/1000,
260 maple_cpu_freqs[0].frequency/1000,
261 maple_cpu_freqs[maple_pmode_cur].frequency/1000);
262
263 rc = cpufreq_register_driver(&maple_cpufreq_driver);
264
265 of_node_put(cpunode);
Dmitry Eremin-Solenikov5d8c6652011-06-29 05:07:56 +0000266
267 return rc;
268
269bail_noprops:
270 of_node_put(cpunode);
Dmitry Eremin-Solenikov5d8c6652011-06-29 05:07:56 +0000271
272 return rc;
273}
274
275module_init(maple_cpufreq_init);
276
277
278MODULE_LICENSE("GPL");