| GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 1 | /* |
| 2 | * PKUnity NAND Controller Registers |
| 3 | */ |
| 4 | /* |
| 5 | * ID Reg. 0 NAND_IDR0 |
| 6 | */ |
| GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 7 | #define NAND_IDR0 (PKUNITY_NAND_BASE + 0x0000) |
| GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 8 | /* |
| 9 | * ID Reg. 1 NAND_IDR1 |
| 10 | */ |
| GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 11 | #define NAND_IDR1 (PKUNITY_NAND_BASE + 0x0004) |
| GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 12 | /* |
| 13 | * ID Reg. 2 NAND_IDR2 |
| 14 | */ |
| GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 15 | #define NAND_IDR2 (PKUNITY_NAND_BASE + 0x0008) |
| GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 16 | /* |
| 17 | * ID Reg. 3 NAND_IDR3 |
| 18 | */ |
| GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 19 | #define NAND_IDR3 (PKUNITY_NAND_BASE + 0x000C) |
| GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 20 | /* |
| 21 | * Page Address Reg 0 NAND_PAR0 |
| 22 | */ |
| GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 23 | #define NAND_PAR0 (PKUNITY_NAND_BASE + 0x0010) |
| GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 24 | /* |
| 25 | * Page Address Reg 1 NAND_PAR1 |
| 26 | */ |
| GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 27 | #define NAND_PAR1 (PKUNITY_NAND_BASE + 0x0014) |
| GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 28 | /* |
| 29 | * Page Address Reg 2 NAND_PAR2 |
| 30 | */ |
| GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 31 | #define NAND_PAR2 (PKUNITY_NAND_BASE + 0x0018) |
| GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 32 | /* |
| 33 | * ECC Enable Reg NAND_ECCEN |
| 34 | */ |
| GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 35 | #define NAND_ECCEN (PKUNITY_NAND_BASE + 0x001C) |
| GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 36 | /* |
| 37 | * Buffer Reg NAND_BUF |
| 38 | */ |
| GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 39 | #define NAND_BUF (PKUNITY_NAND_BASE + 0x0020) |
| GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 40 | /* |
| 41 | * ECC Status Reg NAND_ECCSR |
| 42 | */ |
| GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 43 | #define NAND_ECCSR (PKUNITY_NAND_BASE + 0x0024) |
| GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 44 | /* |
| 45 | * Command Reg NAND_CMD |
| 46 | */ |
| GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 47 | #define NAND_CMD (PKUNITY_NAND_BASE + 0x0028) |
| GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 48 | /* |
| 49 | * DMA Configure Reg NAND_DMACR |
| 50 | */ |
| GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 51 | #define NAND_DMACR (PKUNITY_NAND_BASE + 0x002C) |
| GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 52 | /* |
| 53 | * Interrupt Reg NAND_IR |
| 54 | */ |
| GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 55 | #define NAND_IR (PKUNITY_NAND_BASE + 0x0030) |
| GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 56 | /* |
| 57 | * Interrupt Mask Reg NAND_IMR |
| 58 | */ |
| GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 59 | #define NAND_IMR (PKUNITY_NAND_BASE + 0x0034) |
| GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 60 | /* |
| 61 | * Chip Enable Reg NAND_CHIPEN |
| 62 | */ |
| GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 63 | #define NAND_CHIPEN (PKUNITY_NAND_BASE + 0x0038) |
| GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 64 | /* |
| 65 | * Address Reg NAND_ADDR |
| 66 | */ |
| GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 67 | #define NAND_ADDR (PKUNITY_NAND_BASE + 0x003C) |
| GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 68 | |
| 69 | /* |
| 70 | * Command bits NAND_CMD_CMD_MASK |
| 71 | */ |
| 72 | #define NAND_CMD_CMD_MASK FMASK(4, 4) |
| 73 | #define NAND_CMD_CMD_READPAGE FIELD(0x0, 4, 4) |
| 74 | #define NAND_CMD_CMD_ERASEBLOCK FIELD(0x6, 4, 4) |
| 75 | #define NAND_CMD_CMD_READSTATUS FIELD(0x7, 4, 4) |
| 76 | #define NAND_CMD_CMD_WRITEPAGE FIELD(0x8, 4, 4) |
| 77 | #define NAND_CMD_CMD_READID FIELD(0x9, 4, 4) |
| 78 | #define NAND_CMD_CMD_RESET FIELD(0xf, 4, 4) |
| 79 | |