GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 1 | /* |
| 2 | * PKUnity UNIGFX Registers |
| 3 | */ |
| 4 | |
| 5 | #define UDE_BASE (PKUNITY_UNIGFX_BASE + 0x1400) |
| 6 | #define UGE_BASE (PKUNITY_UNIGFX_BASE + 0x0000) |
| 7 | |
| 8 | /* |
| 9 | * command reg for UNIGFX DE |
| 10 | */ |
| 11 | /* |
| 12 | * control reg UDE_CFG |
| 13 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 14 | #define UDE_CFG (UDE_BASE + 0x0000) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 15 | /* |
| 16 | * framebuffer start address reg UDE_FSA |
| 17 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 18 | #define UDE_FSA (UDE_BASE + 0x0004) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 19 | /* |
| 20 | * line size reg UDE_LS |
| 21 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 22 | #define UDE_LS (UDE_BASE + 0x0008) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 23 | /* |
| 24 | * pitch size reg UDE_PS |
| 25 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 26 | #define UDE_PS (UDE_BASE + 0x000C) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 27 | /* |
| 28 | * horizontal active time reg UDE_HAT |
| 29 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 30 | #define UDE_HAT (UDE_BASE + 0x0010) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 31 | /* |
| 32 | * horizontal blank time reg UDE_HBT |
| 33 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 34 | #define UDE_HBT (UDE_BASE + 0x0014) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 35 | /* |
| 36 | * horizontal sync time reg UDE_HST |
| 37 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 38 | #define UDE_HST (UDE_BASE + 0x0018) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 39 | /* |
| 40 | * vertival active time reg UDE_VAT |
| 41 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 42 | #define UDE_VAT (UDE_BASE + 0x001C) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 43 | /* |
| 44 | * vertival blank time reg UDE_VBT |
| 45 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 46 | #define UDE_VBT (UDE_BASE + 0x0020) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 47 | /* |
| 48 | * vertival sync time reg UDE_VST |
| 49 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 50 | #define UDE_VST (UDE_BASE + 0x0024) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 51 | /* |
| 52 | * cursor position UDE_CXY |
| 53 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 54 | #define UDE_CXY (UDE_BASE + 0x0028) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 55 | /* |
| 56 | * cursor front color UDE_CC0 |
| 57 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 58 | #define UDE_CC0 (UDE_BASE + 0x002C) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 59 | /* |
| 60 | * cursor background color UDE_CC1 |
| 61 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 62 | #define UDE_CC1 (UDE_BASE + 0x0030) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 63 | /* |
| 64 | * video position UDE_VXY |
| 65 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 66 | #define UDE_VXY (UDE_BASE + 0x0034) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 67 | /* |
| 68 | * video start address reg UDE_VSA |
| 69 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 70 | #define UDE_VSA (UDE_BASE + 0x0040) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 71 | /* |
| 72 | * video size reg UDE_VS |
| 73 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 74 | #define UDE_VS (UDE_BASE + 0x004C) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 75 | |
| 76 | /* |
| 77 | * command reg for UNIGFX GE |
| 78 | */ |
| 79 | /* |
| 80 | * src xy reg UGE_SRCXY |
| 81 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 82 | #define UGE_SRCXY (UGE_BASE + 0x0000) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 83 | /* |
| 84 | * dst xy reg UGE_DSTXY |
| 85 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 86 | #define UGE_DSTXY (UGE_BASE + 0x0004) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 87 | /* |
| 88 | * pitch reg UGE_PITCH |
| 89 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 90 | #define UGE_PITCH (UGE_BASE + 0x0008) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 91 | /* |
| 92 | * src start reg UGE_SRCSTART |
| 93 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 94 | #define UGE_SRCSTART (UGE_BASE + 0x000C) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 95 | /* |
| 96 | * dst start reg UGE_DSTSTART |
| 97 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 98 | #define UGE_DSTSTART (UGE_BASE + 0x0010) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 99 | /* |
| 100 | * width height reg UGE_WIDHEIGHT |
| 101 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 102 | #define UGE_WIDHEIGHT (UGE_BASE + 0x0014) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 103 | /* |
| 104 | * rop alpah reg UGE_ROPALPHA |
| 105 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 106 | #define UGE_ROPALPHA (UGE_BASE + 0x0018) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 107 | /* |
| 108 | * front color UGE_FCOLOR |
| 109 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 110 | #define UGE_FCOLOR (UGE_BASE + 0x001C) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 111 | /* |
| 112 | * background color UGE_BCOLOR |
| 113 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 114 | #define UGE_BCOLOR (UGE_BASE + 0x0020) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 115 | /* |
| 116 | * src color key for high value UGE_SCH |
| 117 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 118 | #define UGE_SCH (UGE_BASE + 0x0024) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 119 | /* |
| 120 | * dst color key for high value UGE_DCH |
| 121 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 122 | #define UGE_DCH (UGE_BASE + 0x0028) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 123 | /* |
| 124 | * src color key for low value UGE_SCL |
| 125 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 126 | #define UGE_SCL (UGE_BASE + 0x002C) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 127 | /* |
| 128 | * dst color key for low value UGE_DCL |
| 129 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 130 | #define UGE_DCL (UGE_BASE + 0x0030) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 131 | /* |
| 132 | * clip 0 reg UGE_CLIP0 |
| 133 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 134 | #define UGE_CLIP0 (UGE_BASE + 0x0034) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 135 | /* |
| 136 | * clip 1 reg UGE_CLIP1 |
| 137 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 138 | #define UGE_CLIP1 (UGE_BASE + 0x0038) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 139 | /* |
| 140 | * command reg UGE_COMMAND |
| 141 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 142 | #define UGE_COMMAND (UGE_BASE + 0x003C) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 143 | /* |
| 144 | * pattern 0 UGE_P0 |
| 145 | */ |
GuanXuetao | 1cf46c4 | 2011-03-04 18:07:48 +0800 | [diff] [blame] | 146 | #define UGE_P0 (UGE_BASE + 0x0040) |
| 147 | #define UGE_P1 (UGE_BASE + 0x0044) |
| 148 | #define UGE_P2 (UGE_BASE + 0x0048) |
| 149 | #define UGE_P3 (UGE_BASE + 0x004C) |
| 150 | #define UGE_P4 (UGE_BASE + 0x0050) |
| 151 | #define UGE_P5 (UGE_BASE + 0x0054) |
| 152 | #define UGE_P6 (UGE_BASE + 0x0058) |
| 153 | #define UGE_P7 (UGE_BASE + 0x005C) |
| 154 | #define UGE_P8 (UGE_BASE + 0x0060) |
| 155 | #define UGE_P9 (UGE_BASE + 0x0064) |
| 156 | #define UGE_P10 (UGE_BASE + 0x0068) |
| 157 | #define UGE_P11 (UGE_BASE + 0x006C) |
| 158 | #define UGE_P12 (UGE_BASE + 0x0070) |
| 159 | #define UGE_P13 (UGE_BASE + 0x0074) |
| 160 | #define UGE_P14 (UGE_BASE + 0x0078) |
| 161 | #define UGE_P15 (UGE_BASE + 0x007C) |
| 162 | #define UGE_P16 (UGE_BASE + 0x0080) |
| 163 | #define UGE_P17 (UGE_BASE + 0x0084) |
| 164 | #define UGE_P18 (UGE_BASE + 0x0088) |
| 165 | #define UGE_P19 (UGE_BASE + 0x008C) |
| 166 | #define UGE_P20 (UGE_BASE + 0x0090) |
| 167 | #define UGE_P21 (UGE_BASE + 0x0094) |
| 168 | #define UGE_P22 (UGE_BASE + 0x0098) |
| 169 | #define UGE_P23 (UGE_BASE + 0x009C) |
| 170 | #define UGE_P24 (UGE_BASE + 0x00A0) |
| 171 | #define UGE_P25 (UGE_BASE + 0x00A4) |
| 172 | #define UGE_P26 (UGE_BASE + 0x00A8) |
| 173 | #define UGE_P27 (UGE_BASE + 0x00AC) |
| 174 | #define UGE_P28 (UGE_BASE + 0x00B0) |
| 175 | #define UGE_P29 (UGE_BASE + 0x00B4) |
| 176 | #define UGE_P30 (UGE_BASE + 0x00B8) |
| 177 | #define UGE_P31 (UGE_BASE + 0x00BC) |
GuanXuetao | b08b4f8 | 2011-02-26 20:08:36 +0800 | [diff] [blame] | 178 | |
| 179 | #define UDE_CFG_DST_MASK FMASK(2, 8) |
| 180 | #define UDE_CFG_DST8 FIELD(0x0, 2, 8) |
| 181 | #define UDE_CFG_DST16 FIELD(0x1, 2, 8) |
| 182 | #define UDE_CFG_DST24 FIELD(0x2, 2, 8) |
| 183 | #define UDE_CFG_DST32 FIELD(0x3, 2, 8) |
| 184 | |
| 185 | /* |
| 186 | * GDEN enable UDE_CFG_GDEN_ENABLE |
| 187 | */ |
| 188 | #define UDE_CFG_GDEN_ENABLE FIELD(1, 1, 3) |
| 189 | /* |
| 190 | * VDEN enable UDE_CFG_VDEN_ENABLE |
| 191 | */ |
| 192 | #define UDE_CFG_VDEN_ENABLE FIELD(1, 1, 4) |
| 193 | /* |
| 194 | * CDEN enable UDE_CFG_CDEN_ENABLE |
| 195 | */ |
| 196 | #define UDE_CFG_CDEN_ENABLE FIELD(1, 1, 5) |
| 197 | /* |
| 198 | * TIMEUP enable UDE_CFG_TIMEUP_ENABLE |
| 199 | */ |
| 200 | #define UDE_CFG_TIMEUP_ENABLE FIELD(1, 1, 6) |