Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 1 | /* |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 2 | * arch/arm/plat-omap/include/plat/dmtimer.h |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 3 | * |
| 4 | * OMAP Dual-Mode Timers |
| 5 | * |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 6 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ |
| 7 | * Tarun Kanti DebBarma <tarun.kanti@ti.com> |
| 8 | * Thara Gopinath <thara@ti.com> |
| 9 | * |
| 10 | * Platform device conversion and hwmod support. |
| 11 | * |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 12 | * Copyright (C) 2005 Nokia Corporation |
| 13 | * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com> |
| 14 | * PWM and clock framwork support by Timo Teras. |
| 15 | * |
| 16 | * This program is free software; you can redistribute it and/or modify it |
| 17 | * under the terms of the GNU General Public License as published by the |
| 18 | * Free Software Foundation; either version 2 of the License, or (at your |
| 19 | * option) any later version. |
| 20 | * |
| 21 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 22 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 23 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 24 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 25 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 28 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 29 | * |
| 30 | * You should have received a copy of the GNU General Public License along |
| 31 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 32 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 33 | */ |
| 34 | |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 35 | #include <linux/clk.h> |
| 36 | #include <linux/delay.h> |
Paul Walmsley | a7cd4b08 | 2011-07-09 18:00:25 -0600 | [diff] [blame] | 37 | #include <linux/io.h> |
Tarun Kanti DebBarma | 97933d6 | 2011-09-20 17:00:17 +0530 | [diff] [blame] | 38 | #include <linux/platform_device.h> |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 39 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 40 | #ifndef __ASM_ARCH_DMTIMER_H |
| 41 | #define __ASM_ARCH_DMTIMER_H |
| 42 | |
| 43 | /* clock sources */ |
| 44 | #define OMAP_TIMER_SRC_SYS_CLK 0x00 |
| 45 | #define OMAP_TIMER_SRC_32_KHZ 0x01 |
| 46 | #define OMAP_TIMER_SRC_EXT_CLK 0x02 |
| 47 | |
| 48 | /* timer interrupt enable bits */ |
| 49 | #define OMAP_TIMER_INT_CAPTURE (1 << 2) |
| 50 | #define OMAP_TIMER_INT_OVERFLOW (1 << 1) |
| 51 | #define OMAP_TIMER_INT_MATCH (1 << 0) |
| 52 | |
| 53 | /* trigger types */ |
| 54 | #define OMAP_TIMER_TRIGGER_NONE 0x00 |
| 55 | #define OMAP_TIMER_TRIGGER_OVERFLOW 0x01 |
| 56 | #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 |
| 57 | |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 58 | /* |
| 59 | * IP revision identifier so that Highlander IP |
| 60 | * in OMAP4 can be distinguished. |
| 61 | */ |
| 62 | #define OMAP_TIMER_IP_VERSION_1 0x1 |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 63 | |
| 64 | /* timer capabilities used in hwmod database */ |
| 65 | #define OMAP_TIMER_SECURE 0x80000000 |
| 66 | #define OMAP_TIMER_ALWON 0x40000000 |
| 67 | #define OMAP_TIMER_HAS_PWM 0x20000000 |
| 68 | |
| 69 | struct omap_timer_capability_dev_attr { |
| 70 | u32 timer_capability; |
| 71 | }; |
| 72 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 73 | struct omap_dm_timer; |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 74 | |
Tarun Kanti DebBarma | b481113 | 2011-09-20 17:00:24 +0530 | [diff] [blame] | 75 | struct timer_regs { |
| 76 | u32 tidr; |
Tarun Kanti DebBarma | b481113 | 2011-09-20 17:00:24 +0530 | [diff] [blame] | 77 | u32 tistat; |
| 78 | u32 tisr; |
| 79 | u32 tier; |
| 80 | u32 twer; |
| 81 | u32 tclr; |
| 82 | u32 tcrr; |
| 83 | u32 tldr; |
| 84 | u32 ttrg; |
| 85 | u32 twps; |
| 86 | u32 tmar; |
| 87 | u32 tcar1; |
| 88 | u32 tsicr; |
| 89 | u32 tcar2; |
| 90 | u32 tpir; |
| 91 | u32 tnir; |
| 92 | u32 tcvr; |
| 93 | u32 tocr; |
| 94 | u32 towr; |
| 95 | }; |
| 96 | |
Tarun Kanti DebBarma | 97933d6 | 2011-09-20 17:00:17 +0530 | [diff] [blame] | 97 | struct dmtimer_platform_data { |
| 98 | int (*set_timer_src)(struct platform_device *pdev, int source); |
| 99 | int timer_ip_version; |
| 100 | u32 needs_manual_reset:1; |
Tarun Kanti DebBarma | b481113 | 2011-09-20 17:00:24 +0530 | [diff] [blame] | 101 | bool loses_context; |
| 102 | |
Tomi Valkeinen | fc01387 | 2011-06-09 16:56:23 +0300 | [diff] [blame] | 103 | int (*get_context_loss_count)(struct device *dev); |
Tarun Kanti DebBarma | 97933d6 | 2011-09-20 17:00:17 +0530 | [diff] [blame] | 104 | }; |
| 105 | |
Jon Hunter | b7b4ff7 | 2012-06-05 12:34:51 -0500 | [diff] [blame^] | 106 | int omap_dm_timer_reserve_systimer(int id); |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 107 | struct omap_dm_timer *omap_dm_timer_request(void); |
| 108 | struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id); |
Tarun Kanti DebBarma | ab4eb8b | 2011-09-20 17:00:26 +0530 | [diff] [blame] | 109 | int omap_dm_timer_free(struct omap_dm_timer *timer); |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 110 | void omap_dm_timer_enable(struct omap_dm_timer *timer); |
| 111 | void omap_dm_timer_disable(struct omap_dm_timer *timer); |
| 112 | |
| 113 | int omap_dm_timer_get_irq(struct omap_dm_timer *timer); |
| 114 | |
| 115 | u32 omap_dm_timer_modify_idlect_mask(u32 inputmask); |
| 116 | struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer); |
| 117 | |
Tarun Kanti DebBarma | ab4eb8b | 2011-09-20 17:00:26 +0530 | [diff] [blame] | 118 | int omap_dm_timer_trigger(struct omap_dm_timer *timer); |
| 119 | int omap_dm_timer_start(struct omap_dm_timer *timer); |
| 120 | int omap_dm_timer_stop(struct omap_dm_timer *timer); |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 121 | |
Paul Walmsley | f248076 | 2009-04-23 21:11:10 -0600 | [diff] [blame] | 122 | int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source); |
Tarun Kanti DebBarma | ab4eb8b | 2011-09-20 17:00:26 +0530 | [diff] [blame] | 123 | int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value); |
| 124 | int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value); |
| 125 | int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match); |
| 126 | int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger); |
| 127 | int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler); |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 128 | |
Tarun Kanti DebBarma | ab4eb8b | 2011-09-20 17:00:26 +0530 | [diff] [blame] | 129 | int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value); |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 130 | |
| 131 | unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer); |
Tarun Kanti DebBarma | ab4eb8b | 2011-09-20 17:00:26 +0530 | [diff] [blame] | 132 | int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value); |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 133 | unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer); |
Tarun Kanti DebBarma | ab4eb8b | 2011-09-20 17:00:26 +0530 | [diff] [blame] | 134 | int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value); |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 135 | |
| 136 | int omap_dm_timers_active(void); |
| 137 | |
Tony Lindgren | ec97489 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 138 | /* |
| 139 | * Do not use the defines below, they are not needed. They should be only |
| 140 | * used by dmtimer.c and sys_timer related code. |
| 141 | */ |
| 142 | |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 143 | /* |
| 144 | * The interrupt registers are different between v1 and v2 ip. |
| 145 | * These registers are offsets from timer->iobase. |
| 146 | */ |
| 147 | #define OMAP_TIMER_ID_OFFSET 0x00 |
| 148 | #define OMAP_TIMER_OCP_CFG_OFFSET 0x10 |
| 149 | |
| 150 | #define OMAP_TIMER_V1_SYS_STAT_OFFSET 0x14 |
| 151 | #define OMAP_TIMER_V1_STAT_OFFSET 0x18 |
| 152 | #define OMAP_TIMER_V1_INT_EN_OFFSET 0x1c |
| 153 | |
| 154 | #define OMAP_TIMER_V2_IRQSTATUS_RAW 0x24 |
| 155 | #define OMAP_TIMER_V2_IRQSTATUS 0x28 |
| 156 | #define OMAP_TIMER_V2_IRQENABLE_SET 0x2c |
| 157 | #define OMAP_TIMER_V2_IRQENABLE_CLR 0x30 |
| 158 | |
| 159 | /* |
| 160 | * The functional registers have a different base on v1 and v2 ip. |
| 161 | * These registers are offsets from timer->func_base. The func_base |
| 162 | * is samae as io_base for v1 and io_base + 0x14 for v2 ip. |
| 163 | * |
| 164 | */ |
| 165 | #define OMAP_TIMER_V2_FUNC_OFFSET 0x14 |
| 166 | |
Tony Lindgren | ec97489 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 167 | #define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20 |
| 168 | #define _OMAP_TIMER_CTRL_OFFSET 0x24 |
| 169 | #define OMAP_TIMER_CTRL_GPOCFG (1 << 14) |
| 170 | #define OMAP_TIMER_CTRL_CAPTMODE (1 << 13) |
| 171 | #define OMAP_TIMER_CTRL_PT (1 << 12) |
| 172 | #define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8) |
| 173 | #define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8) |
| 174 | #define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8) |
| 175 | #define OMAP_TIMER_CTRL_SCPWM (1 << 7) |
| 176 | #define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */ |
| 177 | #define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */ |
| 178 | #define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */ |
| 179 | #define OMAP_TIMER_CTRL_POSTED (1 << 2) |
| 180 | #define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */ |
| 181 | #define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */ |
| 182 | #define _OMAP_TIMER_COUNTER_OFFSET 0x28 |
| 183 | #define _OMAP_TIMER_LOAD_OFFSET 0x2c |
| 184 | #define _OMAP_TIMER_TRIGGER_OFFSET 0x30 |
| 185 | #define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34 |
| 186 | #define WP_NONE 0 /* no write pending bit */ |
| 187 | #define WP_TCLR (1 << 0) |
| 188 | #define WP_TCRR (1 << 1) |
| 189 | #define WP_TLDR (1 << 2) |
| 190 | #define WP_TTGR (1 << 3) |
| 191 | #define WP_TMAR (1 << 4) |
| 192 | #define WP_TPIR (1 << 5) |
| 193 | #define WP_TNIR (1 << 6) |
| 194 | #define WP_TCVR (1 << 7) |
| 195 | #define WP_TOCR (1 << 8) |
| 196 | #define WP_TOWR (1 << 9) |
| 197 | #define _OMAP_TIMER_MATCH_OFFSET 0x38 |
| 198 | #define _OMAP_TIMER_CAPTURE_OFFSET 0x3c |
| 199 | #define _OMAP_TIMER_IF_CTRL_OFFSET 0x40 |
| 200 | #define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */ |
| 201 | #define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */ |
| 202 | #define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */ |
| 203 | #define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */ |
| 204 | #define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */ |
| 205 | #define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */ |
| 206 | |
| 207 | /* register offsets with the write pending bit encoded */ |
| 208 | #define WPSHIFT 16 |
| 209 | |
Tony Lindgren | ec97489 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 210 | #define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \ |
| 211 | | (WP_NONE << WPSHIFT)) |
| 212 | |
| 213 | #define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \ |
| 214 | | (WP_TCLR << WPSHIFT)) |
| 215 | |
| 216 | #define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \ |
| 217 | | (WP_TCRR << WPSHIFT)) |
| 218 | |
| 219 | #define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \ |
| 220 | | (WP_TLDR << WPSHIFT)) |
| 221 | |
| 222 | #define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \ |
| 223 | | (WP_TTGR << WPSHIFT)) |
| 224 | |
| 225 | #define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \ |
| 226 | | (WP_NONE << WPSHIFT)) |
| 227 | |
| 228 | #define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \ |
| 229 | | (WP_TMAR << WPSHIFT)) |
| 230 | |
| 231 | #define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \ |
| 232 | | (WP_NONE << WPSHIFT)) |
| 233 | |
| 234 | #define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \ |
| 235 | | (WP_NONE << WPSHIFT)) |
| 236 | |
| 237 | #define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \ |
| 238 | | (WP_NONE << WPSHIFT)) |
| 239 | |
| 240 | #define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \ |
| 241 | | (WP_TPIR << WPSHIFT)) |
| 242 | |
| 243 | #define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \ |
| 244 | | (WP_TNIR << WPSHIFT)) |
| 245 | |
| 246 | #define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \ |
| 247 | | (WP_TCVR << WPSHIFT)) |
| 248 | |
| 249 | #define OMAP_TIMER_TICK_INT_MASK_SET_REG \ |
| 250 | (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT)) |
| 251 | |
| 252 | #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \ |
| 253 | (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT)) |
| 254 | |
| 255 | struct omap_dm_timer { |
| 256 | unsigned long phys_base; |
Tarun Kanti DebBarma | df28472 | 2011-09-20 17:00:19 +0530 | [diff] [blame] | 257 | int id; |
Tony Lindgren | ec97489 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 258 | int irq; |
Tarun Kanti DebBarma | f1bbbb1 | 2012-05-07 23:55:30 -0600 | [diff] [blame] | 259 | struct clk *fclk; |
Tarun Kanti DebBarma | 3392cdd | 2011-09-20 17:00:20 +0530 | [diff] [blame] | 260 | |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 261 | void __iomem *io_base; |
| 262 | void __iomem *sys_stat; /* TISTAT timer status */ |
| 263 | void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */ |
| 264 | void __iomem *irq_ena; /* irq enable */ |
| 265 | void __iomem *irq_dis; /* irq disable, only on v2 ip */ |
| 266 | void __iomem *pend; /* write pending */ |
| 267 | void __iomem *func_base; /* function register base */ |
| 268 | |
Tony Lindgren | aa56188 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 269 | unsigned long rate; |
Tony Lindgren | ec97489 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 270 | unsigned reserved:1; |
Tony Lindgren | ec97489 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 271 | unsigned posted:1; |
Tarun Kanti DebBarma | b481113 | 2011-09-20 17:00:24 +0530 | [diff] [blame] | 272 | struct timer_regs context; |
| 273 | bool loses_context; |
| 274 | int ctx_loss_count; |
| 275 | int revision; |
Tarun Kanti DebBarma | 97933d6 | 2011-09-20 17:00:17 +0530 | [diff] [blame] | 276 | struct platform_device *pdev; |
Tarun Kanti DebBarma | df28472 | 2011-09-20 17:00:19 +0530 | [diff] [blame] | 277 | struct list_head node; |
Tarun Kanti DebBarma | b481113 | 2011-09-20 17:00:24 +0530 | [diff] [blame] | 278 | |
Tomi Valkeinen | fc01387 | 2011-06-09 16:56:23 +0300 | [diff] [blame] | 279 | int (*get_context_loss_count)(struct device *dev); |
Tony Lindgren | ec97489 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 280 | }; |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 281 | |
Tarun Kanti DebBarma | 3392cdd | 2011-09-20 17:00:20 +0530 | [diff] [blame] | 282 | int omap_dm_timer_prepare(struct omap_dm_timer *timer); |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 283 | |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 284 | static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg, |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 285 | int posted) |
| 286 | { |
| 287 | if (posted) |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 288 | while (__raw_readl(timer->pend) & (reg >> WPSHIFT)) |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 289 | cpu_relax(); |
| 290 | |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 291 | return __raw_readl(timer->func_base + (reg & 0xff)); |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 292 | } |
| 293 | |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 294 | static inline void __omap_dm_timer_write(struct omap_dm_timer *timer, |
| 295 | u32 reg, u32 val, int posted) |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 296 | { |
| 297 | if (posted) |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 298 | while (__raw_readl(timer->pend) & (reg >> WPSHIFT)) |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 299 | cpu_relax(); |
| 300 | |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 301 | __raw_writel(val, timer->func_base + (reg & 0xff)); |
| 302 | } |
| 303 | |
| 304 | static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer) |
| 305 | { |
| 306 | u32 tidr; |
| 307 | |
| 308 | /* Assume v1 ip if bits [31:16] are zero */ |
| 309 | tidr = __raw_readl(timer->io_base); |
| 310 | if (!(tidr >> 16)) { |
Tarun Kanti DebBarma | b481113 | 2011-09-20 17:00:24 +0530 | [diff] [blame] | 311 | timer->revision = 1; |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 312 | timer->sys_stat = timer->io_base + |
| 313 | OMAP_TIMER_V1_SYS_STAT_OFFSET; |
| 314 | timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET; |
| 315 | timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET; |
Paul Walmsley | a7022d6 | 2012-04-13 06:34:28 -0600 | [diff] [blame] | 316 | timer->irq_dis = NULL; |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 317 | timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET; |
| 318 | timer->func_base = timer->io_base; |
| 319 | } else { |
Tarun Kanti DebBarma | b481113 | 2011-09-20 17:00:24 +0530 | [diff] [blame] | 320 | timer->revision = 2; |
Paul Walmsley | a7022d6 | 2012-04-13 06:34:28 -0600 | [diff] [blame] | 321 | timer->sys_stat = NULL; |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 322 | timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS; |
| 323 | timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET; |
| 324 | timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR; |
| 325 | timer->pend = timer->io_base + |
| 326 | _OMAP_TIMER_WRITE_PEND_OFFSET + |
| 327 | OMAP_TIMER_V2_FUNC_OFFSET; |
| 328 | timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET; |
| 329 | } |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 330 | } |
| 331 | |
| 332 | /* Assumes the source clock has been set by caller */ |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 333 | static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer, |
| 334 | int autoidle, int wakeup) |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 335 | { |
| 336 | u32 l; |
| 337 | |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 338 | l = __raw_readl(timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET); |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 339 | l |= 0x02 << 3; /* Set to smart-idle mode */ |
| 340 | l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */ |
| 341 | |
| 342 | if (autoidle) |
| 343 | l |= 0x1 << 0; |
| 344 | |
| 345 | if (wakeup) |
| 346 | l |= 1 << 2; |
| 347 | |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 348 | __raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET); |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 349 | |
| 350 | /* Match hardware reset default of posted mode */ |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 351 | __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 352 | OMAP_TIMER_CTRL_POSTED, 0); |
| 353 | } |
| 354 | |
| 355 | static inline int __omap_dm_timer_set_source(struct clk *timer_fck, |
| 356 | struct clk *parent) |
| 357 | { |
| 358 | int ret; |
| 359 | |
| 360 | clk_disable(timer_fck); |
| 361 | ret = clk_set_parent(timer_fck, parent); |
| 362 | clk_enable(timer_fck); |
| 363 | |
| 364 | /* |
| 365 | * When the functional clock disappears, too quick writes seem |
| 366 | * to cause an abort. XXX Is this still necessary? |
| 367 | */ |
| 368 | __delay(300000); |
| 369 | |
| 370 | return ret; |
| 371 | } |
| 372 | |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 373 | static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer, |
| 374 | int posted, unsigned long rate) |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 375 | { |
| 376 | u32 l; |
| 377 | |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 378 | l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted); |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 379 | if (l & OMAP_TIMER_CTRL_ST) { |
| 380 | l &= ~0x1; |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 381 | __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted); |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 382 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| 383 | /* Readback to make sure write has completed */ |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 384 | __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted); |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 385 | /* |
| 386 | * Wait for functional clock period x 3.5 to make sure that |
| 387 | * timer is stopped |
| 388 | */ |
| 389 | udelay(3500000 / rate + 1); |
| 390 | #endif |
| 391 | } |
| 392 | |
| 393 | /* Ack possibly pending interrupt */ |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 394 | __raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat); |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 395 | } |
| 396 | |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 397 | static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer, |
| 398 | u32 ctrl, unsigned int load, |
| 399 | int posted) |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 400 | { |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 401 | __omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted); |
| 402 | __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted); |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 403 | } |
| 404 | |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 405 | static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer, |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 406 | unsigned int value) |
| 407 | { |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 408 | __raw_writel(value, timer->irq_ena); |
| 409 | __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0); |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 410 | } |
| 411 | |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 412 | static inline unsigned int |
| 413 | __omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted) |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 414 | { |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 415 | return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted); |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 416 | } |
| 417 | |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 418 | static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer, |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 419 | unsigned int value) |
| 420 | { |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 421 | __raw_writel(value, timer->irq_stat); |
Tony Lindgren | caf64f2 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 422 | } |
| 423 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 424 | #endif /* __ASM_ARCH_DMTIMER_H */ |