blob: 1e5ce5d5624098e0819d9937f57232e3a0270993 [file] [log] [blame]
Russell Kinga09e64f2008-08-05 16:14:15 +01001/*
Tarun Kanti DebBarmac345c8b2011-09-20 17:00:18 +05302 * arch/arm/plat-omap/include/plat/dmtimer.h
Russell Kinga09e64f2008-08-05 16:14:15 +01003 *
4 * OMAP Dual-Mode Timers
5 *
Thara Gopinatheddb1262011-02-23 00:14:04 -07006 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7 * Tarun Kanti DebBarma <tarun.kanti@ti.com>
8 * Thara Gopinath <thara@ti.com>
9 *
10 * Platform device conversion and hwmod support.
11 *
Russell Kinga09e64f2008-08-05 16:14:15 +010012 * Copyright (C) 2005 Nokia Corporation
13 * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
14 * PWM and clock framwork support by Timo Teras.
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * You should have received a copy of the GNU General Public License along
31 * with this program; if not, write to the Free Software Foundation, Inc.,
32 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 */
34
Tony Lindgrencaf64f22011-03-29 15:54:48 -070035#include <linux/clk.h>
36#include <linux/delay.h>
Paul Walmsleya7cd4b082011-07-09 18:00:25 -060037#include <linux/io.h>
Tarun Kanti DebBarma97933d62011-09-20 17:00:17 +053038#include <linux/platform_device.h>
Tony Lindgrencaf64f22011-03-29 15:54:48 -070039
Russell Kinga09e64f2008-08-05 16:14:15 +010040#ifndef __ASM_ARCH_DMTIMER_H
41#define __ASM_ARCH_DMTIMER_H
42
43/* clock sources */
44#define OMAP_TIMER_SRC_SYS_CLK 0x00
45#define OMAP_TIMER_SRC_32_KHZ 0x01
46#define OMAP_TIMER_SRC_EXT_CLK 0x02
47
48/* timer interrupt enable bits */
49#define OMAP_TIMER_INT_CAPTURE (1 << 2)
50#define OMAP_TIMER_INT_OVERFLOW (1 << 1)
51#define OMAP_TIMER_INT_MATCH (1 << 0)
52
53/* trigger types */
54#define OMAP_TIMER_TRIGGER_NONE 0x00
55#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
56#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
57
Thara Gopinatheddb1262011-02-23 00:14:04 -070058/*
59 * IP revision identifier so that Highlander IP
60 * in OMAP4 can be distinguished.
61 */
62#define OMAP_TIMER_IP_VERSION_1 0x1
Tarun Kanti DebBarmac345c8b2011-09-20 17:00:18 +053063
64/* timer capabilities used in hwmod database */
65#define OMAP_TIMER_SECURE 0x80000000
66#define OMAP_TIMER_ALWON 0x40000000
67#define OMAP_TIMER_HAS_PWM 0x20000000
68
69struct omap_timer_capability_dev_attr {
70 u32 timer_capability;
71};
72
Russell Kinga09e64f2008-08-05 16:14:15 +010073struct omap_dm_timer;
Russell Kinga09e64f2008-08-05 16:14:15 +010074
Tarun Kanti DebBarmab4811132011-09-20 17:00:24 +053075struct timer_regs {
76 u32 tidr;
Tarun Kanti DebBarmab4811132011-09-20 17:00:24 +053077 u32 tistat;
78 u32 tisr;
79 u32 tier;
80 u32 twer;
81 u32 tclr;
82 u32 tcrr;
83 u32 tldr;
84 u32 ttrg;
85 u32 twps;
86 u32 tmar;
87 u32 tcar1;
88 u32 tsicr;
89 u32 tcar2;
90 u32 tpir;
91 u32 tnir;
92 u32 tcvr;
93 u32 tocr;
94 u32 towr;
95};
96
Tarun Kanti DebBarma97933d62011-09-20 17:00:17 +053097struct dmtimer_platform_data {
98 int (*set_timer_src)(struct platform_device *pdev, int source);
99 int timer_ip_version;
100 u32 needs_manual_reset:1;
Tarun Kanti DebBarmab4811132011-09-20 17:00:24 +0530101 bool loses_context;
102
Tomi Valkeinenfc013872011-06-09 16:56:23 +0300103 int (*get_context_loss_count)(struct device *dev);
Tarun Kanti DebBarma97933d62011-09-20 17:00:17 +0530104};
105
Jon Hunterb7b4ff72012-06-05 12:34:51 -0500106int omap_dm_timer_reserve_systimer(int id);
Russell Kinga09e64f2008-08-05 16:14:15 +0100107struct omap_dm_timer *omap_dm_timer_request(void);
108struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
Tarun Kanti DebBarmaab4eb8b2011-09-20 17:00:26 +0530109int omap_dm_timer_free(struct omap_dm_timer *timer);
Russell Kinga09e64f2008-08-05 16:14:15 +0100110void omap_dm_timer_enable(struct omap_dm_timer *timer);
111void omap_dm_timer_disable(struct omap_dm_timer *timer);
112
113int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
114
115u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
116struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
117
Tarun Kanti DebBarmaab4eb8b2011-09-20 17:00:26 +0530118int omap_dm_timer_trigger(struct omap_dm_timer *timer);
119int omap_dm_timer_start(struct omap_dm_timer *timer);
120int omap_dm_timer_stop(struct omap_dm_timer *timer);
Russell Kinga09e64f2008-08-05 16:14:15 +0100121
Paul Walmsleyf2480762009-04-23 21:11:10 -0600122int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
Tarun Kanti DebBarmaab4eb8b2011-09-20 17:00:26 +0530123int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
124int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
125int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
126int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
127int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
Russell Kinga09e64f2008-08-05 16:14:15 +0100128
Tarun Kanti DebBarmaab4eb8b2011-09-20 17:00:26 +0530129int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
Russell Kinga09e64f2008-08-05 16:14:15 +0100130
131unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
Tarun Kanti DebBarmaab4eb8b2011-09-20 17:00:26 +0530132int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
Russell Kinga09e64f2008-08-05 16:14:15 +0100133unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
Tarun Kanti DebBarmaab4eb8b2011-09-20 17:00:26 +0530134int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
Russell Kinga09e64f2008-08-05 16:14:15 +0100135
136int omap_dm_timers_active(void);
137
Tony Lindgrenec974892011-03-29 15:54:48 -0700138/*
139 * Do not use the defines below, they are not needed. They should be only
140 * used by dmtimer.c and sys_timer related code.
141 */
142
Tony Lindgrenee17f112011-09-16 15:44:20 -0700143/*
144 * The interrupt registers are different between v1 and v2 ip.
145 * These registers are offsets from timer->iobase.
146 */
147#define OMAP_TIMER_ID_OFFSET 0x00
148#define OMAP_TIMER_OCP_CFG_OFFSET 0x10
149
150#define OMAP_TIMER_V1_SYS_STAT_OFFSET 0x14
151#define OMAP_TIMER_V1_STAT_OFFSET 0x18
152#define OMAP_TIMER_V1_INT_EN_OFFSET 0x1c
153
154#define OMAP_TIMER_V2_IRQSTATUS_RAW 0x24
155#define OMAP_TIMER_V2_IRQSTATUS 0x28
156#define OMAP_TIMER_V2_IRQENABLE_SET 0x2c
157#define OMAP_TIMER_V2_IRQENABLE_CLR 0x30
158
159/*
160 * The functional registers have a different base on v1 and v2 ip.
161 * These registers are offsets from timer->func_base. The func_base
162 * is samae as io_base for v1 and io_base + 0x14 for v2 ip.
163 *
164 */
165#define OMAP_TIMER_V2_FUNC_OFFSET 0x14
166
Tony Lindgrenec974892011-03-29 15:54:48 -0700167#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
168#define _OMAP_TIMER_CTRL_OFFSET 0x24
169#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
170#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
171#define OMAP_TIMER_CTRL_PT (1 << 12)
172#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
173#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
174#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
175#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
176#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
177#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
178#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
179#define OMAP_TIMER_CTRL_POSTED (1 << 2)
180#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
181#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
182#define _OMAP_TIMER_COUNTER_OFFSET 0x28
183#define _OMAP_TIMER_LOAD_OFFSET 0x2c
184#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
185#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
186#define WP_NONE 0 /* no write pending bit */
187#define WP_TCLR (1 << 0)
188#define WP_TCRR (1 << 1)
189#define WP_TLDR (1 << 2)
190#define WP_TTGR (1 << 3)
191#define WP_TMAR (1 << 4)
192#define WP_TPIR (1 << 5)
193#define WP_TNIR (1 << 6)
194#define WP_TCVR (1 << 7)
195#define WP_TOCR (1 << 8)
196#define WP_TOWR (1 << 9)
197#define _OMAP_TIMER_MATCH_OFFSET 0x38
198#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
199#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
200#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
201#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
202#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
203#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
204#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
205#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
206
207/* register offsets with the write pending bit encoded */
208#define WPSHIFT 16
209
Tony Lindgrenec974892011-03-29 15:54:48 -0700210#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
211 | (WP_NONE << WPSHIFT))
212
213#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
214 | (WP_TCLR << WPSHIFT))
215
216#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
217 | (WP_TCRR << WPSHIFT))
218
219#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
220 | (WP_TLDR << WPSHIFT))
221
222#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
223 | (WP_TTGR << WPSHIFT))
224
225#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
226 | (WP_NONE << WPSHIFT))
227
228#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
229 | (WP_TMAR << WPSHIFT))
230
231#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
232 | (WP_NONE << WPSHIFT))
233
234#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
235 | (WP_NONE << WPSHIFT))
236
237#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
238 | (WP_NONE << WPSHIFT))
239
240#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
241 | (WP_TPIR << WPSHIFT))
242
243#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
244 | (WP_TNIR << WPSHIFT))
245
246#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
247 | (WP_TCVR << WPSHIFT))
248
249#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
250 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
251
252#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
253 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
254
255struct omap_dm_timer {
256 unsigned long phys_base;
Tarun Kanti DebBarmadf284722011-09-20 17:00:19 +0530257 int id;
Tony Lindgrenec974892011-03-29 15:54:48 -0700258 int irq;
Tarun Kanti DebBarmaf1bbbb12012-05-07 23:55:30 -0600259 struct clk *fclk;
Tarun Kanti DebBarma3392cdd2011-09-20 17:00:20 +0530260
Tony Lindgrenee17f112011-09-16 15:44:20 -0700261 void __iomem *io_base;
262 void __iomem *sys_stat; /* TISTAT timer status */
263 void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */
264 void __iomem *irq_ena; /* irq enable */
265 void __iomem *irq_dis; /* irq disable, only on v2 ip */
266 void __iomem *pend; /* write pending */
267 void __iomem *func_base; /* function register base */
268
Tony Lindgrenaa561882011-03-29 15:54:48 -0700269 unsigned long rate;
Tony Lindgrenec974892011-03-29 15:54:48 -0700270 unsigned reserved:1;
Tony Lindgrenec974892011-03-29 15:54:48 -0700271 unsigned posted:1;
Tarun Kanti DebBarmab4811132011-09-20 17:00:24 +0530272 struct timer_regs context;
273 bool loses_context;
274 int ctx_loss_count;
275 int revision;
Tarun Kanti DebBarma97933d62011-09-20 17:00:17 +0530276 struct platform_device *pdev;
Tarun Kanti DebBarmadf284722011-09-20 17:00:19 +0530277 struct list_head node;
Tarun Kanti DebBarmab4811132011-09-20 17:00:24 +0530278
Tomi Valkeinenfc013872011-06-09 16:56:23 +0300279 int (*get_context_loss_count)(struct device *dev);
Tony Lindgrenec974892011-03-29 15:54:48 -0700280};
Russell Kinga09e64f2008-08-05 16:14:15 +0100281
Tarun Kanti DebBarma3392cdd2011-09-20 17:00:20 +0530282int omap_dm_timer_prepare(struct omap_dm_timer *timer);
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700283
Tony Lindgrenee17f112011-09-16 15:44:20 -0700284static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700285 int posted)
286{
287 if (posted)
Tony Lindgrenee17f112011-09-16 15:44:20 -0700288 while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700289 cpu_relax();
290
Tony Lindgrenee17f112011-09-16 15:44:20 -0700291 return __raw_readl(timer->func_base + (reg & 0xff));
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700292}
293
Tony Lindgrenee17f112011-09-16 15:44:20 -0700294static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
295 u32 reg, u32 val, int posted)
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700296{
297 if (posted)
Tony Lindgrenee17f112011-09-16 15:44:20 -0700298 while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700299 cpu_relax();
300
Tony Lindgrenee17f112011-09-16 15:44:20 -0700301 __raw_writel(val, timer->func_base + (reg & 0xff));
302}
303
304static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
305{
306 u32 tidr;
307
308 /* Assume v1 ip if bits [31:16] are zero */
309 tidr = __raw_readl(timer->io_base);
310 if (!(tidr >> 16)) {
Tarun Kanti DebBarmab4811132011-09-20 17:00:24 +0530311 timer->revision = 1;
Tony Lindgrenee17f112011-09-16 15:44:20 -0700312 timer->sys_stat = timer->io_base +
313 OMAP_TIMER_V1_SYS_STAT_OFFSET;
314 timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
315 timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
Paul Walmsleya7022d62012-04-13 06:34:28 -0600316 timer->irq_dis = NULL;
Tony Lindgrenee17f112011-09-16 15:44:20 -0700317 timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
318 timer->func_base = timer->io_base;
319 } else {
Tarun Kanti DebBarmab4811132011-09-20 17:00:24 +0530320 timer->revision = 2;
Paul Walmsleya7022d62012-04-13 06:34:28 -0600321 timer->sys_stat = NULL;
Tony Lindgrenee17f112011-09-16 15:44:20 -0700322 timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
323 timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
324 timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
325 timer->pend = timer->io_base +
326 _OMAP_TIMER_WRITE_PEND_OFFSET +
327 OMAP_TIMER_V2_FUNC_OFFSET;
328 timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
329 }
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700330}
331
332/* Assumes the source clock has been set by caller */
Tony Lindgrenee17f112011-09-16 15:44:20 -0700333static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer,
334 int autoidle, int wakeup)
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700335{
336 u32 l;
337
Tony Lindgrenee17f112011-09-16 15:44:20 -0700338 l = __raw_readl(timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700339 l |= 0x02 << 3; /* Set to smart-idle mode */
340 l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
341
342 if (autoidle)
343 l |= 0x1 << 0;
344
345 if (wakeup)
346 l |= 1 << 2;
347
Tony Lindgrenee17f112011-09-16 15:44:20 -0700348 __raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700349
350 /* Match hardware reset default of posted mode */
Tony Lindgrenee17f112011-09-16 15:44:20 -0700351 __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700352 OMAP_TIMER_CTRL_POSTED, 0);
353}
354
355static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
356 struct clk *parent)
357{
358 int ret;
359
360 clk_disable(timer_fck);
361 ret = clk_set_parent(timer_fck, parent);
362 clk_enable(timer_fck);
363
364 /*
365 * When the functional clock disappears, too quick writes seem
366 * to cause an abort. XXX Is this still necessary?
367 */
368 __delay(300000);
369
370 return ret;
371}
372
Tony Lindgrenee17f112011-09-16 15:44:20 -0700373static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
374 int posted, unsigned long rate)
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700375{
376 u32 l;
377
Tony Lindgrenee17f112011-09-16 15:44:20 -0700378 l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700379 if (l & OMAP_TIMER_CTRL_ST) {
380 l &= ~0x1;
Tony Lindgrenee17f112011-09-16 15:44:20 -0700381 __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700382#ifdef CONFIG_ARCH_OMAP2PLUS
383 /* Readback to make sure write has completed */
Tony Lindgrenee17f112011-09-16 15:44:20 -0700384 __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700385 /*
386 * Wait for functional clock period x 3.5 to make sure that
387 * timer is stopped
388 */
389 udelay(3500000 / rate + 1);
390#endif
391 }
392
393 /* Ack possibly pending interrupt */
Tony Lindgrenee17f112011-09-16 15:44:20 -0700394 __raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700395}
396
Tony Lindgrenee17f112011-09-16 15:44:20 -0700397static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
398 u32 ctrl, unsigned int load,
399 int posted)
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700400{
Tony Lindgrenee17f112011-09-16 15:44:20 -0700401 __omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted);
402 __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted);
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700403}
404
Tony Lindgrenee17f112011-09-16 15:44:20 -0700405static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700406 unsigned int value)
407{
Tony Lindgrenee17f112011-09-16 15:44:20 -0700408 __raw_writel(value, timer->irq_ena);
409 __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700410}
411
Tony Lindgrenee17f112011-09-16 15:44:20 -0700412static inline unsigned int
413__omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700414{
Tony Lindgrenee17f112011-09-16 15:44:20 -0700415 return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700416}
417
Tony Lindgrenee17f112011-09-16 15:44:20 -0700418static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700419 unsigned int value)
420{
Tony Lindgrenee17f112011-09-16 15:44:20 -0700421 __raw_writel(value, timer->irq_stat);
Tony Lindgrencaf64f22011-03-29 15:54:48 -0700422}
423
Russell Kinga09e64f2008-08-05 16:14:15 +0100424#endif /* __ASM_ARCH_DMTIMER_H */