Laurent Pinchart | 5d5166d | 2012-12-15 23:51:24 +0100 | [diff] [blame] | 1 | /* |
| 2 | * sh73a0 processor support - PFC hardware block |
| 3 | * |
| 4 | * Copyright (C) 2010 Renesas Solutions Corp. |
| 5 | * Copyright (C) 2010 NISHIMOTO Hiroki |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of the |
| 10 | * License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
Laurent Pinchart | b823899 | 2013-03-13 01:31:23 +0100 | [diff] [blame^] | 21 | #include <linux/io.h> |
Laurent Pinchart | 5d5166d | 2012-12-15 23:51:24 +0100 | [diff] [blame] | 22 | #include <linux/kernel.h> |
Laurent Pinchart | b823899 | 2013-03-13 01:31:23 +0100 | [diff] [blame^] | 23 | #include <linux/pinctrl/pinconf-generic.h> |
| 24 | |
Laurent Pinchart | 5d5166d | 2012-12-15 23:51:24 +0100 | [diff] [blame] | 25 | #include <mach/sh73a0.h> |
| 26 | #include <mach/irqs.h> |
| 27 | |
Laurent Pinchart | b823899 | 2013-03-13 01:31:23 +0100 | [diff] [blame^] | 28 | #include "core.h" |
Laurent Pinchart | c332380 | 2012-12-15 23:51:55 +0100 | [diff] [blame] | 29 | #include "sh_pfc.h" |
| 30 | |
Laurent Pinchart | 5d5166d | 2012-12-15 23:51:24 +0100 | [diff] [blame] | 31 | #define CPU_ALL_PORT(fn, pfx, sfx) \ |
Guennadi Liakhovetski | 942785d | 2013-02-12 16:34:31 +0100 | [diff] [blame] | 32 | PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \ |
Laurent Pinchart | 5d5166d | 2012-12-15 23:51:24 +0100 | [diff] [blame] | 33 | PORT_10(fn, pfx##10, sfx), \ |
| 34 | PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \ |
| 35 | PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \ |
| 36 | PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \ |
| 37 | PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \ |
| 38 | PORT_1(fn, pfx##118, sfx), \ |
| 39 | PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \ |
| 40 | PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \ |
| 41 | PORT_10(fn, pfx##15, sfx), \ |
| 42 | PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \ |
| 43 | PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \ |
| 44 | PORT_1(fn, pfx##164, sfx), \ |
| 45 | PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \ |
| 46 | PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \ |
| 47 | PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \ |
| 48 | PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \ |
| 49 | PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \ |
| 50 | PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \ |
| 51 | PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \ |
| 52 | PORT_10(fn, pfx##26, sfx), PORT_10(fn, pfx##27, sfx), \ |
| 53 | PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \ |
| 54 | PORT_1(fn, pfx##282, sfx), \ |
| 55 | PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \ |
| 56 | PORT_10(fn, pfx##29, sfx), PORT_10(fn, pfx##30, sfx) |
| 57 | |
| 58 | enum { |
| 59 | PINMUX_RESERVED = 0, |
| 60 | |
| 61 | PINMUX_DATA_BEGIN, |
| 62 | PORT_ALL(DATA), /* PORT0_DATA -> PORT309_DATA */ |
| 63 | PINMUX_DATA_END, |
| 64 | |
| 65 | PINMUX_INPUT_BEGIN, |
| 66 | PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */ |
| 67 | PINMUX_INPUT_END, |
| 68 | |
| 69 | PINMUX_INPUT_PULLUP_BEGIN, |
| 70 | PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */ |
| 71 | PINMUX_INPUT_PULLUP_END, |
| 72 | |
| 73 | PINMUX_INPUT_PULLDOWN_BEGIN, |
| 74 | PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */ |
| 75 | PINMUX_INPUT_PULLDOWN_END, |
| 76 | |
| 77 | PINMUX_OUTPUT_BEGIN, |
| 78 | PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */ |
| 79 | PINMUX_OUTPUT_END, |
| 80 | |
| 81 | PINMUX_FUNCTION_BEGIN, |
| 82 | PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */ |
| 83 | PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */ |
| 84 | PORT_ALL(FN0), /* PORT0_FN0 -> PORT309_FN0 */ |
| 85 | PORT_ALL(FN1), /* PORT0_FN1 -> PORT309_FN1 */ |
| 86 | PORT_ALL(FN2), /* PORT0_FN2 -> PORT309_FN2 */ |
| 87 | PORT_ALL(FN3), /* PORT0_FN3 -> PORT309_FN3 */ |
| 88 | PORT_ALL(FN4), /* PORT0_FN4 -> PORT309_FN4 */ |
| 89 | PORT_ALL(FN5), /* PORT0_FN5 -> PORT309_FN5 */ |
| 90 | PORT_ALL(FN6), /* PORT0_FN6 -> PORT309_FN6 */ |
| 91 | PORT_ALL(FN7), /* PORT0_FN7 -> PORT309_FN7 */ |
| 92 | |
| 93 | MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1, |
| 94 | MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1, |
| 95 | MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1, |
| 96 | MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1, |
| 97 | MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1, |
| 98 | MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1, |
| 99 | MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1, |
| 100 | MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1, |
| 101 | MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1, |
| 102 | MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1, |
| 103 | MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1, |
| 104 | MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1, |
| 105 | MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1, |
| 106 | MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1, |
| 107 | MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1, |
| 108 | MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1, |
| 109 | MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1, |
| 110 | MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1, |
| 111 | MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1, |
| 112 | MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1, |
| 113 | MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1, |
| 114 | MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1, |
| 115 | MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1, |
| 116 | MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1, |
| 117 | MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1, |
| 118 | MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1, |
| 119 | MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1, |
| 120 | MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1, |
| 121 | MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1, |
| 122 | MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1, |
| 123 | MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1, |
| 124 | MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1, |
| 125 | MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1, |
| 126 | MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1, |
| 127 | MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1, |
| 128 | MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1, |
| 129 | MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1, |
| 130 | MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1, |
| 131 | MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1, |
| 132 | MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1, |
| 133 | MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1, |
| 134 | MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1, |
| 135 | PINMUX_FUNCTION_END, |
| 136 | |
| 137 | PINMUX_MARK_BEGIN, |
| 138 | /* Hardware manual Table 25-1 (Function 0-7) */ |
| 139 | VBUS_0_MARK, |
| 140 | GPI0_MARK, |
| 141 | GPI1_MARK, |
| 142 | GPI2_MARK, |
| 143 | GPI3_MARK, |
| 144 | GPI4_MARK, |
| 145 | GPI5_MARK, |
| 146 | GPI6_MARK, |
| 147 | GPI7_MARK, |
| 148 | SCIFA7_RXD_MARK, |
| 149 | SCIFA7_CTS__MARK, |
| 150 | GPO7_MARK, MFG0_OUT2_MARK, |
| 151 | GPO6_MARK, MFG1_OUT2_MARK, |
| 152 | GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK, |
| 153 | SCIFA0_TXD_MARK, |
| 154 | SCIFA7_TXD_MARK, |
| 155 | SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK, |
| 156 | GPO0_MARK, |
| 157 | GPO1_MARK, |
| 158 | GPO2_MARK, STATUS0_MARK, |
| 159 | GPO3_MARK, STATUS1_MARK, |
| 160 | GPO4_MARK, STATUS2_MARK, |
| 161 | VINT_MARK, |
| 162 | TCKON_MARK, |
| 163 | XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \ |
| 164 | MFG0_OUT1_MARK, PORT27_IROUT_MARK, |
| 165 | XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \ |
| 166 | PORT28_TPU1TO1_MARK, |
| 167 | SIM_RST_MARK, PORT29_TPU1TO1_MARK, |
| 168 | SIM_CLK_MARK, PORT30_VIO_CKOR_MARK, |
| 169 | SIM_D_MARK, PORT31_IROUT_MARK, |
| 170 | SCIFA4_TXD_MARK, |
| 171 | SCIFA4_RXD_MARK, XWUP_MARK, |
| 172 | SCIFA4_RTS__MARK, |
| 173 | SCIFA4_CTS__MARK, |
| 174 | FSIBOBT_MARK, FSIBIBT_MARK, |
| 175 | FSIBOLR_MARK, FSIBILR_MARK, |
| 176 | FSIBOSLD_MARK, |
| 177 | FSIBISLD_MARK, |
| 178 | VACK_MARK, |
| 179 | XTAL1L_MARK, |
| 180 | SCIFA0_RTS__MARK, FSICOSLDT2_MARK, |
| 181 | SCIFA0_RXD_MARK, |
| 182 | SCIFA0_CTS__MARK, FSICOSLDT1_MARK, |
| 183 | FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK, |
| 184 | FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK, |
| 185 | FSICOSLD_MARK, PORT47_FSICSPDIF_MARK, |
| 186 | FSICISLD_MARK, FSIDISLD_MARK, |
| 187 | FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK, |
| 188 | FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK, |
| 189 | |
| 190 | FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK, |
| 191 | FSIAOSLD_MARK, BBIF2_TXD2_MARK, |
| 192 | FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \ |
| 193 | PORT53_FSICSPDIF_MARK, |
| 194 | FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \ |
| 195 | FSICCK_MARK, FSICOMC_MARK, |
| 196 | FSIAISLD_MARK, TPU0TO0_MARK, |
| 197 | A0_MARK, BS__MARK, |
| 198 | A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK, |
| 199 | A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK, |
| 200 | A14_MARK, KEYOUT5_MARK, |
| 201 | A15_MARK, KEYOUT4_MARK, |
| 202 | A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK, |
| 203 | A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK, |
| 204 | A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK, |
| 205 | A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK, |
| 206 | A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK, |
| 207 | A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK, |
| 208 | A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK, |
| 209 | A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK, |
| 210 | A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK, |
| 211 | A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK, |
| 212 | A26_MARK, KEYIN6_MARK, |
| 213 | KEYIN7_MARK, |
| 214 | D0_NAF0_MARK, |
| 215 | D1_NAF1_MARK, |
| 216 | D2_NAF2_MARK, |
| 217 | D3_NAF3_MARK, |
| 218 | D4_NAF4_MARK, |
| 219 | D5_NAF5_MARK, |
| 220 | D6_NAF6_MARK, |
| 221 | D7_NAF7_MARK, |
| 222 | D8_NAF8_MARK, |
| 223 | D9_NAF9_MARK, |
| 224 | D10_NAF10_MARK, |
| 225 | D11_NAF11_MARK, |
| 226 | D12_NAF12_MARK, |
| 227 | D13_NAF13_MARK, |
| 228 | D14_NAF14_MARK, |
| 229 | D15_NAF15_MARK, |
| 230 | CS4__MARK, |
| 231 | CS5A__MARK, PORT91_RDWR_MARK, |
| 232 | CS5B__MARK, FCE1__MARK, |
| 233 | CS6B__MARK, DACK0_MARK, |
| 234 | FCE0__MARK, CS6A__MARK, |
| 235 | WAIT__MARK, DREQ0_MARK, |
| 236 | RD__FSC_MARK, |
| 237 | WE0__FWE_MARK, RDWR_FWE_MARK, |
| 238 | WE1__MARK, |
| 239 | FRB_MARK, |
| 240 | CKO_MARK, |
| 241 | NBRSTOUT__MARK, |
| 242 | NBRST__MARK, |
| 243 | BBIF2_TXD_MARK, |
| 244 | BBIF2_RXD_MARK, |
| 245 | BBIF2_SYNC_MARK, |
| 246 | BBIF2_SCK_MARK, |
| 247 | SCIFA3_CTS__MARK, MFG3_IN2_MARK, |
| 248 | SCIFA3_RXD_MARK, MFG3_IN1_MARK, |
| 249 | BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK, |
| 250 | SCIFA3_TXD_MARK, |
| 251 | HSI_RX_DATA_MARK, BBIF1_RXD_MARK, |
| 252 | HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK, |
| 253 | HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK, |
| 254 | HSI_TX_READY_MARK, BBIF1_TXD_MARK, |
| 255 | HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \ |
| 256 | PORT115_I2C_SCL3_MARK, |
| 257 | HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \ |
| 258 | PORT116_I2C_SDA3_MARK, |
| 259 | HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK, |
| 260 | HSI_TX_FLAG_MARK, |
| 261 | VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK, |
| 262 | |
| 263 | VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \ |
| 264 | VIO2_HD_MARK, LCD2D1_MARK, |
| 265 | VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK, |
| 266 | VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \ |
| 267 | PORT131_KEYOUT11_MARK, LCD2D11_MARK, |
| 268 | VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \ |
| 269 | PORT132_KEYOUT10_MARK, LCD2D12_MARK, |
| 270 | VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK, |
| 271 | VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK, |
| 272 | VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK, |
| 273 | VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK, |
| 274 | VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK, |
| 275 | VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK, |
| 276 | VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK, |
| 277 | VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK, |
| 278 | VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK, |
| 279 | VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK, |
| 280 | VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \ |
| 281 | VIO2_D5_MARK, LCD2D3_MARK, |
| 282 | VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK, |
| 283 | VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \ |
| 284 | PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK, |
| 285 | VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \ |
| 286 | LCD2D18_MARK, |
| 287 | VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK, |
| 288 | VIO_CKO_MARK, |
| 289 | A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK, |
| 290 | MFG0_IN2_MARK, |
| 291 | TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK, |
| 292 | TS_SDAT3_MARK, MSIOF2_RSYNC_MARK, |
| 293 | TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK, |
| 294 | SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK, |
| 295 | SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK, |
| 296 | SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK, |
| 297 | SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK, |
| 298 | DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK, |
| 299 | PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK, |
| 300 | PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK, |
| 301 | PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK, |
| 302 | PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK, |
| 303 | PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK, |
| 304 | LCDD0_MARK, |
| 305 | LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK, |
| 306 | LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK, |
| 307 | LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK, |
| 308 | LCDD4_MARK, PORT196_SCIFA5_TXD_MARK, |
| 309 | LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK, |
| 310 | LCDD6_MARK, |
| 311 | LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK, |
| 312 | LCDD8_MARK, D16_MARK, |
| 313 | LCDD9_MARK, D17_MARK, |
| 314 | LCDD10_MARK, D18_MARK, |
| 315 | LCDD11_MARK, D19_MARK, |
| 316 | LCDD12_MARK, D20_MARK, |
| 317 | LCDD13_MARK, D21_MARK, |
| 318 | LCDD14_MARK, D22_MARK, |
| 319 | LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK, |
| 320 | LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK, |
| 321 | LCDD17_MARK, D25_MARK, |
| 322 | LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK, |
| 323 | LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK, |
| 324 | LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK, |
| 325 | LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK, |
| 326 | LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK, |
| 327 | LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK, |
| 328 | LCDDCK_MARK, LCDWR__MARK, |
| 329 | LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \ |
| 330 | VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK, |
| 331 | LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \ |
| 332 | PORT218_VIO_CKOR_MARK, |
| 333 | LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \ |
| 334 | MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK, |
| 335 | LCDVSYN_MARK, LCDVSYN2_MARK, |
| 336 | LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \ |
| 337 | MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK, |
| 338 | LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \ |
| 339 | VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK, |
| 340 | |
| 341 | SCIFA1_TXD_MARK, OVCN2_MARK, |
| 342 | EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK, |
| 343 | SCIFA1_RTS__MARK, IDIN_MARK, |
| 344 | SCIFA1_RXD_MARK, |
| 345 | SCIFA1_CTS__MARK, MFG1_IN1_MARK, |
| 346 | MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK, |
| 347 | MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK, |
| 348 | MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK, |
| 349 | MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK, |
| 350 | MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK, |
| 351 | MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK, |
| 352 | MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK, |
| 353 | MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK, |
| 354 | MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK, |
| 355 | MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK, |
| 356 | SCIFA6_TXD_MARK, |
| 357 | PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK, |
| 358 | PORT242_IRDA_IN_MARK, MFG4_IN2_MARK, |
| 359 | PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK, |
| 360 | PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \ |
| 361 | MSIOF2R_RXD_MARK, |
| 362 | PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \ |
| 363 | MSIOF2R_TXD_MARK, |
| 364 | PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \ |
| 365 | TPU1TO0_MARK, |
| 366 | PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \ |
| 367 | TPU3TO1_MARK, |
| 368 | PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \ |
| 369 | TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK, |
| 370 | PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \ |
| 371 | MSIOF2R_TSYNC_MARK, |
| 372 | SDHICLK0_MARK, |
| 373 | SDHICD0_MARK, |
| 374 | SDHID0_0_MARK, |
| 375 | SDHID0_1_MARK, |
| 376 | SDHID0_2_MARK, |
| 377 | SDHID0_3_MARK, |
| 378 | SDHICMD0_MARK, |
| 379 | SDHIWP0_MARK, |
| 380 | SDHICLK1_MARK, |
| 381 | SDHID1_0_MARK, TS_SPSYNC2_MARK, |
| 382 | SDHID1_1_MARK, TS_SDAT2_MARK, |
| 383 | SDHID1_2_MARK, TS_SDEN2_MARK, |
| 384 | SDHID1_3_MARK, TS_SCK2_MARK, |
| 385 | SDHICMD1_MARK, |
| 386 | SDHICLK2_MARK, |
| 387 | SDHID2_0_MARK, TS_SPSYNC4_MARK, |
| 388 | SDHID2_1_MARK, TS_SDAT4_MARK, |
| 389 | SDHID2_2_MARK, TS_SDEN4_MARK, |
| 390 | SDHID2_3_MARK, TS_SCK4_MARK, |
| 391 | SDHICMD2_MARK, |
| 392 | MMCCLK0_MARK, |
| 393 | MMCD0_0_MARK, |
| 394 | MMCD0_1_MARK, |
| 395 | MMCD0_2_MARK, |
| 396 | MMCD0_3_MARK, |
| 397 | MMCD0_4_MARK, TS_SPSYNC5_MARK, |
| 398 | MMCD0_5_MARK, TS_SDAT5_MARK, |
| 399 | MMCD0_6_MARK, TS_SDEN5_MARK, |
| 400 | MMCD0_7_MARK, TS_SCK5_MARK, |
| 401 | MMCCMD0_MARK, |
| 402 | RESETOUTS__MARK, EXTAL2OUT_MARK, |
| 403 | MCP_WAIT__MCP_FRB_MARK, |
| 404 | MCP_CKO_MARK, MMCCLK1_MARK, |
| 405 | MCP_D15_MCP_NAF15_MARK, |
| 406 | MCP_D14_MCP_NAF14_MARK, |
| 407 | MCP_D13_MCP_NAF13_MARK, |
| 408 | MCP_D12_MCP_NAF12_MARK, |
| 409 | MCP_D11_MCP_NAF11_MARK, |
| 410 | MCP_D10_MCP_NAF10_MARK, |
| 411 | MCP_D9_MCP_NAF9_MARK, |
| 412 | MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK, |
| 413 | MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK, |
| 414 | |
| 415 | MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK, |
| 416 | MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK, |
| 417 | MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK, |
| 418 | MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK, |
| 419 | MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK, |
| 420 | MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK, |
| 421 | MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK, |
| 422 | MCP_NBRSTOUT__MARK, |
| 423 | MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK, |
| 424 | |
| 425 | /* MSEL2 special cases */ |
| 426 | TSIF2_TS_XX1_MARK, |
| 427 | TSIF2_TS_XX2_MARK, |
| 428 | TSIF2_TS_XX3_MARK, |
| 429 | TSIF2_TS_XX4_MARK, |
| 430 | TSIF2_TS_XX5_MARK, |
| 431 | TSIF1_TS_XX1_MARK, |
| 432 | TSIF1_TS_XX2_MARK, |
| 433 | TSIF1_TS_XX3_MARK, |
| 434 | TSIF1_TS_XX4_MARK, |
| 435 | TSIF1_TS_XX5_MARK, |
| 436 | TSIF0_TS_XX1_MARK, |
| 437 | TSIF0_TS_XX2_MARK, |
| 438 | TSIF0_TS_XX3_MARK, |
| 439 | TSIF0_TS_XX4_MARK, |
| 440 | TSIF0_TS_XX5_MARK, |
| 441 | MST1_TS_XX1_MARK, |
| 442 | MST1_TS_XX2_MARK, |
| 443 | MST1_TS_XX3_MARK, |
| 444 | MST1_TS_XX4_MARK, |
| 445 | MST1_TS_XX5_MARK, |
| 446 | MST0_TS_XX1_MARK, |
| 447 | MST0_TS_XX2_MARK, |
| 448 | MST0_TS_XX3_MARK, |
| 449 | MST0_TS_XX4_MARK, |
| 450 | MST0_TS_XX5_MARK, |
| 451 | |
| 452 | /* MSEL3 special cases */ |
| 453 | SDHI0_VCCQ_MC0_ON_MARK, |
| 454 | SDHI0_VCCQ_MC0_OFF_MARK, |
| 455 | DEBUG_MON_VIO_MARK, |
| 456 | DEBUG_MON_LCDD_MARK, |
| 457 | LCDC_LCDC0_MARK, |
| 458 | LCDC_LCDC1_MARK, |
| 459 | |
| 460 | /* MSEL4 special cases */ |
| 461 | IRQ9_MEM_INT_MARK, |
| 462 | IRQ9_MCP_INT_MARK, |
| 463 | A11_MARK, |
| 464 | KEYOUT8_MARK, |
| 465 | TPU4TO3_MARK, |
| 466 | RESETA_N_PU_ON_MARK, |
| 467 | RESETA_N_PU_OFF_MARK, |
| 468 | EDBGREQ_PD_MARK, |
| 469 | EDBGREQ_PU_MARK, |
| 470 | |
| 471 | /* Functions with pull-ups */ |
| 472 | KEYIN0_PU_MARK, |
| 473 | KEYIN1_PU_MARK, |
| 474 | KEYIN2_PU_MARK, |
| 475 | KEYIN3_PU_MARK, |
| 476 | KEYIN4_PU_MARK, |
| 477 | KEYIN5_PU_MARK, |
| 478 | KEYIN6_PU_MARK, |
| 479 | KEYIN7_PU_MARK, |
| 480 | SDHICD0_PU_MARK, |
| 481 | SDHID0_0_PU_MARK, |
| 482 | SDHID0_1_PU_MARK, |
| 483 | SDHID0_2_PU_MARK, |
| 484 | SDHID0_3_PU_MARK, |
| 485 | SDHICMD0_PU_MARK, |
| 486 | SDHIWP0_PU_MARK, |
| 487 | SDHID1_0_PU_MARK, |
| 488 | SDHID1_1_PU_MARK, |
| 489 | SDHID1_2_PU_MARK, |
| 490 | SDHID1_3_PU_MARK, |
| 491 | SDHICMD1_PU_MARK, |
| 492 | SDHID2_0_PU_MARK, |
| 493 | SDHID2_1_PU_MARK, |
| 494 | SDHID2_2_PU_MARK, |
| 495 | SDHID2_3_PU_MARK, |
| 496 | SDHICMD2_PU_MARK, |
| 497 | MMCCMD0_PU_MARK, |
| 498 | MMCCMD1_PU_MARK, |
| 499 | MMCD0_0_PU_MARK, |
| 500 | MMCD0_1_PU_MARK, |
| 501 | MMCD0_2_PU_MARK, |
| 502 | MMCD0_3_PU_MARK, |
| 503 | MMCD0_4_PU_MARK, |
| 504 | MMCD0_5_PU_MARK, |
| 505 | MMCD0_6_PU_MARK, |
| 506 | MMCD0_7_PU_MARK, |
| 507 | FSIBISLD_PU_MARK, |
| 508 | FSIACK_PU_MARK, |
| 509 | FSIAILR_PU_MARK, |
| 510 | FSIAIBT_PU_MARK, |
| 511 | FSIAISLD_PU_MARK, |
| 512 | |
| 513 | PINMUX_MARK_END, |
| 514 | }; |
| 515 | |
Laurent Pinchart | cd3c1be | 2013-02-16 18:47:05 +0100 | [diff] [blame] | 516 | static const pinmux_enum_t pinmux_data[] = { |
Laurent Pinchart | 5d5166d | 2012-12-15 23:51:24 +0100 | [diff] [blame] | 517 | /* specify valid pin states for each pin in GPIO mode */ |
| 518 | |
| 519 | /* Table 25-1 (I/O and Pull U/D) */ |
| 520 | PORT_DATA_I_PD(0), |
| 521 | PORT_DATA_I_PU(1), |
| 522 | PORT_DATA_I_PU(2), |
| 523 | PORT_DATA_I_PU(3), |
| 524 | PORT_DATA_I_PU(4), |
| 525 | PORT_DATA_I_PU(5), |
| 526 | PORT_DATA_I_PU(6), |
| 527 | PORT_DATA_I_PU(7), |
| 528 | PORT_DATA_I_PU(8), |
| 529 | PORT_DATA_I_PD(9), |
| 530 | PORT_DATA_I_PD(10), |
| 531 | PORT_DATA_I_PU_PD(11), |
| 532 | PORT_DATA_IO_PU_PD(12), |
| 533 | PORT_DATA_IO_PU_PD(13), |
| 534 | PORT_DATA_IO_PU_PD(14), |
| 535 | PORT_DATA_IO_PU_PD(15), |
| 536 | PORT_DATA_IO_PD(16), |
| 537 | PORT_DATA_IO_PD(17), |
| 538 | PORT_DATA_IO_PU(18), |
| 539 | PORT_DATA_IO_PU(19), |
| 540 | PORT_DATA_O(20), |
| 541 | PORT_DATA_O(21), |
| 542 | PORT_DATA_O(22), |
| 543 | PORT_DATA_O(23), |
| 544 | PORT_DATA_O(24), |
| 545 | PORT_DATA_I_PD(25), |
| 546 | PORT_DATA_I_PD(26), |
| 547 | PORT_DATA_IO_PU(27), |
| 548 | PORT_DATA_IO_PU(28), |
| 549 | PORT_DATA_IO_PD(29), |
| 550 | PORT_DATA_IO_PD(30), |
| 551 | PORT_DATA_IO_PU(31), |
| 552 | PORT_DATA_IO_PD(32), |
| 553 | PORT_DATA_I_PU_PD(33), |
| 554 | PORT_DATA_IO_PD(34), |
| 555 | PORT_DATA_I_PU_PD(35), |
| 556 | PORT_DATA_IO_PD(36), |
| 557 | PORT_DATA_IO(37), |
| 558 | PORT_DATA_O(38), |
| 559 | PORT_DATA_I_PU(39), |
| 560 | PORT_DATA_I_PU_PD(40), |
| 561 | PORT_DATA_O(41), |
| 562 | PORT_DATA_IO_PD(42), |
| 563 | PORT_DATA_IO_PU_PD(43), |
| 564 | PORT_DATA_IO_PU_PD(44), |
| 565 | PORT_DATA_IO_PD(45), |
| 566 | PORT_DATA_IO_PD(46), |
| 567 | PORT_DATA_IO_PD(47), |
| 568 | PORT_DATA_I_PD(48), |
| 569 | PORT_DATA_IO_PU_PD(49), |
| 570 | PORT_DATA_IO_PD(50), |
| 571 | |
| 572 | PORT_DATA_IO_PD(51), |
| 573 | PORT_DATA_O(52), |
| 574 | PORT_DATA_IO_PU_PD(53), |
| 575 | PORT_DATA_IO_PU_PD(54), |
| 576 | PORT_DATA_IO_PD(55), |
| 577 | PORT_DATA_I_PU_PD(56), |
| 578 | PORT_DATA_IO(57), |
| 579 | PORT_DATA_IO(58), |
| 580 | PORT_DATA_IO(59), |
| 581 | PORT_DATA_IO(60), |
| 582 | PORT_DATA_IO(61), |
| 583 | PORT_DATA_IO_PD(62), |
| 584 | PORT_DATA_IO_PD(63), |
| 585 | PORT_DATA_IO_PU_PD(64), |
| 586 | PORT_DATA_IO_PD(65), |
| 587 | PORT_DATA_IO_PU_PD(66), |
| 588 | PORT_DATA_IO_PU_PD(67), |
| 589 | PORT_DATA_IO_PU_PD(68), |
| 590 | PORT_DATA_IO_PU_PD(69), |
| 591 | PORT_DATA_IO_PU_PD(70), |
| 592 | PORT_DATA_IO_PU_PD(71), |
| 593 | PORT_DATA_IO_PU_PD(72), |
| 594 | PORT_DATA_I_PU_PD(73), |
| 595 | PORT_DATA_IO_PU(74), |
| 596 | PORT_DATA_IO_PU(75), |
| 597 | PORT_DATA_IO_PU(76), |
| 598 | PORT_DATA_IO_PU(77), |
| 599 | PORT_DATA_IO_PU(78), |
| 600 | PORT_DATA_IO_PU(79), |
| 601 | PORT_DATA_IO_PU(80), |
| 602 | PORT_DATA_IO_PU(81), |
| 603 | PORT_DATA_IO_PU(82), |
| 604 | PORT_DATA_IO_PU(83), |
| 605 | PORT_DATA_IO_PU(84), |
| 606 | PORT_DATA_IO_PU(85), |
| 607 | PORT_DATA_IO_PU(86), |
| 608 | PORT_DATA_IO_PU(87), |
| 609 | PORT_DATA_IO_PU(88), |
| 610 | PORT_DATA_IO_PU(89), |
| 611 | PORT_DATA_O(90), |
| 612 | PORT_DATA_IO_PU(91), |
| 613 | PORT_DATA_O(92), |
| 614 | PORT_DATA_IO_PU(93), |
| 615 | PORT_DATA_O(94), |
| 616 | PORT_DATA_I_PU_PD(95), |
| 617 | PORT_DATA_IO(96), |
| 618 | PORT_DATA_IO(97), |
| 619 | PORT_DATA_IO(98), |
| 620 | PORT_DATA_I_PU(99), |
| 621 | PORT_DATA_O(100), |
| 622 | PORT_DATA_O(101), |
| 623 | PORT_DATA_I_PU(102), |
| 624 | PORT_DATA_IO_PD(103), |
| 625 | PORT_DATA_I_PU_PD(104), |
| 626 | PORT_DATA_I_PD(105), |
| 627 | PORT_DATA_I_PD(106), |
| 628 | PORT_DATA_I_PU_PD(107), |
| 629 | PORT_DATA_I_PU_PD(108), |
| 630 | PORT_DATA_IO_PD(109), |
| 631 | PORT_DATA_IO_PD(110), |
| 632 | PORT_DATA_IO_PU_PD(111), |
| 633 | PORT_DATA_IO_PU_PD(112), |
| 634 | PORT_DATA_IO_PU_PD(113), |
| 635 | PORT_DATA_IO_PD(114), |
| 636 | PORT_DATA_IO_PU(115), |
| 637 | PORT_DATA_IO_PU(116), |
| 638 | PORT_DATA_IO_PU_PD(117), |
| 639 | PORT_DATA_IO_PU_PD(118), |
| 640 | PORT_DATA_IO_PD(128), |
| 641 | |
| 642 | PORT_DATA_IO_PD(129), |
| 643 | PORT_DATA_IO_PU_PD(130), |
| 644 | PORT_DATA_IO_PD(131), |
| 645 | PORT_DATA_IO_PD(132), |
| 646 | PORT_DATA_IO_PD(133), |
| 647 | PORT_DATA_IO_PU_PD(134), |
| 648 | PORT_DATA_IO_PU_PD(135), |
| 649 | PORT_DATA_IO_PU_PD(136), |
| 650 | PORT_DATA_IO_PU_PD(137), |
| 651 | PORT_DATA_IO_PD(138), |
| 652 | PORT_DATA_IO_PD(139), |
| 653 | PORT_DATA_IO_PD(140), |
| 654 | PORT_DATA_IO_PD(141), |
| 655 | PORT_DATA_IO_PD(142), |
| 656 | PORT_DATA_IO_PD(143), |
| 657 | PORT_DATA_IO_PU_PD(144), |
| 658 | PORT_DATA_IO_PD(145), |
| 659 | PORT_DATA_IO_PU_PD(146), |
| 660 | PORT_DATA_IO_PU_PD(147), |
| 661 | PORT_DATA_IO_PU_PD(148), |
| 662 | PORT_DATA_IO_PU_PD(149), |
| 663 | PORT_DATA_I_PU_PD(150), |
| 664 | PORT_DATA_IO_PU_PD(151), |
| 665 | PORT_DATA_IO_PU_PD(152), |
| 666 | PORT_DATA_IO_PD(153), |
| 667 | PORT_DATA_IO_PD(154), |
| 668 | PORT_DATA_I_PU_PD(155), |
| 669 | PORT_DATA_IO_PU_PD(156), |
| 670 | PORT_DATA_I_PD(157), |
| 671 | PORT_DATA_IO_PD(158), |
| 672 | PORT_DATA_IO_PU_PD(159), |
| 673 | PORT_DATA_IO_PU_PD(160), |
| 674 | PORT_DATA_I_PU_PD(161), |
| 675 | PORT_DATA_I_PU_PD(162), |
| 676 | PORT_DATA_IO_PU_PD(163), |
| 677 | PORT_DATA_I_PU_PD(164), |
| 678 | PORT_DATA_IO_PD(192), |
| 679 | PORT_DATA_IO_PU_PD(193), |
| 680 | PORT_DATA_IO_PD(194), |
| 681 | PORT_DATA_IO_PU_PD(195), |
| 682 | PORT_DATA_IO_PD(196), |
| 683 | PORT_DATA_IO_PD(197), |
| 684 | PORT_DATA_IO_PD(198), |
| 685 | PORT_DATA_IO_PD(199), |
| 686 | PORT_DATA_IO_PU_PD(200), |
| 687 | PORT_DATA_IO_PU_PD(201), |
| 688 | PORT_DATA_IO_PU_PD(202), |
| 689 | PORT_DATA_IO_PU_PD(203), |
| 690 | PORT_DATA_IO_PU_PD(204), |
| 691 | PORT_DATA_IO_PU_PD(205), |
| 692 | PORT_DATA_IO_PU_PD(206), |
| 693 | PORT_DATA_IO_PD(207), |
| 694 | PORT_DATA_IO_PD(208), |
| 695 | PORT_DATA_IO_PD(209), |
| 696 | PORT_DATA_IO_PD(210), |
| 697 | PORT_DATA_IO_PD(211), |
| 698 | PORT_DATA_IO_PD(212), |
| 699 | PORT_DATA_IO_PD(213), |
| 700 | PORT_DATA_IO_PU_PD(214), |
| 701 | PORT_DATA_IO_PU_PD(215), |
| 702 | PORT_DATA_IO_PD(216), |
| 703 | PORT_DATA_IO_PD(217), |
| 704 | PORT_DATA_O(218), |
| 705 | PORT_DATA_IO_PD(219), |
| 706 | PORT_DATA_IO_PD(220), |
| 707 | PORT_DATA_IO_PU_PD(221), |
| 708 | PORT_DATA_IO_PU_PD(222), |
| 709 | PORT_DATA_I_PU_PD(223), |
| 710 | PORT_DATA_I_PU_PD(224), |
| 711 | |
| 712 | PORT_DATA_IO_PU_PD(225), |
| 713 | PORT_DATA_O(226), |
| 714 | PORT_DATA_IO_PU_PD(227), |
| 715 | PORT_DATA_I_PU_PD(228), |
| 716 | PORT_DATA_I_PD(229), |
| 717 | PORT_DATA_IO(230), |
| 718 | PORT_DATA_IO_PU_PD(231), |
| 719 | PORT_DATA_IO_PU_PD(232), |
| 720 | PORT_DATA_I_PU_PD(233), |
| 721 | PORT_DATA_IO_PU_PD(234), |
| 722 | PORT_DATA_IO_PU_PD(235), |
| 723 | PORT_DATA_IO_PU_PD(236), |
| 724 | PORT_DATA_IO_PD(237), |
| 725 | PORT_DATA_IO_PU_PD(238), |
| 726 | PORT_DATA_IO_PU_PD(239), |
| 727 | PORT_DATA_IO_PU_PD(240), |
| 728 | PORT_DATA_O(241), |
| 729 | PORT_DATA_I_PD(242), |
| 730 | PORT_DATA_IO_PU_PD(243), |
| 731 | PORT_DATA_IO_PU_PD(244), |
| 732 | PORT_DATA_IO_PU_PD(245), |
| 733 | PORT_DATA_IO_PU_PD(246), |
| 734 | PORT_DATA_IO_PU_PD(247), |
| 735 | PORT_DATA_IO_PU_PD(248), |
| 736 | PORT_DATA_IO_PU_PD(249), |
| 737 | PORT_DATA_IO_PU_PD(250), |
| 738 | PORT_DATA_IO_PU_PD(251), |
| 739 | PORT_DATA_IO_PU_PD(252), |
| 740 | PORT_DATA_IO_PU_PD(253), |
| 741 | PORT_DATA_IO_PU_PD(254), |
| 742 | PORT_DATA_IO_PU_PD(255), |
| 743 | PORT_DATA_IO_PU_PD(256), |
| 744 | PORT_DATA_IO_PU_PD(257), |
| 745 | PORT_DATA_IO_PU_PD(258), |
| 746 | PORT_DATA_IO_PU_PD(259), |
| 747 | PORT_DATA_IO_PU_PD(260), |
| 748 | PORT_DATA_IO_PU_PD(261), |
| 749 | PORT_DATA_IO_PU_PD(262), |
| 750 | PORT_DATA_IO_PU_PD(263), |
| 751 | PORT_DATA_IO_PU_PD(264), |
| 752 | PORT_DATA_IO_PU_PD(265), |
| 753 | PORT_DATA_IO_PU_PD(266), |
| 754 | PORT_DATA_IO_PU_PD(267), |
| 755 | PORT_DATA_IO_PU_PD(268), |
| 756 | PORT_DATA_IO_PU_PD(269), |
| 757 | PORT_DATA_IO_PU_PD(270), |
| 758 | PORT_DATA_IO_PU_PD(271), |
| 759 | PORT_DATA_IO_PU_PD(272), |
| 760 | PORT_DATA_IO_PU_PD(273), |
| 761 | PORT_DATA_IO_PU_PD(274), |
| 762 | PORT_DATA_IO_PU_PD(275), |
| 763 | PORT_DATA_IO_PU_PD(276), |
| 764 | PORT_DATA_IO_PU_PD(277), |
| 765 | PORT_DATA_IO_PU_PD(278), |
| 766 | PORT_DATA_IO_PU_PD(279), |
| 767 | PORT_DATA_IO_PU_PD(280), |
| 768 | PORT_DATA_O(281), |
| 769 | PORT_DATA_O(282), |
| 770 | PORT_DATA_I_PU(288), |
| 771 | PORT_DATA_IO_PU_PD(289), |
| 772 | PORT_DATA_IO_PU_PD(290), |
| 773 | PORT_DATA_IO_PU_PD(291), |
| 774 | PORT_DATA_IO_PU_PD(292), |
| 775 | PORT_DATA_IO_PU_PD(293), |
| 776 | PORT_DATA_IO_PU_PD(294), |
| 777 | PORT_DATA_IO_PU_PD(295), |
| 778 | PORT_DATA_IO_PU_PD(296), |
| 779 | PORT_DATA_IO_PU_PD(297), |
| 780 | PORT_DATA_IO_PU_PD(298), |
| 781 | |
| 782 | PORT_DATA_IO_PU_PD(299), |
| 783 | PORT_DATA_IO_PU_PD(300), |
| 784 | PORT_DATA_IO_PU_PD(301), |
| 785 | PORT_DATA_IO_PU_PD(302), |
| 786 | PORT_DATA_IO_PU_PD(303), |
| 787 | PORT_DATA_IO_PU_PD(304), |
| 788 | PORT_DATA_IO_PU_PD(305), |
| 789 | PORT_DATA_O(306), |
| 790 | PORT_DATA_O(307), |
| 791 | PORT_DATA_I_PU(308), |
| 792 | PORT_DATA_O(309), |
| 793 | |
| 794 | /* Table 25-1 (Function 0-7) */ |
| 795 | PINMUX_DATA(VBUS_0_MARK, PORT0_FN1), |
| 796 | PINMUX_DATA(GPI0_MARK, PORT1_FN1), |
| 797 | PINMUX_DATA(GPI1_MARK, PORT2_FN1), |
| 798 | PINMUX_DATA(GPI2_MARK, PORT3_FN1), |
| 799 | PINMUX_DATA(GPI3_MARK, PORT4_FN1), |
| 800 | PINMUX_DATA(GPI4_MARK, PORT5_FN1), |
| 801 | PINMUX_DATA(GPI5_MARK, PORT6_FN1), |
| 802 | PINMUX_DATA(GPI6_MARK, PORT7_FN1), |
| 803 | PINMUX_DATA(GPI7_MARK, PORT8_FN1), |
| 804 | PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2), |
| 805 | PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2), |
| 806 | PINMUX_DATA(GPO7_MARK, PORT14_FN1), \ |
| 807 | PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4), |
| 808 | PINMUX_DATA(GPO6_MARK, PORT15_FN1), \ |
| 809 | PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4), |
| 810 | PINMUX_DATA(GPO5_MARK, PORT16_FN1), \ |
| 811 | PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \ |
| 812 | PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \ |
| 813 | PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4), |
| 814 | PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2), |
| 815 | PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2), |
| 816 | PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \ |
| 817 | PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3), |
| 818 | PINMUX_DATA(GPO0_MARK, PORT20_FN1), |
| 819 | PINMUX_DATA(GPO1_MARK, PORT21_FN1), |
| 820 | PINMUX_DATA(GPO2_MARK, PORT22_FN1), \ |
| 821 | PINMUX_DATA(STATUS0_MARK, PORT22_FN2), |
| 822 | PINMUX_DATA(GPO3_MARK, PORT23_FN1), \ |
| 823 | PINMUX_DATA(STATUS1_MARK, PORT23_FN2), |
| 824 | PINMUX_DATA(GPO4_MARK, PORT24_FN1), \ |
| 825 | PINMUX_DATA(STATUS2_MARK, PORT24_FN2), |
| 826 | PINMUX_DATA(VINT_MARK, PORT25_FN1), |
| 827 | PINMUX_DATA(TCKON_MARK, PORT26_FN1), |
| 828 | PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \ |
| 829 | PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0, |
| 830 | MSEL2CR_MSEL16_1), \ |
| 831 | PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0, |
| 832 | MSEL2CR_MSEL18_1), \ |
| 833 | PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \ |
| 834 | PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7), |
| 835 | PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \ |
| 836 | PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0, |
| 837 | MSEL2CR_MSEL16_1), \ |
| 838 | PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0, |
| 839 | MSEL2CR_MSEL18_1), \ |
| 840 | PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7), |
| 841 | PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \ |
| 842 | PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4), |
| 843 | PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \ |
| 844 | PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4), |
| 845 | PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \ |
| 846 | PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4), |
| 847 | PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2), |
| 848 | PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \ |
| 849 | PINMUX_DATA(XWUP_MARK, PORT33_FN3), |
| 850 | PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2), |
| 851 | PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2), |
| 852 | PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \ |
| 853 | PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2), |
| 854 | PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \ |
| 855 | PINMUX_DATA(FSIBILR_MARK, PORT37_FN2), |
| 856 | PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1), |
| 857 | PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1), |
| 858 | PINMUX_DATA(VACK_MARK, PORT40_FN1), |
| 859 | PINMUX_DATA(XTAL1L_MARK, PORT41_FN1), |
| 860 | PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \ |
| 861 | PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3), |
| 862 | PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2), |
| 863 | PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \ |
| 864 | PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3), |
| 865 | PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \ |
| 866 | PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \ |
| 867 | PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \ |
| 868 | PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4), |
| 869 | PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \ |
| 870 | PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \ |
| 871 | PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \ |
| 872 | PINMUX_DATA(FSIDILR_MARK, PORT46_FN4), |
| 873 | PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \ |
| 874 | PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2), |
| 875 | PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \ |
| 876 | PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3), |
| 877 | PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \ |
| 878 | PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \ |
| 879 | PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \ |
| 880 | PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5), |
| 881 | PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \ |
| 882 | PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \ |
| 883 | PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \ |
| 884 | PINMUX_DATA(FSIAILR_MARK, PORT50_FN5), |
| 885 | |
| 886 | PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \ |
| 887 | PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \ |
| 888 | PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \ |
| 889 | PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5), |
| 890 | PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \ |
| 891 | PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2), |
| 892 | PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \ |
| 893 | PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \ |
| 894 | PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \ |
| 895 | PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \ |
| 896 | PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6), |
| 897 | PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \ |
| 898 | PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \ |
| 899 | PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \ |
| 900 | PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \ |
| 901 | PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \ |
| 902 | PINMUX_DATA(FSICOMC_MARK, PORT54_FN7), |
| 903 | PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \ |
| 904 | PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3), |
| 905 | PINMUX_DATA(A0_MARK, PORT57_FN1), \ |
| 906 | PINMUX_DATA(BS__MARK, PORT57_FN2), |
| 907 | PINMUX_DATA(A12_MARK, PORT58_FN1), \ |
| 908 | PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \ |
| 909 | PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4), |
| 910 | PINMUX_DATA(A13_MARK, PORT59_FN1), \ |
| 911 | PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \ |
| 912 | PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4), |
| 913 | PINMUX_DATA(A14_MARK, PORT60_FN1), \ |
| 914 | PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2), |
| 915 | PINMUX_DATA(A15_MARK, PORT61_FN1), \ |
| 916 | PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2), |
| 917 | PINMUX_DATA(A16_MARK, PORT62_FN1), \ |
| 918 | PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \ |
| 919 | PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0), |
| 920 | PINMUX_DATA(A17_MARK, PORT63_FN1), \ |
| 921 | PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \ |
| 922 | PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0), |
| 923 | PINMUX_DATA(A18_MARK, PORT64_FN1), \ |
| 924 | PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \ |
| 925 | PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0), |
| 926 | PINMUX_DATA(A19_MARK, PORT65_FN1), \ |
| 927 | PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \ |
| 928 | PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0), |
| 929 | PINMUX_DATA(A20_MARK, PORT66_FN1), \ |
| 930 | PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \ |
| 931 | PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0), |
| 932 | PINMUX_DATA(A21_MARK, PORT67_FN1), \ |
| 933 | PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \ |
| 934 | PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0), |
| 935 | PINMUX_DATA(A22_MARK, PORT68_FN1), \ |
| 936 | PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \ |
| 937 | PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0), |
| 938 | PINMUX_DATA(A23_MARK, PORT69_FN1), \ |
| 939 | PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \ |
| 940 | PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0), |
| 941 | PINMUX_DATA(A24_MARK, PORT70_FN1), \ |
| 942 | PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \ |
| 943 | PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0), |
| 944 | PINMUX_DATA(A25_MARK, PORT71_FN1), \ |
| 945 | PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \ |
| 946 | PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0), |
| 947 | PINMUX_DATA(A26_MARK, PORT72_FN1), \ |
| 948 | PINMUX_DATA(KEYIN6_MARK, PORT72_FN2), |
| 949 | PINMUX_DATA(KEYIN7_MARK, PORT73_FN2), |
| 950 | PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1), |
| 951 | PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1), |
| 952 | PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1), |
| 953 | PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1), |
| 954 | PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1), |
| 955 | PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1), |
| 956 | PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1), |
| 957 | PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1), |
| 958 | PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1), |
| 959 | PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1), |
| 960 | PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1), |
| 961 | PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1), |
| 962 | PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1), |
| 963 | PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1), |
| 964 | PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1), |
| 965 | PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1), |
| 966 | PINMUX_DATA(CS4__MARK, PORT90_FN1), |
| 967 | PINMUX_DATA(CS5A__MARK, PORT91_FN1), \ |
| 968 | PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2), |
| 969 | PINMUX_DATA(CS5B__MARK, PORT92_FN1), \ |
| 970 | PINMUX_DATA(FCE1__MARK, PORT92_FN2), |
| 971 | PINMUX_DATA(CS6B__MARK, PORT93_FN1), \ |
| 972 | PINMUX_DATA(DACK0_MARK, PORT93_FN4), |
| 973 | PINMUX_DATA(FCE0__MARK, PORT94_FN1), \ |
| 974 | PINMUX_DATA(CS6A__MARK, PORT94_FN2), |
| 975 | PINMUX_DATA(WAIT__MARK, PORT95_FN1), \ |
| 976 | PINMUX_DATA(DREQ0_MARK, PORT95_FN2), |
| 977 | PINMUX_DATA(RD__FSC_MARK, PORT96_FN1), |
| 978 | PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \ |
| 979 | PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2), |
| 980 | PINMUX_DATA(WE1__MARK, PORT98_FN1), |
| 981 | PINMUX_DATA(FRB_MARK, PORT99_FN1), |
| 982 | PINMUX_DATA(CKO_MARK, PORT100_FN1), |
| 983 | PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1), |
| 984 | PINMUX_DATA(NBRST__MARK, PORT102_FN1), |
| 985 | PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3), |
| 986 | PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3), |
| 987 | PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3), |
| 988 | PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3), |
| 989 | PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \ |
| 990 | PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4), |
| 991 | PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \ |
| 992 | PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4), |
| 993 | PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \ |
| 994 | PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \ |
| 995 | PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4), |
| 996 | PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3), |
| 997 | PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \ |
| 998 | PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3), |
| 999 | PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \ |
| 1000 | PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3), |
| 1001 | PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \ |
| 1002 | PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3), |
| 1003 | PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \ |
| 1004 | PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3), |
| 1005 | PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \ |
| 1006 | PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \ |
| 1007 | PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \ |
| 1008 | PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1), |
| 1009 | PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \ |
| 1010 | PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \ |
| 1011 | PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \ |
| 1012 | PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1), |
| 1013 | PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \ |
| 1014 | PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \ |
| 1015 | PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3), |
| 1016 | PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1), |
| 1017 | PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \ |
| 1018 | PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \ |
| 1019 | PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \ |
| 1020 | PINMUX_DATA(LCD2D0_MARK, PORT128_FN7), |
| 1021 | |
| 1022 | PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \ |
| 1023 | PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \ |
| 1024 | PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \ |
| 1025 | PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \ |
| 1026 | PINMUX_DATA(LCD2D1_MARK, PORT129_FN7), |
| 1027 | PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \ |
| 1028 | PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0, |
| 1029 | MSEL4CR_MSEL10_1), \ |
| 1030 | PINMUX_DATA(LCD2D10_MARK, PORT130_FN7), |
| 1031 | PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \ |
| 1032 | PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \ |
| 1033 | PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \ |
| 1034 | PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \ |
| 1035 | PINMUX_DATA(LCD2D11_MARK, PORT131_FN7), |
| 1036 | PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \ |
| 1037 | PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \ |
| 1038 | PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \ |
| 1039 | PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \ |
| 1040 | PINMUX_DATA(LCD2D12_MARK, PORT132_FN7), |
| 1041 | PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \ |
| 1042 | PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \ |
| 1043 | PINMUX_DATA(LCD2D13_MARK, PORT133_FN7), |
| 1044 | PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \ |
| 1045 | PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \ |
| 1046 | PINMUX_DATA(LCD2D14_MARK, PORT134_FN7), |
| 1047 | PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \ |
| 1048 | PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \ |
| 1049 | PINMUX_DATA(LCD2D15_MARK, PORT135_FN7), |
| 1050 | PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \ |
| 1051 | PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \ |
| 1052 | PINMUX_DATA(LCD2D16_MARK, PORT136_FN7), |
| 1053 | PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \ |
| 1054 | PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \ |
| 1055 | PINMUX_DATA(LCD2D17_MARK, PORT137_FN7), |
| 1056 | PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \ |
| 1057 | PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \ |
| 1058 | PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \ |
| 1059 | PINMUX_DATA(LCD2D6_MARK, PORT138_FN7), |
| 1060 | PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \ |
| 1061 | PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \ |
| 1062 | PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \ |
| 1063 | PINMUX_DATA(LCD2D7_MARK, PORT139_FN7), |
| 1064 | PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \ |
| 1065 | PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \ |
| 1066 | PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \ |
| 1067 | PINMUX_DATA(LCD2D8_MARK, PORT140_FN7), |
| 1068 | PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \ |
| 1069 | PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \ |
| 1070 | PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \ |
| 1071 | PINMUX_DATA(LCD2D9_MARK, PORT141_FN7), |
| 1072 | PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \ |
| 1073 | PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \ |
| 1074 | PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \ |
| 1075 | PINMUX_DATA(LCD2D2_MARK, PORT142_FN7), |
| 1076 | PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \ |
| 1077 | PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \ |
| 1078 | PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \ |
| 1079 | PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \ |
| 1080 | PINMUX_DATA(LCD2D3_MARK, PORT143_FN7), |
| 1081 | PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \ |
| 1082 | PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \ |
| 1083 | PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \ |
| 1084 | PINMUX_DATA(LCD2D4_MARK, PORT144_FN7), |
| 1085 | PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \ |
| 1086 | PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \ |
| 1087 | PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \ |
| 1088 | PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \ |
| 1089 | PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \ |
| 1090 | PINMUX_DATA(LCD2D5_MARK, PORT145_FN7), |
| 1091 | PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \ |
| 1092 | PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \ |
| 1093 | PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \ |
| 1094 | PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \ |
| 1095 | PINMUX_DATA(LCD2D18_MARK, PORT146_FN7), |
| 1096 | PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \ |
| 1097 | PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \ |
| 1098 | PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \ |
| 1099 | PINMUX_DATA(LCD2D19_MARK, PORT147_FN7), |
| 1100 | PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1), |
| 1101 | PINMUX_DATA(A27_MARK, PORT149_FN1), \ |
| 1102 | PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \ |
| 1103 | PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \ |
| 1104 | PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4), |
| 1105 | PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3), |
| 1106 | PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \ |
| 1107 | PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5), |
| 1108 | PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \ |
| 1109 | PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5), |
| 1110 | PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \ |
| 1111 | PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \ |
| 1112 | PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5), |
| 1113 | PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \ |
| 1114 | PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5), |
| 1115 | PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \ |
| 1116 | PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5), |
| 1117 | PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \ |
| 1118 | PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5), |
| 1119 | PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \ |
| 1120 | PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0, |
| 1121 | MSEL4CR_MSEL10_0), |
| 1122 | PINMUX_DATA(DINT__MARK, PORT158_FN1), \ |
| 1123 | PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \ |
| 1124 | PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4), |
| 1125 | PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \ |
| 1126 | PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \ |
| 1127 | PINMUX_DATA(NMI_MARK, PORT159_FN3), |
| 1128 | PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \ |
| 1129 | PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1), |
| 1130 | PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \ |
| 1131 | PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1), |
| 1132 | PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \ |
| 1133 | PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1), |
| 1134 | PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \ |
| 1135 | PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \ |
| 1136 | PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5), |
| 1137 | PINMUX_DATA(LCDD0_MARK, PORT192_FN1), |
| 1138 | PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \ |
| 1139 | PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0, |
| 1140 | MSEL4CR_MSEL20_1), \ |
| 1141 | PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5), |
| 1142 | PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \ |
| 1143 | PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0, |
| 1144 | MSEL4CR_MSEL20_1), \ |
| 1145 | PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5), |
| 1146 | PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \ |
| 1147 | PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0, |
| 1148 | MSEL4CR_MSEL20_1), \ |
| 1149 | PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5), |
| 1150 | PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \ |
| 1151 | PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0, |
| 1152 | MSEL4CR_MSEL20_1), |
| 1153 | PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \ |
| 1154 | PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0, |
| 1155 | MSEL4CR_MSEL20_1), \ |
| 1156 | PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \ |
| 1157 | PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7), |
| 1158 | PINMUX_DATA(LCDD6_MARK, PORT198_FN1), |
| 1159 | PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \ |
| 1160 | PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \ |
| 1161 | PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5), |
| 1162 | PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \ |
| 1163 | PINMUX_DATA(D16_MARK, PORT200_FN6), |
| 1164 | PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \ |
| 1165 | PINMUX_DATA(D17_MARK, PORT201_FN6), |
| 1166 | PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \ |
| 1167 | PINMUX_DATA(D18_MARK, PORT202_FN6), |
| 1168 | PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \ |
| 1169 | PINMUX_DATA(D19_MARK, PORT203_FN6), |
| 1170 | PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \ |
| 1171 | PINMUX_DATA(D20_MARK, PORT204_FN6), |
| 1172 | PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \ |
| 1173 | PINMUX_DATA(D21_MARK, PORT205_FN6), |
| 1174 | PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \ |
| 1175 | PINMUX_DATA(D22_MARK, PORT206_FN6), |
| 1176 | PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \ |
| 1177 | PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \ |
| 1178 | PINMUX_DATA(D23_MARK, PORT207_FN6), |
| 1179 | PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \ |
| 1180 | PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \ |
| 1181 | PINMUX_DATA(D24_MARK, PORT208_FN6), |
| 1182 | PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \ |
| 1183 | PINMUX_DATA(D25_MARK, PORT209_FN6), |
| 1184 | PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \ |
| 1185 | PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \ |
| 1186 | PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \ |
| 1187 | PINMUX_DATA(D26_MARK, PORT210_FN6), |
| 1188 | PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \ |
| 1189 | PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \ |
| 1190 | PINMUX_DATA(D27_MARK, PORT211_FN6), |
| 1191 | PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \ |
| 1192 | PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \ |
| 1193 | PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \ |
| 1194 | PINMUX_DATA(D28_MARK, PORT212_FN6), |
| 1195 | PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \ |
| 1196 | PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \ |
| 1197 | PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \ |
| 1198 | PINMUX_DATA(D29_MARK, PORT213_FN6), |
| 1199 | PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \ |
| 1200 | PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \ |
| 1201 | PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \ |
| 1202 | PINMUX_DATA(D30_MARK, PORT214_FN6), |
| 1203 | PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \ |
| 1204 | PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \ |
| 1205 | PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \ |
| 1206 | PINMUX_DATA(D31_MARK, PORT215_FN6), |
| 1207 | PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \ |
| 1208 | PINMUX_DATA(LCDWR__MARK, PORT216_FN2), |
| 1209 | PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \ |
| 1210 | PINMUX_DATA(DACK2_MARK, PORT217_FN2), \ |
| 1211 | PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \ |
| 1212 | PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \ |
| 1213 | PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1, |
| 1214 | MSEL4CR_MSEL26_1), \ |
| 1215 | PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7), |
| 1216 | PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \ |
| 1217 | PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \ |
| 1218 | PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \ |
| 1219 | PINMUX_DATA(DACK3_MARK, PORT218_FN4), \ |
| 1220 | PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5), |
| 1221 | PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \ |
| 1222 | PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \ |
| 1223 | PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \ |
| 1224 | PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \ |
| 1225 | PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \ |
| 1226 | PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1, |
| 1227 | MSEL4CR_MSEL26_1), \ |
| 1228 | PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7), |
| 1229 | PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \ |
| 1230 | PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2), |
| 1231 | PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \ |
| 1232 | PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \ |
| 1233 | PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \ |
| 1234 | PINMUX_DATA(PWEN_MARK, PORT221_FN4), \ |
| 1235 | PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \ |
| 1236 | PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1, |
| 1237 | MSEL4CR_MSEL26_1), \ |
| 1238 | PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7), |
| 1239 | PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \ |
| 1240 | PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \ |
| 1241 | PINMUX_DATA(DACK1_MARK, PORT222_FN3), \ |
| 1242 | PINMUX_DATA(OVCN_MARK, PORT222_FN4), \ |
| 1243 | PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \ |
| 1244 | PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1, |
| 1245 | MSEL4CR_MSEL26_1), \ |
| 1246 | PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1), |
| 1247 | |
| 1248 | PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \ |
| 1249 | PINMUX_DATA(OVCN2_MARK, PORT225_FN4), |
| 1250 | PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \ |
| 1251 | PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \ |
| 1252 | PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5), |
| 1253 | PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \ |
| 1254 | PINMUX_DATA(IDIN_MARK, PORT227_FN4), |
| 1255 | PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2), |
| 1256 | PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \ |
| 1257 | PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3), |
| 1258 | PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \ |
| 1259 | PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1), |
| 1260 | PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \ |
| 1261 | PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1), |
| 1262 | PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \ |
| 1263 | PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1), |
| 1264 | PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \ |
| 1265 | PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1), |
| 1266 | PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \ |
| 1267 | PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \ |
| 1268 | PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1, |
| 1269 | MSEL4CR_MSEL26_0), \ |
| 1270 | PINMUX_DATA(LCD2D20_MARK, PORT234_FN7), |
| 1271 | PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \ |
| 1272 | PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \ |
| 1273 | PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1, |
| 1274 | MSEL4CR_MSEL26_0), \ |
| 1275 | PINMUX_DATA(LCD2D21_MARK, PORT235_FN7), |
| 1276 | PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \ |
| 1277 | PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0, |
| 1278 | MSEL2CR_MSEL16_0), |
| 1279 | PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \ |
| 1280 | PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0, |
| 1281 | MSEL2CR_MSEL16_0), |
| 1282 | PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \ |
| 1283 | PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1, |
| 1284 | MSEL4CR_MSEL26_0), \ |
| 1285 | PINMUX_DATA(LCD2D22_MARK, PORT238_FN7), |
| 1286 | PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \ |
| 1287 | PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1, |
| 1288 | MSEL4CR_MSEL26_0), \ |
| 1289 | PINMUX_DATA(LCD2D23_MARK, PORT239_FN7), |
| 1290 | PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1), |
| 1291 | PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \ |
| 1292 | PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \ |
| 1293 | PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \ |
| 1294 | PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4), |
| 1295 | PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \ |
| 1296 | PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3), |
| 1297 | PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \ |
| 1298 | PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2), |
| 1299 | PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0, |
| 1300 | MSEL4CR_MSEL20_0), \ |
| 1301 | PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \ |
| 1302 | PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \ |
| 1303 | PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1), |
| 1304 | PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0, |
| 1305 | MSEL4CR_MSEL20_0), \ |
| 1306 | PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \ |
| 1307 | PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \ |
| 1308 | PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1), |
| 1309 | PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0, |
| 1310 | MSEL4CR_MSEL20_0), \ |
| 1311 | PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \ |
| 1312 | PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \ |
| 1313 | PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4), |
| 1314 | PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0, |
| 1315 | MSEL4CR_MSEL20_0), \ |
| 1316 | PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \ |
| 1317 | PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \ |
| 1318 | PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4), |
| 1319 | PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0, |
| 1320 | MSEL4CR_MSEL20_0), \ |
| 1321 | PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \ |
| 1322 | PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \ |
| 1323 | PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \ |
| 1324 | PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0, |
| 1325 | MSEL2CR_MSEL18_0), \ |
| 1326 | PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1), |
| 1327 | PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \ |
| 1328 | PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \ |
| 1329 | PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0, |
| 1330 | MSEL2CR_MSEL18_0), \ |
| 1331 | PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1), |
| 1332 | PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1), |
| 1333 | PINMUX_DATA(SDHICD0_MARK, PORT251_FN1), |
| 1334 | PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1), |
| 1335 | PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1), |
| 1336 | PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1), |
| 1337 | PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1), |
| 1338 | PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1), |
| 1339 | PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1), |
| 1340 | PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1), |
| 1341 | PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \ |
| 1342 | PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3), |
| 1343 | PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \ |
| 1344 | PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3), |
| 1345 | PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \ |
| 1346 | PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3), |
| 1347 | PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \ |
| 1348 | PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3), |
| 1349 | PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1), |
| 1350 | PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1), |
| 1351 | PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \ |
| 1352 | PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3), |
| 1353 | PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \ |
| 1354 | PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3), |
| 1355 | PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \ |
| 1356 | PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3), |
| 1357 | PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \ |
| 1358 | PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3), |
| 1359 | PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1), |
| 1360 | PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0), |
| 1361 | PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, PORT271_IN_PU, |
| 1362 | MSEL4CR_MSEL15_0), |
| 1363 | PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, PORT272_IN_PU, |
| 1364 | MSEL4CR_MSEL15_0), |
| 1365 | PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, PORT273_IN_PU, |
| 1366 | MSEL4CR_MSEL15_0), |
| 1367 | PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, PORT274_IN_PU, |
| 1368 | MSEL4CR_MSEL15_0), |
| 1369 | PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, PORT275_IN_PU, |
| 1370 | MSEL4CR_MSEL15_0), \ |
| 1371 | PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3), |
| 1372 | PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, PORT276_IN_PU, |
| 1373 | MSEL4CR_MSEL15_0), \ |
| 1374 | PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3), |
| 1375 | PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, PORT277_IN_PU, |
| 1376 | MSEL4CR_MSEL15_0), \ |
| 1377 | PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3), |
| 1378 | PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, PORT278_IN_PU, |
| 1379 | MSEL4CR_MSEL15_0), \ |
| 1380 | PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3), |
| 1381 | PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, PORT279_IN_PU, |
| 1382 | MSEL4CR_MSEL15_0), |
| 1383 | PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \ |
| 1384 | PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2), |
| 1385 | PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1), |
| 1386 | PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \ |
| 1387 | PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1), |
| 1388 | PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1), |
| 1389 | PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1), |
| 1390 | PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1), |
| 1391 | PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1), |
| 1392 | PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1), |
| 1393 | PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1), |
| 1394 | PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1), |
| 1395 | PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \ |
| 1396 | PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1), |
| 1397 | PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \ |
| 1398 | PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1), |
| 1399 | |
| 1400 | PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \ |
| 1401 | PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1), |
| 1402 | PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \ |
| 1403 | PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1), |
| 1404 | PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \ |
| 1405 | PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1), |
| 1406 | PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \ |
| 1407 | PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1), |
| 1408 | PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \ |
| 1409 | PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1), |
| 1410 | PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \ |
| 1411 | PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1), |
| 1412 | PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \ |
| 1413 | PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1), |
| 1414 | PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1), |
| 1415 | PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \ |
| 1416 | PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2), |
| 1417 | |
| 1418 | /* MSEL2 special cases */ |
| 1419 | PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0, |
| 1420 | MSEL2CR_MSEL12_0), |
| 1421 | PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0, |
| 1422 | MSEL2CR_MSEL12_1), |
| 1423 | PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1, |
| 1424 | MSEL2CR_MSEL12_0), |
| 1425 | PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1, |
| 1426 | MSEL2CR_MSEL12_1), |
| 1427 | PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0, |
| 1428 | MSEL2CR_MSEL12_0), |
| 1429 | PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0, |
| 1430 | MSEL2CR_MSEL9_0), |
| 1431 | PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0, |
| 1432 | MSEL2CR_MSEL9_1), |
| 1433 | PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1, |
| 1434 | MSEL2CR_MSEL9_0), |
| 1435 | PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1, |
| 1436 | MSEL2CR_MSEL9_1), |
| 1437 | PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0, |
| 1438 | MSEL2CR_MSEL9_0), |
| 1439 | PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0, |
| 1440 | MSEL2CR_MSEL6_0), |
| 1441 | PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0, |
| 1442 | MSEL2CR_MSEL6_1), |
| 1443 | PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1, |
| 1444 | MSEL2CR_MSEL6_0), |
| 1445 | PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1, |
| 1446 | MSEL2CR_MSEL6_1), |
| 1447 | PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0, |
| 1448 | MSEL2CR_MSEL6_0), |
| 1449 | PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0, |
| 1450 | MSEL2CR_MSEL3_0), |
| 1451 | PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0, |
| 1452 | MSEL2CR_MSEL3_1), |
| 1453 | PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1, |
| 1454 | MSEL2CR_MSEL3_0), |
| 1455 | PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1, |
| 1456 | MSEL2CR_MSEL3_1), |
| 1457 | PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0, |
| 1458 | MSEL2CR_MSEL3_0), |
| 1459 | PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0, |
| 1460 | MSEL2CR_MSEL0_0), |
| 1461 | PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0, |
| 1462 | MSEL2CR_MSEL0_1), |
| 1463 | PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1, |
| 1464 | MSEL2CR_MSEL0_0), |
| 1465 | PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1, |
| 1466 | MSEL2CR_MSEL0_1), |
| 1467 | PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0, |
| 1468 | MSEL2CR_MSEL0_0), |
| 1469 | |
| 1470 | /* MSEL3 special cases */ |
| 1471 | PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1), |
| 1472 | PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0), |
| 1473 | PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0), |
| 1474 | PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1), |
| 1475 | PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0), |
| 1476 | PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1), |
| 1477 | |
| 1478 | /* MSEL4 special cases */ |
| 1479 | PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0), |
| 1480 | PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1), |
| 1481 | PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0), |
| 1482 | PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1), |
| 1483 | PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0), |
| 1484 | PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0), |
| 1485 | PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1), |
| 1486 | PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0), |
| 1487 | PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1), |
| 1488 | |
| 1489 | /* Functions with pull-ups */ |
| 1490 | PINMUX_DATA(KEYIN0_PU_MARK, PORT66_FN2, PORT66_IN_PU), |
| 1491 | PINMUX_DATA(KEYIN1_PU_MARK, PORT67_FN2, PORT67_IN_PU), |
| 1492 | PINMUX_DATA(KEYIN2_PU_MARK, PORT68_FN2, PORT68_IN_PU), |
| 1493 | PINMUX_DATA(KEYIN3_PU_MARK, PORT69_FN2, PORT69_IN_PU), |
| 1494 | PINMUX_DATA(KEYIN4_PU_MARK, PORT70_FN2, PORT70_IN_PU), |
| 1495 | PINMUX_DATA(KEYIN5_PU_MARK, PORT71_FN2, PORT71_IN_PU), |
| 1496 | PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU), |
| 1497 | PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU), |
| 1498 | |
| 1499 | PINMUX_DATA(SDHICD0_PU_MARK, PORT251_FN1, PORT251_IN_PU), |
| 1500 | PINMUX_DATA(SDHID0_0_PU_MARK, PORT252_FN1, PORT252_IN_PU), |
| 1501 | PINMUX_DATA(SDHID0_1_PU_MARK, PORT253_FN1, PORT253_IN_PU), |
| 1502 | PINMUX_DATA(SDHID0_2_PU_MARK, PORT254_FN1, PORT254_IN_PU), |
| 1503 | PINMUX_DATA(SDHID0_3_PU_MARK, PORT255_FN1, PORT255_IN_PU), |
| 1504 | PINMUX_DATA(SDHICMD0_PU_MARK, PORT256_FN1, PORT256_IN_PU), |
Guennadi Liakhovetski | 942785d | 2013-02-12 16:34:31 +0100 | [diff] [blame] | 1505 | PINMUX_DATA(SDHIWP0_PU_MARK, PORT257_FN1, PORT257_IN_PU), |
Laurent Pinchart | 5d5166d | 2012-12-15 23:51:24 +0100 | [diff] [blame] | 1506 | PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_FN1, PORT259_IN_PU), |
| 1507 | PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_FN1, PORT260_IN_PU), |
| 1508 | PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_FN1, PORT261_IN_PU), |
| 1509 | PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_FN1, PORT262_IN_PU), |
| 1510 | PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_FN1, PORT263_IN_PU), |
| 1511 | PINMUX_DATA(SDHID2_0_PU_MARK, PORT265_FN1, PORT265_IN_PU), |
| 1512 | PINMUX_DATA(SDHID2_1_PU_MARK, PORT266_FN1, PORT266_IN_PU), |
| 1513 | PINMUX_DATA(SDHID2_2_PU_MARK, PORT267_FN1, PORT267_IN_PU), |
| 1514 | PINMUX_DATA(SDHID2_3_PU_MARK, PORT268_FN1, PORT268_IN_PU), |
| 1515 | PINMUX_DATA(SDHICMD2_PU_MARK, PORT269_FN1, PORT269_IN_PU), |
| 1516 | |
| 1517 | PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU, |
| 1518 | MSEL4CR_MSEL15_0), |
| 1519 | PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU, |
| 1520 | MSEL4CR_MSEL15_1), |
| 1521 | |
| 1522 | PINMUX_DATA(MMCD0_0_PU_MARK, |
| 1523 | PORT271_FN1, PORT271_IN_PU, MSEL4CR_MSEL15_0), |
| 1524 | PINMUX_DATA(MMCD0_1_PU_MARK, |
| 1525 | PORT272_FN1, PORT272_IN_PU, MSEL4CR_MSEL15_0), |
| 1526 | PINMUX_DATA(MMCD0_2_PU_MARK, |
| 1527 | PORT273_FN1, PORT273_IN_PU, MSEL4CR_MSEL15_0), |
| 1528 | PINMUX_DATA(MMCD0_3_PU_MARK, |
| 1529 | PORT274_FN1, PORT274_IN_PU, MSEL4CR_MSEL15_0), |
| 1530 | PINMUX_DATA(MMCD0_4_PU_MARK, |
| 1531 | PORT275_FN1, PORT275_IN_PU, MSEL4CR_MSEL15_0), |
| 1532 | PINMUX_DATA(MMCD0_5_PU_MARK, |
| 1533 | PORT276_FN1, PORT276_IN_PU, MSEL4CR_MSEL15_0), |
| 1534 | PINMUX_DATA(MMCD0_6_PU_MARK, |
| 1535 | PORT277_FN1, PORT277_IN_PU, MSEL4CR_MSEL15_0), |
| 1536 | PINMUX_DATA(MMCD0_7_PU_MARK, |
| 1537 | PORT278_FN1, PORT278_IN_PU, MSEL4CR_MSEL15_0), |
| 1538 | |
| 1539 | PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU), |
| 1540 | PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU), |
| 1541 | PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU), |
| 1542 | PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU), |
| 1543 | PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU), |
| 1544 | }; |
| 1545 | |
Laurent Pinchart | b823899 | 2013-03-13 01:31:23 +0100 | [diff] [blame^] | 1546 | #define SH73A0_PIN(pin, cfgs) \ |
| 1547 | { \ |
| 1548 | .name = __stringify(PORT##pin), \ |
| 1549 | .enum_id = PORT##pin##_DATA, \ |
| 1550 | .configs = cfgs, \ |
| 1551 | } |
| 1552 | |
| 1553 | #define __I (SH_PFC_PIN_CFG_INPUT) |
| 1554 | #define __O (SH_PFC_PIN_CFG_OUTPUT) |
| 1555 | #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) |
| 1556 | #define __PD (SH_PFC_PIN_CFG_PULL_DOWN) |
| 1557 | #define __PU (SH_PFC_PIN_CFG_PULL_UP) |
| 1558 | #define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) |
| 1559 | |
| 1560 | #define SH73A0_PIN_I_PD(pin) SH73A0_PIN(pin, __I | __PD) |
| 1561 | #define SH73A0_PIN_I_PU(pin) SH73A0_PIN(pin, __I | __PU) |
| 1562 | #define SH73A0_PIN_I_PU_PD(pin) SH73A0_PIN(pin, __I | __PUD) |
| 1563 | #define SH73A0_PIN_IO(pin) SH73A0_PIN(pin, __IO) |
| 1564 | #define SH73A0_PIN_IO_PD(pin) SH73A0_PIN(pin, __IO | __PD) |
| 1565 | #define SH73A0_PIN_IO_PU(pin) SH73A0_PIN(pin, __IO | __PU) |
| 1566 | #define SH73A0_PIN_IO_PU_PD(pin) SH73A0_PIN(pin, __IO | __PUD) |
| 1567 | #define SH73A0_PIN_O(pin) SH73A0_PIN(pin, __O) |
| 1568 | |
Laurent Pinchart | a3db40a6 | 2013-01-02 14:53:37 +0100 | [diff] [blame] | 1569 | static struct sh_pfc_pin pinmux_pins[] = { |
Laurent Pinchart | b823899 | 2013-03-13 01:31:23 +0100 | [diff] [blame^] | 1570 | /* Table 25-1 (I/O and Pull U/D) */ |
| 1571 | SH73A0_PIN_I_PD(0), |
| 1572 | SH73A0_PIN_I_PU(1), |
| 1573 | SH73A0_PIN_I_PU(2), |
| 1574 | SH73A0_PIN_I_PU(3), |
| 1575 | SH73A0_PIN_I_PU(4), |
| 1576 | SH73A0_PIN_I_PU(5), |
| 1577 | SH73A0_PIN_I_PU(6), |
| 1578 | SH73A0_PIN_I_PU(7), |
| 1579 | SH73A0_PIN_I_PU(8), |
| 1580 | SH73A0_PIN_I_PD(9), |
| 1581 | SH73A0_PIN_I_PD(10), |
| 1582 | SH73A0_PIN_I_PU_PD(11), |
| 1583 | SH73A0_PIN_IO_PU_PD(12), |
| 1584 | SH73A0_PIN_IO_PU_PD(13), |
| 1585 | SH73A0_PIN_IO_PU_PD(14), |
| 1586 | SH73A0_PIN_IO_PU_PD(15), |
| 1587 | SH73A0_PIN_IO_PD(16), |
| 1588 | SH73A0_PIN_IO_PD(17), |
| 1589 | SH73A0_PIN_IO_PU(18), |
| 1590 | SH73A0_PIN_IO_PU(19), |
| 1591 | SH73A0_PIN_O(20), |
| 1592 | SH73A0_PIN_O(21), |
| 1593 | SH73A0_PIN_O(22), |
| 1594 | SH73A0_PIN_O(23), |
| 1595 | SH73A0_PIN_O(24), |
| 1596 | SH73A0_PIN_I_PD(25), |
| 1597 | SH73A0_PIN_I_PD(26), |
| 1598 | SH73A0_PIN_IO_PU(27), |
| 1599 | SH73A0_PIN_IO_PU(28), |
| 1600 | SH73A0_PIN_IO_PD(29), |
| 1601 | SH73A0_PIN_IO_PD(30), |
| 1602 | SH73A0_PIN_IO_PU(31), |
| 1603 | SH73A0_PIN_IO_PD(32), |
| 1604 | SH73A0_PIN_I_PU_PD(33), |
| 1605 | SH73A0_PIN_IO_PD(34), |
| 1606 | SH73A0_PIN_I_PU_PD(35), |
| 1607 | SH73A0_PIN_IO_PD(36), |
| 1608 | SH73A0_PIN_IO(37), |
| 1609 | SH73A0_PIN_O(38), |
| 1610 | SH73A0_PIN_I_PU(39), |
| 1611 | SH73A0_PIN_I_PU_PD(40), |
| 1612 | SH73A0_PIN_O(41), |
| 1613 | SH73A0_PIN_IO_PD(42), |
| 1614 | SH73A0_PIN_IO_PU_PD(43), |
| 1615 | SH73A0_PIN_IO_PU_PD(44), |
| 1616 | SH73A0_PIN_IO_PD(45), |
| 1617 | SH73A0_PIN_IO_PD(46), |
| 1618 | SH73A0_PIN_IO_PD(47), |
| 1619 | SH73A0_PIN_I_PD(48), |
| 1620 | SH73A0_PIN_IO_PU_PD(49), |
| 1621 | SH73A0_PIN_IO_PD(50), |
| 1622 | SH73A0_PIN_IO_PD(51), |
| 1623 | SH73A0_PIN_O(52), |
| 1624 | SH73A0_PIN_IO_PU_PD(53), |
| 1625 | SH73A0_PIN_IO_PU_PD(54), |
| 1626 | SH73A0_PIN_IO_PD(55), |
| 1627 | SH73A0_PIN_I_PU_PD(56), |
| 1628 | SH73A0_PIN_IO(57), |
| 1629 | SH73A0_PIN_IO(58), |
| 1630 | SH73A0_PIN_IO(59), |
| 1631 | SH73A0_PIN_IO(60), |
| 1632 | SH73A0_PIN_IO(61), |
| 1633 | SH73A0_PIN_IO_PD(62), |
| 1634 | SH73A0_PIN_IO_PD(63), |
| 1635 | SH73A0_PIN_IO_PU_PD(64), |
| 1636 | SH73A0_PIN_IO_PD(65), |
| 1637 | SH73A0_PIN_IO_PU_PD(66), |
| 1638 | SH73A0_PIN_IO_PU_PD(67), |
| 1639 | SH73A0_PIN_IO_PU_PD(68), |
| 1640 | SH73A0_PIN_IO_PU_PD(69), |
| 1641 | SH73A0_PIN_IO_PU_PD(70), |
| 1642 | SH73A0_PIN_IO_PU_PD(71), |
| 1643 | SH73A0_PIN_IO_PU_PD(72), |
| 1644 | SH73A0_PIN_I_PU_PD(73), |
| 1645 | SH73A0_PIN_IO_PU(74), |
| 1646 | SH73A0_PIN_IO_PU(75), |
| 1647 | SH73A0_PIN_IO_PU(76), |
| 1648 | SH73A0_PIN_IO_PU(77), |
| 1649 | SH73A0_PIN_IO_PU(78), |
| 1650 | SH73A0_PIN_IO_PU(79), |
| 1651 | SH73A0_PIN_IO_PU(80), |
| 1652 | SH73A0_PIN_IO_PU(81), |
| 1653 | SH73A0_PIN_IO_PU(82), |
| 1654 | SH73A0_PIN_IO_PU(83), |
| 1655 | SH73A0_PIN_IO_PU(84), |
| 1656 | SH73A0_PIN_IO_PU(85), |
| 1657 | SH73A0_PIN_IO_PU(86), |
| 1658 | SH73A0_PIN_IO_PU(87), |
| 1659 | SH73A0_PIN_IO_PU(88), |
| 1660 | SH73A0_PIN_IO_PU(89), |
| 1661 | SH73A0_PIN_O(90), |
| 1662 | SH73A0_PIN_IO_PU(91), |
| 1663 | SH73A0_PIN_O(92), |
| 1664 | SH73A0_PIN_IO_PU(93), |
| 1665 | SH73A0_PIN_O(94), |
| 1666 | SH73A0_PIN_I_PU_PD(95), |
| 1667 | SH73A0_PIN_IO(96), |
| 1668 | SH73A0_PIN_IO(97), |
| 1669 | SH73A0_PIN_IO(98), |
| 1670 | SH73A0_PIN_I_PU(99), |
| 1671 | SH73A0_PIN_O(100), |
| 1672 | SH73A0_PIN_O(101), |
| 1673 | SH73A0_PIN_I_PU(102), |
| 1674 | SH73A0_PIN_IO_PD(103), |
| 1675 | SH73A0_PIN_I_PU_PD(104), |
| 1676 | SH73A0_PIN_I_PD(105), |
| 1677 | SH73A0_PIN_I_PD(106), |
| 1678 | SH73A0_PIN_I_PU_PD(107), |
| 1679 | SH73A0_PIN_I_PU_PD(108), |
| 1680 | SH73A0_PIN_IO_PD(109), |
| 1681 | SH73A0_PIN_IO_PD(110), |
| 1682 | SH73A0_PIN_IO_PU_PD(111), |
| 1683 | SH73A0_PIN_IO_PU_PD(112), |
| 1684 | SH73A0_PIN_IO_PU_PD(113), |
| 1685 | SH73A0_PIN_IO_PD(114), |
| 1686 | SH73A0_PIN_IO_PU(115), |
| 1687 | SH73A0_PIN_IO_PU(116), |
| 1688 | SH73A0_PIN_IO_PU_PD(117), |
| 1689 | SH73A0_PIN_IO_PU_PD(118), |
| 1690 | SH73A0_PIN_IO_PD(128), |
| 1691 | SH73A0_PIN_IO_PD(129), |
| 1692 | SH73A0_PIN_IO_PU_PD(130), |
| 1693 | SH73A0_PIN_IO_PD(131), |
| 1694 | SH73A0_PIN_IO_PD(132), |
| 1695 | SH73A0_PIN_IO_PD(133), |
| 1696 | SH73A0_PIN_IO_PU_PD(134), |
| 1697 | SH73A0_PIN_IO_PU_PD(135), |
| 1698 | SH73A0_PIN_IO_PU_PD(136), |
| 1699 | SH73A0_PIN_IO_PU_PD(137), |
| 1700 | SH73A0_PIN_IO_PD(138), |
| 1701 | SH73A0_PIN_IO_PD(139), |
| 1702 | SH73A0_PIN_IO_PD(140), |
| 1703 | SH73A0_PIN_IO_PD(141), |
| 1704 | SH73A0_PIN_IO_PD(142), |
| 1705 | SH73A0_PIN_IO_PD(143), |
| 1706 | SH73A0_PIN_IO_PU_PD(144), |
| 1707 | SH73A0_PIN_IO_PD(145), |
| 1708 | SH73A0_PIN_IO_PU_PD(146), |
| 1709 | SH73A0_PIN_IO_PU_PD(147), |
| 1710 | SH73A0_PIN_IO_PU_PD(148), |
| 1711 | SH73A0_PIN_IO_PU_PD(149), |
| 1712 | SH73A0_PIN_I_PU_PD(150), |
| 1713 | SH73A0_PIN_IO_PU_PD(151), |
| 1714 | SH73A0_PIN_IO_PU_PD(152), |
| 1715 | SH73A0_PIN_IO_PD(153), |
| 1716 | SH73A0_PIN_IO_PD(154), |
| 1717 | SH73A0_PIN_I_PU_PD(155), |
| 1718 | SH73A0_PIN_IO_PU_PD(156), |
| 1719 | SH73A0_PIN_I_PD(157), |
| 1720 | SH73A0_PIN_IO_PD(158), |
| 1721 | SH73A0_PIN_IO_PU_PD(159), |
| 1722 | SH73A0_PIN_IO_PU_PD(160), |
| 1723 | SH73A0_PIN_I_PU_PD(161), |
| 1724 | SH73A0_PIN_I_PU_PD(162), |
| 1725 | SH73A0_PIN_IO_PU_PD(163), |
| 1726 | SH73A0_PIN_I_PU_PD(164), |
| 1727 | SH73A0_PIN_IO_PD(192), |
| 1728 | SH73A0_PIN_IO_PU_PD(193), |
| 1729 | SH73A0_PIN_IO_PD(194), |
| 1730 | SH73A0_PIN_IO_PU_PD(195), |
| 1731 | SH73A0_PIN_IO_PD(196), |
| 1732 | SH73A0_PIN_IO_PD(197), |
| 1733 | SH73A0_PIN_IO_PD(198), |
| 1734 | SH73A0_PIN_IO_PD(199), |
| 1735 | SH73A0_PIN_IO_PU_PD(200), |
| 1736 | SH73A0_PIN_IO_PU_PD(201), |
| 1737 | SH73A0_PIN_IO_PU_PD(202), |
| 1738 | SH73A0_PIN_IO_PU_PD(203), |
| 1739 | SH73A0_PIN_IO_PU_PD(204), |
| 1740 | SH73A0_PIN_IO_PU_PD(205), |
| 1741 | SH73A0_PIN_IO_PU_PD(206), |
| 1742 | SH73A0_PIN_IO_PD(207), |
| 1743 | SH73A0_PIN_IO_PD(208), |
| 1744 | SH73A0_PIN_IO_PD(209), |
| 1745 | SH73A0_PIN_IO_PD(210), |
| 1746 | SH73A0_PIN_IO_PD(211), |
| 1747 | SH73A0_PIN_IO_PD(212), |
| 1748 | SH73A0_PIN_IO_PD(213), |
| 1749 | SH73A0_PIN_IO_PU_PD(214), |
| 1750 | SH73A0_PIN_IO_PU_PD(215), |
| 1751 | SH73A0_PIN_IO_PD(216), |
| 1752 | SH73A0_PIN_IO_PD(217), |
| 1753 | SH73A0_PIN_O(218), |
| 1754 | SH73A0_PIN_IO_PD(219), |
| 1755 | SH73A0_PIN_IO_PD(220), |
| 1756 | SH73A0_PIN_IO_PU_PD(221), |
| 1757 | SH73A0_PIN_IO_PU_PD(222), |
| 1758 | SH73A0_PIN_I_PU_PD(223), |
| 1759 | SH73A0_PIN_I_PU_PD(224), |
| 1760 | SH73A0_PIN_IO_PU_PD(225), |
| 1761 | SH73A0_PIN_O(226), |
| 1762 | SH73A0_PIN_IO_PU_PD(227), |
| 1763 | SH73A0_PIN_I_PU_PD(228), |
| 1764 | SH73A0_PIN_I_PD(229), |
| 1765 | SH73A0_PIN_IO(230), |
| 1766 | SH73A0_PIN_IO_PU_PD(231), |
| 1767 | SH73A0_PIN_IO_PU_PD(232), |
| 1768 | SH73A0_PIN_I_PU_PD(233), |
| 1769 | SH73A0_PIN_IO_PU_PD(234), |
| 1770 | SH73A0_PIN_IO_PU_PD(235), |
| 1771 | SH73A0_PIN_IO_PU_PD(236), |
| 1772 | SH73A0_PIN_IO_PD(237), |
| 1773 | SH73A0_PIN_IO_PU_PD(238), |
| 1774 | SH73A0_PIN_IO_PU_PD(239), |
| 1775 | SH73A0_PIN_IO_PU_PD(240), |
| 1776 | SH73A0_PIN_O(241), |
| 1777 | SH73A0_PIN_I_PD(242), |
| 1778 | SH73A0_PIN_IO_PU_PD(243), |
| 1779 | SH73A0_PIN_IO_PU_PD(244), |
| 1780 | SH73A0_PIN_IO_PU_PD(245), |
| 1781 | SH73A0_PIN_IO_PU_PD(246), |
| 1782 | SH73A0_PIN_IO_PU_PD(247), |
| 1783 | SH73A0_PIN_IO_PU_PD(248), |
| 1784 | SH73A0_PIN_IO_PU_PD(249), |
| 1785 | SH73A0_PIN_IO_PU_PD(250), |
| 1786 | SH73A0_PIN_IO_PU_PD(251), |
| 1787 | SH73A0_PIN_IO_PU_PD(252), |
| 1788 | SH73A0_PIN_IO_PU_PD(253), |
| 1789 | SH73A0_PIN_IO_PU_PD(254), |
| 1790 | SH73A0_PIN_IO_PU_PD(255), |
| 1791 | SH73A0_PIN_IO_PU_PD(256), |
| 1792 | SH73A0_PIN_IO_PU_PD(257), |
| 1793 | SH73A0_PIN_IO_PU_PD(258), |
| 1794 | SH73A0_PIN_IO_PU_PD(259), |
| 1795 | SH73A0_PIN_IO_PU_PD(260), |
| 1796 | SH73A0_PIN_IO_PU_PD(261), |
| 1797 | SH73A0_PIN_IO_PU_PD(262), |
| 1798 | SH73A0_PIN_IO_PU_PD(263), |
| 1799 | SH73A0_PIN_IO_PU_PD(264), |
| 1800 | SH73A0_PIN_IO_PU_PD(265), |
| 1801 | SH73A0_PIN_IO_PU_PD(266), |
| 1802 | SH73A0_PIN_IO_PU_PD(267), |
| 1803 | SH73A0_PIN_IO_PU_PD(268), |
| 1804 | SH73A0_PIN_IO_PU_PD(269), |
| 1805 | SH73A0_PIN_IO_PU_PD(270), |
| 1806 | SH73A0_PIN_IO_PU_PD(271), |
| 1807 | SH73A0_PIN_IO_PU_PD(272), |
| 1808 | SH73A0_PIN_IO_PU_PD(273), |
| 1809 | SH73A0_PIN_IO_PU_PD(274), |
| 1810 | SH73A0_PIN_IO_PU_PD(275), |
| 1811 | SH73A0_PIN_IO_PU_PD(276), |
| 1812 | SH73A0_PIN_IO_PU_PD(277), |
| 1813 | SH73A0_PIN_IO_PU_PD(278), |
| 1814 | SH73A0_PIN_IO_PU_PD(279), |
| 1815 | SH73A0_PIN_IO_PU_PD(280), |
| 1816 | SH73A0_PIN_O(281), |
| 1817 | SH73A0_PIN_O(282), |
| 1818 | SH73A0_PIN_I_PU(288), |
| 1819 | SH73A0_PIN_IO_PU_PD(289), |
| 1820 | SH73A0_PIN_IO_PU_PD(290), |
| 1821 | SH73A0_PIN_IO_PU_PD(291), |
| 1822 | SH73A0_PIN_IO_PU_PD(292), |
| 1823 | SH73A0_PIN_IO_PU_PD(293), |
| 1824 | SH73A0_PIN_IO_PU_PD(294), |
| 1825 | SH73A0_PIN_IO_PU_PD(295), |
| 1826 | SH73A0_PIN_IO_PU_PD(296), |
| 1827 | SH73A0_PIN_IO_PU_PD(297), |
| 1828 | SH73A0_PIN_IO_PU_PD(298), |
| 1829 | SH73A0_PIN_IO_PU_PD(299), |
| 1830 | SH73A0_PIN_IO_PU_PD(300), |
| 1831 | SH73A0_PIN_IO_PU_PD(301), |
| 1832 | SH73A0_PIN_IO_PU_PD(302), |
| 1833 | SH73A0_PIN_IO_PU_PD(303), |
| 1834 | SH73A0_PIN_IO_PU_PD(304), |
| 1835 | SH73A0_PIN_IO_PU_PD(305), |
| 1836 | SH73A0_PIN_O(306), |
| 1837 | SH73A0_PIN_O(307), |
| 1838 | SH73A0_PIN_I_PU(308), |
| 1839 | SH73A0_PIN_O(309), |
Laurent Pinchart | a373ed0 | 2012-11-29 13:24:07 +0100 | [diff] [blame] | 1840 | }; |
Laurent Pinchart | 5d5166d | 2012-12-15 23:51:24 +0100 | [diff] [blame] | 1841 | |
Laurent Pinchart | cd3c1be | 2013-02-16 18:47:05 +0100 | [diff] [blame] | 1842 | static const struct pinmux_range pinmux_ranges[] = { |
Guennadi Liakhovetski | b58e5fa | 2013-02-12 16:50:02 +0100 | [diff] [blame] | 1843 | {.begin = 0, .end = 118,}, |
| 1844 | {.begin = 128, .end = 164,}, |
| 1845 | {.begin = 192, .end = 282,}, |
| 1846 | {.begin = 288, .end = 309,}, |
| 1847 | }; |
| 1848 | |
| 1849 | #define PINMUX_FN_BASE GPIO_FN_VBUS_0 |
Laurent Pinchart | a373ed0 | 2012-11-29 13:24:07 +0100 | [diff] [blame] | 1850 | |
Laurent Pinchart | cd3c1be | 2013-02-16 18:47:05 +0100 | [diff] [blame] | 1851 | static const struct pinmux_func pinmux_func_gpios[] = { |
Laurent Pinchart | 5d5166d | 2012-12-15 23:51:24 +0100 | [diff] [blame] | 1852 | /* Table 25-1 (Functions 0-7) */ |
| 1853 | GPIO_FN(VBUS_0), |
| 1854 | GPIO_FN(GPI0), |
| 1855 | GPIO_FN(GPI1), |
| 1856 | GPIO_FN(GPI2), |
| 1857 | GPIO_FN(GPI3), |
| 1858 | GPIO_FN(GPI4), |
| 1859 | GPIO_FN(GPI5), |
| 1860 | GPIO_FN(GPI6), |
| 1861 | GPIO_FN(GPI7), |
| 1862 | GPIO_FN(SCIFA7_RXD), |
| 1863 | GPIO_FN(SCIFA7_CTS_), |
| 1864 | GPIO_FN(GPO7), \ |
| 1865 | GPIO_FN(MFG0_OUT2), |
| 1866 | GPIO_FN(GPO6), \ |
| 1867 | GPIO_FN(MFG1_OUT2), |
| 1868 | GPIO_FN(GPO5), \ |
| 1869 | GPIO_FN(SCIFA0_SCK), \ |
| 1870 | GPIO_FN(FSICOSLDT3), \ |
| 1871 | GPIO_FN(PORT16_VIO_CKOR), |
| 1872 | GPIO_FN(SCIFA0_TXD), |
| 1873 | GPIO_FN(SCIFA7_TXD), |
| 1874 | GPIO_FN(SCIFA7_RTS_), \ |
| 1875 | GPIO_FN(PORT19_VIO_CKO2), |
| 1876 | GPIO_FN(GPO0), |
| 1877 | GPIO_FN(GPO1), |
| 1878 | GPIO_FN(GPO2), \ |
| 1879 | GPIO_FN(STATUS0), |
| 1880 | GPIO_FN(GPO3), \ |
| 1881 | GPIO_FN(STATUS1), |
| 1882 | GPIO_FN(GPO4), \ |
| 1883 | GPIO_FN(STATUS2), |
| 1884 | GPIO_FN(VINT), |
| 1885 | GPIO_FN(TCKON), |
| 1886 | GPIO_FN(XDVFS1), \ |
| 1887 | GPIO_FN(PORT27_I2C_SCL2), \ |
| 1888 | GPIO_FN(PORT27_I2C_SCL3), \ |
| 1889 | GPIO_FN(MFG0_OUT1), \ |
| 1890 | GPIO_FN(PORT27_IROUT), |
| 1891 | GPIO_FN(XDVFS2), \ |
| 1892 | GPIO_FN(PORT28_I2C_SDA2), \ |
| 1893 | GPIO_FN(PORT28_I2C_SDA3), \ |
| 1894 | GPIO_FN(PORT28_TPU1TO1), |
| 1895 | GPIO_FN(SIM_RST), \ |
| 1896 | GPIO_FN(PORT29_TPU1TO1), |
| 1897 | GPIO_FN(SIM_CLK), \ |
| 1898 | GPIO_FN(PORT30_VIO_CKOR), |
| 1899 | GPIO_FN(SIM_D), \ |
| 1900 | GPIO_FN(PORT31_IROUT), |
| 1901 | GPIO_FN(SCIFA4_TXD), |
| 1902 | GPIO_FN(SCIFA4_RXD), \ |
| 1903 | GPIO_FN(XWUP), |
| 1904 | GPIO_FN(SCIFA4_RTS_), |
| 1905 | GPIO_FN(SCIFA4_CTS_), |
| 1906 | GPIO_FN(FSIBOBT), \ |
| 1907 | GPIO_FN(FSIBIBT), |
| 1908 | GPIO_FN(FSIBOLR), \ |
| 1909 | GPIO_FN(FSIBILR), |
| 1910 | GPIO_FN(FSIBOSLD), |
| 1911 | GPIO_FN(FSIBISLD), |
| 1912 | GPIO_FN(VACK), |
| 1913 | GPIO_FN(XTAL1L), |
| 1914 | GPIO_FN(SCIFA0_RTS_), \ |
| 1915 | GPIO_FN(FSICOSLDT2), |
| 1916 | GPIO_FN(SCIFA0_RXD), |
| 1917 | GPIO_FN(SCIFA0_CTS_), \ |
| 1918 | GPIO_FN(FSICOSLDT1), |
| 1919 | GPIO_FN(FSICOBT), \ |
| 1920 | GPIO_FN(FSICIBT), \ |
| 1921 | GPIO_FN(FSIDOBT), \ |
| 1922 | GPIO_FN(FSIDIBT), |
| 1923 | GPIO_FN(FSICOLR), \ |
| 1924 | GPIO_FN(FSICILR), \ |
| 1925 | GPIO_FN(FSIDOLR), \ |
| 1926 | GPIO_FN(FSIDILR), |
| 1927 | GPIO_FN(FSICOSLD), \ |
| 1928 | GPIO_FN(PORT47_FSICSPDIF), |
| 1929 | GPIO_FN(FSICISLD), \ |
| 1930 | GPIO_FN(FSIDISLD), |
| 1931 | GPIO_FN(FSIACK), \ |
| 1932 | GPIO_FN(PORT49_IRDA_OUT), \ |
| 1933 | GPIO_FN(PORT49_IROUT), \ |
| 1934 | GPIO_FN(FSIAOMC), |
| 1935 | GPIO_FN(FSIAOLR), \ |
| 1936 | GPIO_FN(BBIF2_TSYNC2), \ |
| 1937 | GPIO_FN(TPU2TO2), \ |
| 1938 | GPIO_FN(FSIAILR), |
| 1939 | |
| 1940 | GPIO_FN(FSIAOBT), \ |
| 1941 | GPIO_FN(BBIF2_TSCK2), \ |
| 1942 | GPIO_FN(TPU2TO3), \ |
| 1943 | GPIO_FN(FSIAIBT), |
| 1944 | GPIO_FN(FSIAOSLD), \ |
| 1945 | GPIO_FN(BBIF2_TXD2), |
| 1946 | GPIO_FN(FSIASPDIF), \ |
| 1947 | GPIO_FN(PORT53_IRDA_IN), \ |
| 1948 | GPIO_FN(TPU3TO3), \ |
| 1949 | GPIO_FN(FSIBSPDIF), \ |
| 1950 | GPIO_FN(PORT53_FSICSPDIF), |
| 1951 | GPIO_FN(FSIBCK), \ |
| 1952 | GPIO_FN(PORT54_IRDA_FIRSEL), \ |
| 1953 | GPIO_FN(TPU3TO2), \ |
| 1954 | GPIO_FN(FSIBOMC), \ |
| 1955 | GPIO_FN(FSICCK), \ |
| 1956 | GPIO_FN(FSICOMC), |
| 1957 | GPIO_FN(FSIAISLD), \ |
| 1958 | GPIO_FN(TPU0TO0), |
| 1959 | GPIO_FN(A0), \ |
| 1960 | GPIO_FN(BS_), |
| 1961 | GPIO_FN(A12), \ |
| 1962 | GPIO_FN(PORT58_KEYOUT7), \ |
| 1963 | GPIO_FN(TPU4TO2), |
| 1964 | GPIO_FN(A13), \ |
| 1965 | GPIO_FN(PORT59_KEYOUT6), \ |
| 1966 | GPIO_FN(TPU0TO1), |
| 1967 | GPIO_FN(A14), \ |
| 1968 | GPIO_FN(KEYOUT5), |
| 1969 | GPIO_FN(A15), \ |
| 1970 | GPIO_FN(KEYOUT4), |
| 1971 | GPIO_FN(A16), \ |
| 1972 | GPIO_FN(KEYOUT3), \ |
| 1973 | GPIO_FN(MSIOF0_SS1), |
| 1974 | GPIO_FN(A17), \ |
| 1975 | GPIO_FN(KEYOUT2), \ |
| 1976 | GPIO_FN(MSIOF0_TSYNC), |
| 1977 | GPIO_FN(A18), \ |
| 1978 | GPIO_FN(KEYOUT1), \ |
| 1979 | GPIO_FN(MSIOF0_TSCK), |
| 1980 | GPIO_FN(A19), \ |
| 1981 | GPIO_FN(KEYOUT0), \ |
| 1982 | GPIO_FN(MSIOF0_TXD), |
| 1983 | GPIO_FN(A20), \ |
| 1984 | GPIO_FN(KEYIN0), \ |
| 1985 | GPIO_FN(MSIOF0_RSCK), |
| 1986 | GPIO_FN(A21), \ |
| 1987 | GPIO_FN(KEYIN1), \ |
| 1988 | GPIO_FN(MSIOF0_RSYNC), |
| 1989 | GPIO_FN(A22), \ |
| 1990 | GPIO_FN(KEYIN2), \ |
| 1991 | GPIO_FN(MSIOF0_MCK0), |
| 1992 | GPIO_FN(A23), \ |
| 1993 | GPIO_FN(KEYIN3), \ |
| 1994 | GPIO_FN(MSIOF0_MCK1), |
| 1995 | GPIO_FN(A24), \ |
| 1996 | GPIO_FN(KEYIN4), \ |
| 1997 | GPIO_FN(MSIOF0_RXD), |
| 1998 | GPIO_FN(A25), \ |
| 1999 | GPIO_FN(KEYIN5), \ |
| 2000 | GPIO_FN(MSIOF0_SS2), |
| 2001 | GPIO_FN(A26), \ |
| 2002 | GPIO_FN(KEYIN6), |
| 2003 | GPIO_FN(KEYIN7), |
| 2004 | GPIO_FN(D0_NAF0), |
| 2005 | GPIO_FN(D1_NAF1), |
| 2006 | GPIO_FN(D2_NAF2), |
| 2007 | GPIO_FN(D3_NAF3), |
| 2008 | GPIO_FN(D4_NAF4), |
| 2009 | GPIO_FN(D5_NAF5), |
| 2010 | GPIO_FN(D6_NAF6), |
| 2011 | GPIO_FN(D7_NAF7), |
| 2012 | GPIO_FN(D8_NAF8), |
| 2013 | GPIO_FN(D9_NAF9), |
| 2014 | GPIO_FN(D10_NAF10), |
| 2015 | GPIO_FN(D11_NAF11), |
| 2016 | GPIO_FN(D12_NAF12), |
| 2017 | GPIO_FN(D13_NAF13), |
| 2018 | GPIO_FN(D14_NAF14), |
| 2019 | GPIO_FN(D15_NAF15), |
| 2020 | GPIO_FN(CS4_), |
| 2021 | GPIO_FN(CS5A_), \ |
| 2022 | GPIO_FN(PORT91_RDWR), |
| 2023 | GPIO_FN(CS5B_), \ |
| 2024 | GPIO_FN(FCE1_), |
| 2025 | GPIO_FN(CS6B_), \ |
| 2026 | GPIO_FN(DACK0), |
| 2027 | GPIO_FN(FCE0_), \ |
| 2028 | GPIO_FN(CS6A_), |
| 2029 | GPIO_FN(WAIT_), \ |
| 2030 | GPIO_FN(DREQ0), |
| 2031 | GPIO_FN(RD__FSC), |
| 2032 | GPIO_FN(WE0__FWE), \ |
| 2033 | GPIO_FN(RDWR_FWE), |
| 2034 | GPIO_FN(WE1_), |
| 2035 | GPIO_FN(FRB), |
| 2036 | GPIO_FN(CKO), |
| 2037 | GPIO_FN(NBRSTOUT_), |
| 2038 | GPIO_FN(NBRST_), |
| 2039 | GPIO_FN(BBIF2_TXD), |
| 2040 | GPIO_FN(BBIF2_RXD), |
| 2041 | GPIO_FN(BBIF2_SYNC), |
| 2042 | GPIO_FN(BBIF2_SCK), |
| 2043 | GPIO_FN(SCIFA3_CTS_), \ |
| 2044 | GPIO_FN(MFG3_IN2), |
| 2045 | GPIO_FN(SCIFA3_RXD), \ |
| 2046 | GPIO_FN(MFG3_IN1), |
| 2047 | GPIO_FN(BBIF1_SS2), \ |
| 2048 | GPIO_FN(SCIFA3_RTS_), \ |
| 2049 | GPIO_FN(MFG3_OUT1), |
| 2050 | GPIO_FN(SCIFA3_TXD), |
| 2051 | GPIO_FN(HSI_RX_DATA), \ |
| 2052 | GPIO_FN(BBIF1_RXD), |
| 2053 | GPIO_FN(HSI_TX_WAKE), \ |
| 2054 | GPIO_FN(BBIF1_TSCK), |
| 2055 | GPIO_FN(HSI_TX_DATA), \ |
| 2056 | GPIO_FN(BBIF1_TSYNC), |
| 2057 | GPIO_FN(HSI_TX_READY), \ |
| 2058 | GPIO_FN(BBIF1_TXD), |
| 2059 | GPIO_FN(HSI_RX_READY), \ |
| 2060 | GPIO_FN(BBIF1_RSCK), \ |
| 2061 | GPIO_FN(PORT115_I2C_SCL2), \ |
| 2062 | GPIO_FN(PORT115_I2C_SCL3), |
| 2063 | GPIO_FN(HSI_RX_WAKE), \ |
| 2064 | GPIO_FN(BBIF1_RSYNC), \ |
| 2065 | GPIO_FN(PORT116_I2C_SDA2), \ |
| 2066 | GPIO_FN(PORT116_I2C_SDA3), |
| 2067 | GPIO_FN(HSI_RX_FLAG), \ |
| 2068 | GPIO_FN(BBIF1_SS1), \ |
| 2069 | GPIO_FN(BBIF1_FLOW), |
| 2070 | GPIO_FN(HSI_TX_FLAG), |
| 2071 | GPIO_FN(VIO_VD), \ |
| 2072 | GPIO_FN(PORT128_LCD2VSYN), \ |
| 2073 | GPIO_FN(VIO2_VD), \ |
| 2074 | GPIO_FN(LCD2D0), |
| 2075 | |
| 2076 | GPIO_FN(VIO_HD), \ |
| 2077 | GPIO_FN(PORT129_LCD2HSYN), \ |
| 2078 | GPIO_FN(PORT129_LCD2CS_), \ |
| 2079 | GPIO_FN(VIO2_HD), \ |
| 2080 | GPIO_FN(LCD2D1), |
| 2081 | GPIO_FN(VIO_D0), \ |
| 2082 | GPIO_FN(PORT130_MSIOF2_RXD), \ |
| 2083 | GPIO_FN(LCD2D10), |
| 2084 | GPIO_FN(VIO_D1), \ |
| 2085 | GPIO_FN(PORT131_KEYOUT6), \ |
| 2086 | GPIO_FN(PORT131_MSIOF2_SS1), \ |
| 2087 | GPIO_FN(PORT131_KEYOUT11), \ |
| 2088 | GPIO_FN(LCD2D11), |
| 2089 | GPIO_FN(VIO_D2), \ |
| 2090 | GPIO_FN(PORT132_KEYOUT7), \ |
| 2091 | GPIO_FN(PORT132_MSIOF2_SS2), \ |
| 2092 | GPIO_FN(PORT132_KEYOUT10), \ |
| 2093 | GPIO_FN(LCD2D12), |
| 2094 | GPIO_FN(VIO_D3), \ |
| 2095 | GPIO_FN(MSIOF2_TSYNC), \ |
| 2096 | GPIO_FN(LCD2D13), |
| 2097 | GPIO_FN(VIO_D4), \ |
| 2098 | GPIO_FN(MSIOF2_TXD), \ |
| 2099 | GPIO_FN(LCD2D14), |
| 2100 | GPIO_FN(VIO_D5), \ |
| 2101 | GPIO_FN(MSIOF2_TSCK), \ |
| 2102 | GPIO_FN(LCD2D15), |
| 2103 | GPIO_FN(VIO_D6), \ |
| 2104 | GPIO_FN(PORT136_KEYOUT8), \ |
| 2105 | GPIO_FN(LCD2D16), |
| 2106 | GPIO_FN(VIO_D7), \ |
| 2107 | GPIO_FN(PORT137_KEYOUT9), \ |
| 2108 | GPIO_FN(LCD2D17), |
| 2109 | GPIO_FN(VIO_D8), \ |
| 2110 | GPIO_FN(PORT138_KEYOUT8), \ |
| 2111 | GPIO_FN(VIO2_D0), \ |
| 2112 | GPIO_FN(LCD2D6), |
| 2113 | GPIO_FN(VIO_D9), \ |
| 2114 | GPIO_FN(PORT139_KEYOUT9), \ |
| 2115 | GPIO_FN(VIO2_D1), \ |
| 2116 | GPIO_FN(LCD2D7), |
| 2117 | GPIO_FN(VIO_D10), \ |
| 2118 | GPIO_FN(TPU0TO2), \ |
| 2119 | GPIO_FN(VIO2_D2), \ |
| 2120 | GPIO_FN(LCD2D8), |
| 2121 | GPIO_FN(VIO_D11), \ |
| 2122 | GPIO_FN(TPU0TO3), \ |
| 2123 | GPIO_FN(VIO2_D3), \ |
| 2124 | GPIO_FN(LCD2D9), |
| 2125 | GPIO_FN(VIO_D12), \ |
| 2126 | GPIO_FN(PORT142_KEYOUT10), \ |
| 2127 | GPIO_FN(VIO2_D4), \ |
| 2128 | GPIO_FN(LCD2D2), |
| 2129 | GPIO_FN(VIO_D13), \ |
| 2130 | GPIO_FN(PORT143_KEYOUT11), \ |
| 2131 | GPIO_FN(PORT143_KEYOUT6), \ |
| 2132 | GPIO_FN(VIO2_D5), \ |
| 2133 | GPIO_FN(LCD2D3), |
| 2134 | GPIO_FN(VIO_D14), \ |
| 2135 | GPIO_FN(PORT144_KEYOUT7), \ |
| 2136 | GPIO_FN(VIO2_D6), \ |
| 2137 | GPIO_FN(LCD2D4), |
| 2138 | GPIO_FN(VIO_D15), \ |
| 2139 | GPIO_FN(TPU1TO3), \ |
| 2140 | GPIO_FN(PORT145_LCD2DISP), \ |
| 2141 | GPIO_FN(PORT145_LCD2RS), \ |
| 2142 | GPIO_FN(VIO2_D7), \ |
| 2143 | GPIO_FN(LCD2D5), |
| 2144 | GPIO_FN(VIO_CLK), \ |
| 2145 | GPIO_FN(LCD2DCK), \ |
| 2146 | GPIO_FN(PORT146_LCD2WR_), \ |
| 2147 | GPIO_FN(VIO2_CLK), \ |
| 2148 | GPIO_FN(LCD2D18), |
| 2149 | GPIO_FN(VIO_FIELD), \ |
| 2150 | GPIO_FN(LCD2RD_), \ |
| 2151 | GPIO_FN(VIO2_FIELD), \ |
| 2152 | GPIO_FN(LCD2D19), |
| 2153 | GPIO_FN(VIO_CKO), |
| 2154 | GPIO_FN(A27), \ |
| 2155 | GPIO_FN(PORT149_RDWR), \ |
| 2156 | GPIO_FN(MFG0_IN1), \ |
| 2157 | GPIO_FN(PORT149_KEYOUT9), |
| 2158 | GPIO_FN(MFG0_IN2), |
| 2159 | GPIO_FN(TS_SPSYNC3), \ |
| 2160 | GPIO_FN(MSIOF2_RSCK), |
| 2161 | GPIO_FN(TS_SDAT3), \ |
| 2162 | GPIO_FN(MSIOF2_RSYNC), |
| 2163 | GPIO_FN(TPU1TO2), \ |
| 2164 | GPIO_FN(TS_SDEN3), \ |
| 2165 | GPIO_FN(PORT153_MSIOF2_SS1), |
| 2166 | GPIO_FN(SCIFA2_TXD1), \ |
| 2167 | GPIO_FN(MSIOF2_MCK0), |
| 2168 | GPIO_FN(SCIFA2_RXD1), \ |
| 2169 | GPIO_FN(MSIOF2_MCK1), |
| 2170 | GPIO_FN(SCIFA2_RTS1_), \ |
| 2171 | GPIO_FN(PORT156_MSIOF2_SS2), |
| 2172 | GPIO_FN(SCIFA2_CTS1_), \ |
| 2173 | GPIO_FN(PORT157_MSIOF2_RXD), |
| 2174 | GPIO_FN(DINT_), \ |
| 2175 | GPIO_FN(SCIFA2_SCK1), \ |
| 2176 | GPIO_FN(TS_SCK3), |
| 2177 | GPIO_FN(PORT159_SCIFB_SCK), \ |
| 2178 | GPIO_FN(PORT159_SCIFA5_SCK), \ |
| 2179 | GPIO_FN(NMI), |
| 2180 | GPIO_FN(PORT160_SCIFB_TXD), \ |
| 2181 | GPIO_FN(PORT160_SCIFA5_TXD), |
| 2182 | GPIO_FN(PORT161_SCIFB_CTS_), \ |
| 2183 | GPIO_FN(PORT161_SCIFA5_CTS_), |
| 2184 | GPIO_FN(PORT162_SCIFB_RXD), \ |
| 2185 | GPIO_FN(PORT162_SCIFA5_RXD), |
| 2186 | GPIO_FN(PORT163_SCIFB_RTS_), \ |
| 2187 | GPIO_FN(PORT163_SCIFA5_RTS_), \ |
| 2188 | GPIO_FN(TPU3TO0), |
| 2189 | GPIO_FN(LCDD0), |
| 2190 | GPIO_FN(LCDD1), \ |
| 2191 | GPIO_FN(PORT193_SCIFA5_CTS_), \ |
| 2192 | GPIO_FN(BBIF2_TSYNC1), |
| 2193 | GPIO_FN(LCDD2), \ |
| 2194 | GPIO_FN(PORT194_SCIFA5_RTS_), \ |
| 2195 | GPIO_FN(BBIF2_TSCK1), |
| 2196 | GPIO_FN(LCDD3), \ |
| 2197 | GPIO_FN(PORT195_SCIFA5_RXD), \ |
| 2198 | GPIO_FN(BBIF2_TXD1), |
| 2199 | GPIO_FN(LCDD4), \ |
| 2200 | GPIO_FN(PORT196_SCIFA5_TXD), |
| 2201 | GPIO_FN(LCDD5), \ |
| 2202 | GPIO_FN(PORT197_SCIFA5_SCK), \ |
| 2203 | GPIO_FN(MFG2_OUT2), \ |
| 2204 | GPIO_FN(TPU2TO1), |
| 2205 | GPIO_FN(LCDD6), |
| 2206 | GPIO_FN(LCDD7), \ |
| 2207 | GPIO_FN(TPU4TO1), \ |
| 2208 | GPIO_FN(MFG4_OUT2), |
| 2209 | GPIO_FN(LCDD8), \ |
| 2210 | GPIO_FN(D16), |
| 2211 | GPIO_FN(LCDD9), \ |
| 2212 | GPIO_FN(D17), |
| 2213 | GPIO_FN(LCDD10), \ |
| 2214 | GPIO_FN(D18), |
| 2215 | GPIO_FN(LCDD11), \ |
| 2216 | GPIO_FN(D19), |
| 2217 | GPIO_FN(LCDD12), \ |
| 2218 | GPIO_FN(D20), |
| 2219 | GPIO_FN(LCDD13), \ |
| 2220 | GPIO_FN(D21), |
| 2221 | GPIO_FN(LCDD14), \ |
| 2222 | GPIO_FN(D22), |
| 2223 | GPIO_FN(LCDD15), \ |
| 2224 | GPIO_FN(PORT207_MSIOF0L_SS1), \ |
| 2225 | GPIO_FN(D23), |
| 2226 | GPIO_FN(LCDD16), \ |
| 2227 | GPIO_FN(PORT208_MSIOF0L_SS2), \ |
| 2228 | GPIO_FN(D24), |
| 2229 | GPIO_FN(LCDD17), \ |
| 2230 | GPIO_FN(D25), |
| 2231 | GPIO_FN(LCDD18), \ |
| 2232 | GPIO_FN(DREQ2), \ |
| 2233 | GPIO_FN(PORT210_MSIOF0L_SS1), \ |
| 2234 | GPIO_FN(D26), |
| 2235 | GPIO_FN(LCDD19), \ |
| 2236 | GPIO_FN(PORT211_MSIOF0L_SS2), \ |
| 2237 | GPIO_FN(D27), |
| 2238 | GPIO_FN(LCDD20), \ |
| 2239 | GPIO_FN(TS_SPSYNC1), \ |
| 2240 | GPIO_FN(MSIOF0L_MCK0), \ |
| 2241 | GPIO_FN(D28), |
| 2242 | GPIO_FN(LCDD21), \ |
| 2243 | GPIO_FN(TS_SDAT1), \ |
| 2244 | GPIO_FN(MSIOF0L_MCK1), \ |
| 2245 | GPIO_FN(D29), |
| 2246 | GPIO_FN(LCDD22), \ |
| 2247 | GPIO_FN(TS_SDEN1), \ |
| 2248 | GPIO_FN(MSIOF0L_RSCK), \ |
| 2249 | GPIO_FN(D30), |
| 2250 | GPIO_FN(LCDD23), \ |
| 2251 | GPIO_FN(TS_SCK1), \ |
| 2252 | GPIO_FN(MSIOF0L_RSYNC), \ |
| 2253 | GPIO_FN(D31), |
| 2254 | GPIO_FN(LCDDCK), \ |
| 2255 | GPIO_FN(LCDWR_), |
| 2256 | GPIO_FN(LCDRD_), \ |
| 2257 | GPIO_FN(DACK2), \ |
| 2258 | GPIO_FN(PORT217_LCD2RS), \ |
| 2259 | GPIO_FN(MSIOF0L_TSYNC), \ |
| 2260 | GPIO_FN(VIO2_FIELD3), \ |
| 2261 | GPIO_FN(PORT217_LCD2DISP), |
| 2262 | GPIO_FN(LCDHSYN), \ |
| 2263 | GPIO_FN(LCDCS_), \ |
| 2264 | GPIO_FN(LCDCS2_), \ |
| 2265 | GPIO_FN(DACK3), \ |
| 2266 | GPIO_FN(PORT218_VIO_CKOR), |
| 2267 | GPIO_FN(LCDDISP), \ |
| 2268 | GPIO_FN(LCDRS), \ |
| 2269 | GPIO_FN(PORT219_LCD2WR_), \ |
| 2270 | GPIO_FN(DREQ3), \ |
| 2271 | GPIO_FN(MSIOF0L_TSCK), \ |
| 2272 | GPIO_FN(VIO2_CLK3), \ |
| 2273 | GPIO_FN(LCD2DCK_2), |
| 2274 | GPIO_FN(LCDVSYN), \ |
| 2275 | GPIO_FN(LCDVSYN2), |
| 2276 | GPIO_FN(LCDLCLK), \ |
| 2277 | GPIO_FN(DREQ1), \ |
| 2278 | GPIO_FN(PORT221_LCD2CS_), \ |
| 2279 | GPIO_FN(PWEN), \ |
| 2280 | GPIO_FN(MSIOF0L_RXD), \ |
| 2281 | GPIO_FN(VIO2_HD3), \ |
| 2282 | GPIO_FN(PORT221_LCD2HSYN), |
| 2283 | GPIO_FN(LCDDON), \ |
| 2284 | GPIO_FN(LCDDON2), \ |
| 2285 | GPIO_FN(DACK1), \ |
| 2286 | GPIO_FN(OVCN), \ |
| 2287 | GPIO_FN(MSIOF0L_TXD), \ |
| 2288 | GPIO_FN(VIO2_VD3), \ |
| 2289 | GPIO_FN(PORT222_LCD2VSYN), |
| 2290 | |
| 2291 | GPIO_FN(SCIFA1_TXD), \ |
| 2292 | GPIO_FN(OVCN2), |
| 2293 | GPIO_FN(EXTLP), \ |
| 2294 | GPIO_FN(SCIFA1_SCK), \ |
| 2295 | GPIO_FN(PORT226_VIO_CKO2), |
| 2296 | GPIO_FN(SCIFA1_RTS_), \ |
| 2297 | GPIO_FN(IDIN), |
| 2298 | GPIO_FN(SCIFA1_RXD), |
| 2299 | GPIO_FN(SCIFA1_CTS_), \ |
| 2300 | GPIO_FN(MFG1_IN1), |
| 2301 | GPIO_FN(MSIOF1_TXD), \ |
| 2302 | GPIO_FN(SCIFA2_TXD2), |
| 2303 | GPIO_FN(MSIOF1_TSYNC), \ |
| 2304 | GPIO_FN(SCIFA2_CTS2_), |
| 2305 | GPIO_FN(MSIOF1_TSCK), \ |
| 2306 | GPIO_FN(SCIFA2_SCK2), |
| 2307 | GPIO_FN(MSIOF1_RXD), \ |
| 2308 | GPIO_FN(SCIFA2_RXD2), |
| 2309 | GPIO_FN(MSIOF1_RSCK), \ |
| 2310 | GPIO_FN(SCIFA2_RTS2_), \ |
| 2311 | GPIO_FN(VIO2_CLK2), \ |
| 2312 | GPIO_FN(LCD2D20), |
| 2313 | GPIO_FN(MSIOF1_RSYNC), \ |
| 2314 | GPIO_FN(MFG1_IN2), \ |
| 2315 | GPIO_FN(VIO2_VD2), \ |
| 2316 | GPIO_FN(LCD2D21), |
| 2317 | GPIO_FN(MSIOF1_MCK0), \ |
| 2318 | GPIO_FN(PORT236_I2C_SDA2), |
| 2319 | GPIO_FN(MSIOF1_MCK1), \ |
| 2320 | GPIO_FN(PORT237_I2C_SCL2), |
| 2321 | GPIO_FN(MSIOF1_SS1), \ |
| 2322 | GPIO_FN(VIO2_FIELD2), \ |
| 2323 | GPIO_FN(LCD2D22), |
| 2324 | GPIO_FN(MSIOF1_SS2), \ |
| 2325 | GPIO_FN(VIO2_HD2), \ |
| 2326 | GPIO_FN(LCD2D23), |
| 2327 | GPIO_FN(SCIFA6_TXD), |
| 2328 | GPIO_FN(PORT241_IRDA_OUT), \ |
| 2329 | GPIO_FN(PORT241_IROUT), \ |
| 2330 | GPIO_FN(MFG4_OUT1), \ |
| 2331 | GPIO_FN(TPU4TO0), |
| 2332 | GPIO_FN(PORT242_IRDA_IN), \ |
| 2333 | GPIO_FN(MFG4_IN2), |
| 2334 | GPIO_FN(PORT243_IRDA_FIRSEL), \ |
| 2335 | GPIO_FN(PORT243_VIO_CKO2), |
| 2336 | GPIO_FN(PORT244_SCIFA5_CTS_), \ |
| 2337 | GPIO_FN(MFG2_IN1), \ |
| 2338 | GPIO_FN(PORT244_SCIFB_CTS_), \ |
| 2339 | GPIO_FN(MSIOF2R_RXD), |
| 2340 | GPIO_FN(PORT245_SCIFA5_RTS_), \ |
| 2341 | GPIO_FN(MFG2_IN2), \ |
| 2342 | GPIO_FN(PORT245_SCIFB_RTS_), \ |
| 2343 | GPIO_FN(MSIOF2R_TXD), |
| 2344 | GPIO_FN(PORT246_SCIFA5_RXD), \ |
| 2345 | GPIO_FN(MFG1_OUT1), \ |
| 2346 | GPIO_FN(PORT246_SCIFB_RXD), \ |
| 2347 | GPIO_FN(TPU1TO0), |
| 2348 | GPIO_FN(PORT247_SCIFA5_TXD), \ |
| 2349 | GPIO_FN(MFG3_OUT2), \ |
| 2350 | GPIO_FN(PORT247_SCIFB_TXD), \ |
| 2351 | GPIO_FN(TPU3TO1), |
| 2352 | GPIO_FN(PORT248_SCIFA5_SCK), \ |
| 2353 | GPIO_FN(MFG2_OUT1), \ |
| 2354 | GPIO_FN(PORT248_SCIFB_SCK), \ |
| 2355 | GPIO_FN(TPU2TO0), \ |
| 2356 | GPIO_FN(PORT248_I2C_SCL3), \ |
| 2357 | GPIO_FN(MSIOF2R_TSCK), |
| 2358 | GPIO_FN(PORT249_IROUT), \ |
| 2359 | GPIO_FN(MFG4_IN1), \ |
| 2360 | GPIO_FN(PORT249_I2C_SDA3), \ |
| 2361 | GPIO_FN(MSIOF2R_TSYNC), |
| 2362 | GPIO_FN(SDHICLK0), |
| 2363 | GPIO_FN(SDHICD0), |
| 2364 | GPIO_FN(SDHID0_0), |
| 2365 | GPIO_FN(SDHID0_1), |
| 2366 | GPIO_FN(SDHID0_2), |
| 2367 | GPIO_FN(SDHID0_3), |
| 2368 | GPIO_FN(SDHICMD0), |
| 2369 | GPIO_FN(SDHIWP0), |
| 2370 | GPIO_FN(SDHICLK1), |
| 2371 | GPIO_FN(SDHID1_0), \ |
| 2372 | GPIO_FN(TS_SPSYNC2), |
| 2373 | GPIO_FN(SDHID1_1), \ |
| 2374 | GPIO_FN(TS_SDAT2), |
| 2375 | GPIO_FN(SDHID1_2), \ |
| 2376 | GPIO_FN(TS_SDEN2), |
| 2377 | GPIO_FN(SDHID1_3), \ |
| 2378 | GPIO_FN(TS_SCK2), |
| 2379 | GPIO_FN(SDHICMD1), |
| 2380 | GPIO_FN(SDHICLK2), |
| 2381 | GPIO_FN(SDHID2_0), \ |
| 2382 | GPIO_FN(TS_SPSYNC4), |
| 2383 | GPIO_FN(SDHID2_1), \ |
| 2384 | GPIO_FN(TS_SDAT4), |
| 2385 | GPIO_FN(SDHID2_2), \ |
| 2386 | GPIO_FN(TS_SDEN4), |
| 2387 | GPIO_FN(SDHID2_3), \ |
| 2388 | GPIO_FN(TS_SCK4), |
| 2389 | GPIO_FN(SDHICMD2), |
| 2390 | GPIO_FN(MMCCLK0), |
| 2391 | GPIO_FN(MMCD0_0), |
| 2392 | GPIO_FN(MMCD0_1), |
| 2393 | GPIO_FN(MMCD0_2), |
| 2394 | GPIO_FN(MMCD0_3), |
| 2395 | GPIO_FN(MMCD0_4), \ |
| 2396 | GPIO_FN(TS_SPSYNC5), |
| 2397 | GPIO_FN(MMCD0_5), \ |
| 2398 | GPIO_FN(TS_SDAT5), |
| 2399 | GPIO_FN(MMCD0_6), \ |
| 2400 | GPIO_FN(TS_SDEN5), |
| 2401 | GPIO_FN(MMCD0_7), \ |
| 2402 | GPIO_FN(TS_SCK5), |
| 2403 | GPIO_FN(MMCCMD0), |
| 2404 | GPIO_FN(RESETOUTS_), \ |
| 2405 | GPIO_FN(EXTAL2OUT), |
| 2406 | GPIO_FN(MCP_WAIT__MCP_FRB), |
| 2407 | GPIO_FN(MCP_CKO), \ |
| 2408 | GPIO_FN(MMCCLK1), |
| 2409 | GPIO_FN(MCP_D15_MCP_NAF15), |
| 2410 | GPIO_FN(MCP_D14_MCP_NAF14), |
| 2411 | GPIO_FN(MCP_D13_MCP_NAF13), |
| 2412 | GPIO_FN(MCP_D12_MCP_NAF12), |
| 2413 | GPIO_FN(MCP_D11_MCP_NAF11), |
| 2414 | GPIO_FN(MCP_D10_MCP_NAF10), |
| 2415 | GPIO_FN(MCP_D9_MCP_NAF9), |
| 2416 | GPIO_FN(MCP_D8_MCP_NAF8), \ |
| 2417 | GPIO_FN(MMCCMD1), |
| 2418 | GPIO_FN(MCP_D7_MCP_NAF7), \ |
| 2419 | GPIO_FN(MMCD1_7), |
| 2420 | |
| 2421 | GPIO_FN(MCP_D6_MCP_NAF6), \ |
| 2422 | GPIO_FN(MMCD1_6), |
| 2423 | GPIO_FN(MCP_D5_MCP_NAF5), \ |
| 2424 | GPIO_FN(MMCD1_5), |
| 2425 | GPIO_FN(MCP_D4_MCP_NAF4), \ |
| 2426 | GPIO_FN(MMCD1_4), |
| 2427 | GPIO_FN(MCP_D3_MCP_NAF3), \ |
| 2428 | GPIO_FN(MMCD1_3), |
| 2429 | GPIO_FN(MCP_D2_MCP_NAF2), \ |
| 2430 | GPIO_FN(MMCD1_2), |
| 2431 | GPIO_FN(MCP_D1_MCP_NAF1), \ |
| 2432 | GPIO_FN(MMCD1_1), |
| 2433 | GPIO_FN(MCP_D0_MCP_NAF0), \ |
| 2434 | GPIO_FN(MMCD1_0), |
| 2435 | GPIO_FN(MCP_NBRSTOUT_), |
| 2436 | GPIO_FN(MCP_WE0__MCP_FWE), \ |
| 2437 | GPIO_FN(MCP_RDWR_MCP_FWE), |
| 2438 | |
| 2439 | /* MSEL2 special cases */ |
| 2440 | GPIO_FN(TSIF2_TS_XX1), |
| 2441 | GPIO_FN(TSIF2_TS_XX2), |
| 2442 | GPIO_FN(TSIF2_TS_XX3), |
| 2443 | GPIO_FN(TSIF2_TS_XX4), |
| 2444 | GPIO_FN(TSIF2_TS_XX5), |
| 2445 | GPIO_FN(TSIF1_TS_XX1), |
| 2446 | GPIO_FN(TSIF1_TS_XX2), |
| 2447 | GPIO_FN(TSIF1_TS_XX3), |
| 2448 | GPIO_FN(TSIF1_TS_XX4), |
| 2449 | GPIO_FN(TSIF1_TS_XX5), |
| 2450 | GPIO_FN(TSIF0_TS_XX1), |
| 2451 | GPIO_FN(TSIF0_TS_XX2), |
| 2452 | GPIO_FN(TSIF0_TS_XX3), |
| 2453 | GPIO_FN(TSIF0_TS_XX4), |
| 2454 | GPIO_FN(TSIF0_TS_XX5), |
| 2455 | GPIO_FN(MST1_TS_XX1), |
| 2456 | GPIO_FN(MST1_TS_XX2), |
| 2457 | GPIO_FN(MST1_TS_XX3), |
| 2458 | GPIO_FN(MST1_TS_XX4), |
| 2459 | GPIO_FN(MST1_TS_XX5), |
| 2460 | GPIO_FN(MST0_TS_XX1), |
| 2461 | GPIO_FN(MST0_TS_XX2), |
| 2462 | GPIO_FN(MST0_TS_XX3), |
| 2463 | GPIO_FN(MST0_TS_XX4), |
| 2464 | GPIO_FN(MST0_TS_XX5), |
| 2465 | |
| 2466 | /* MSEL3 special cases */ |
| 2467 | GPIO_FN(SDHI0_VCCQ_MC0_ON), |
| 2468 | GPIO_FN(SDHI0_VCCQ_MC0_OFF), |
| 2469 | GPIO_FN(DEBUG_MON_VIO), |
| 2470 | GPIO_FN(DEBUG_MON_LCDD), |
| 2471 | GPIO_FN(LCDC_LCDC0), |
| 2472 | GPIO_FN(LCDC_LCDC1), |
| 2473 | |
| 2474 | /* MSEL4 special cases */ |
| 2475 | GPIO_FN(IRQ9_MEM_INT), |
| 2476 | GPIO_FN(IRQ9_MCP_INT), |
| 2477 | GPIO_FN(A11), |
| 2478 | GPIO_FN(KEYOUT8), |
| 2479 | GPIO_FN(TPU4TO3), |
| 2480 | GPIO_FN(RESETA_N_PU_ON), |
| 2481 | GPIO_FN(RESETA_N_PU_OFF), |
| 2482 | GPIO_FN(EDBGREQ_PD), |
| 2483 | GPIO_FN(EDBGREQ_PU), |
| 2484 | |
| 2485 | /* Functions with pull-ups */ |
| 2486 | GPIO_FN(KEYIN0_PU), |
| 2487 | GPIO_FN(KEYIN1_PU), |
| 2488 | GPIO_FN(KEYIN2_PU), |
| 2489 | GPIO_FN(KEYIN3_PU), |
| 2490 | GPIO_FN(KEYIN4_PU), |
| 2491 | GPIO_FN(KEYIN5_PU), |
| 2492 | GPIO_FN(KEYIN6_PU), |
| 2493 | GPIO_FN(KEYIN7_PU), |
| 2494 | GPIO_FN(SDHICD0_PU), |
| 2495 | GPIO_FN(SDHID0_0_PU), |
| 2496 | GPIO_FN(SDHID0_1_PU), |
| 2497 | GPIO_FN(SDHID0_2_PU), |
| 2498 | GPIO_FN(SDHID0_3_PU), |
| 2499 | GPIO_FN(SDHICMD0_PU), |
| 2500 | GPIO_FN(SDHIWP0_PU), |
| 2501 | GPIO_FN(SDHID1_0_PU), |
| 2502 | GPIO_FN(SDHID1_1_PU), |
| 2503 | GPIO_FN(SDHID1_2_PU), |
| 2504 | GPIO_FN(SDHID1_3_PU), |
| 2505 | GPIO_FN(SDHICMD1_PU), |
| 2506 | GPIO_FN(SDHID2_0_PU), |
| 2507 | GPIO_FN(SDHID2_1_PU), |
| 2508 | GPIO_FN(SDHID2_2_PU), |
| 2509 | GPIO_FN(SDHID2_3_PU), |
| 2510 | GPIO_FN(SDHICMD2_PU), |
| 2511 | GPIO_FN(MMCCMD0_PU), |
| 2512 | GPIO_FN(MMCCMD1_PU), |
| 2513 | GPIO_FN(MMCD0_0_PU), |
| 2514 | GPIO_FN(MMCD0_1_PU), |
| 2515 | GPIO_FN(MMCD0_2_PU), |
| 2516 | GPIO_FN(MMCD0_3_PU), |
| 2517 | GPIO_FN(MMCD0_4_PU), |
| 2518 | GPIO_FN(MMCD0_5_PU), |
| 2519 | GPIO_FN(MMCD0_6_PU), |
| 2520 | GPIO_FN(MMCD0_7_PU), |
| 2521 | GPIO_FN(FSIACK_PU), |
| 2522 | GPIO_FN(FSIAILR_PU), |
| 2523 | GPIO_FN(FSIAIBT_PU), |
| 2524 | GPIO_FN(FSIAISLD_PU), |
| 2525 | }; |
| 2526 | |
Laurent Pinchart | cd3c1be | 2013-02-16 18:47:05 +0100 | [diff] [blame] | 2527 | static const struct pinmux_cfg_reg pinmux_config_regs[] = { |
Laurent Pinchart | 5d5166d | 2012-12-15 23:51:24 +0100 | [diff] [blame] | 2528 | PORTCR(0, 0xe6050000), /* PORT0CR */ |
| 2529 | PORTCR(1, 0xe6050001), /* PORT1CR */ |
| 2530 | PORTCR(2, 0xe6050002), /* PORT2CR */ |
| 2531 | PORTCR(3, 0xe6050003), /* PORT3CR */ |
| 2532 | PORTCR(4, 0xe6050004), /* PORT4CR */ |
| 2533 | PORTCR(5, 0xe6050005), /* PORT5CR */ |
| 2534 | PORTCR(6, 0xe6050006), /* PORT6CR */ |
| 2535 | PORTCR(7, 0xe6050007), /* PORT7CR */ |
| 2536 | PORTCR(8, 0xe6050008), /* PORT8CR */ |
| 2537 | PORTCR(9, 0xe6050009), /* PORT9CR */ |
| 2538 | |
| 2539 | PORTCR(10, 0xe605000a), /* PORT10CR */ |
| 2540 | PORTCR(11, 0xe605000b), /* PORT11CR */ |
| 2541 | PORTCR(12, 0xe605000c), /* PORT12CR */ |
| 2542 | PORTCR(13, 0xe605000d), /* PORT13CR */ |
| 2543 | PORTCR(14, 0xe605000e), /* PORT14CR */ |
| 2544 | PORTCR(15, 0xe605000f), /* PORT15CR */ |
| 2545 | PORTCR(16, 0xe6050010), /* PORT16CR */ |
| 2546 | PORTCR(17, 0xe6050011), /* PORT17CR */ |
| 2547 | PORTCR(18, 0xe6050012), /* PORT18CR */ |
| 2548 | PORTCR(19, 0xe6050013), /* PORT19CR */ |
| 2549 | |
| 2550 | PORTCR(20, 0xe6050014), /* PORT20CR */ |
| 2551 | PORTCR(21, 0xe6050015), /* PORT21CR */ |
| 2552 | PORTCR(22, 0xe6050016), /* PORT22CR */ |
| 2553 | PORTCR(23, 0xe6050017), /* PORT23CR */ |
| 2554 | PORTCR(24, 0xe6050018), /* PORT24CR */ |
| 2555 | PORTCR(25, 0xe6050019), /* PORT25CR */ |
| 2556 | PORTCR(26, 0xe605001a), /* PORT26CR */ |
| 2557 | PORTCR(27, 0xe605001b), /* PORT27CR */ |
| 2558 | PORTCR(28, 0xe605001c), /* PORT28CR */ |
| 2559 | PORTCR(29, 0xe605001d), /* PORT29CR */ |
| 2560 | |
| 2561 | PORTCR(30, 0xe605001e), /* PORT30CR */ |
| 2562 | PORTCR(31, 0xe605001f), /* PORT31CR */ |
| 2563 | PORTCR(32, 0xe6051020), /* PORT32CR */ |
| 2564 | PORTCR(33, 0xe6051021), /* PORT33CR */ |
| 2565 | PORTCR(34, 0xe6051022), /* PORT34CR */ |
| 2566 | PORTCR(35, 0xe6051023), /* PORT35CR */ |
| 2567 | PORTCR(36, 0xe6051024), /* PORT36CR */ |
| 2568 | PORTCR(37, 0xe6051025), /* PORT37CR */ |
| 2569 | PORTCR(38, 0xe6051026), /* PORT38CR */ |
| 2570 | PORTCR(39, 0xe6051027), /* PORT39CR */ |
| 2571 | |
| 2572 | PORTCR(40, 0xe6051028), /* PORT40CR */ |
| 2573 | PORTCR(41, 0xe6051029), /* PORT41CR */ |
| 2574 | PORTCR(42, 0xe605102a), /* PORT42CR */ |
| 2575 | PORTCR(43, 0xe605102b), /* PORT43CR */ |
| 2576 | PORTCR(44, 0xe605102c), /* PORT44CR */ |
| 2577 | PORTCR(45, 0xe605102d), /* PORT45CR */ |
| 2578 | PORTCR(46, 0xe605102e), /* PORT46CR */ |
| 2579 | PORTCR(47, 0xe605102f), /* PORT47CR */ |
| 2580 | PORTCR(48, 0xe6051030), /* PORT48CR */ |
| 2581 | PORTCR(49, 0xe6051031), /* PORT49CR */ |
| 2582 | |
| 2583 | PORTCR(50, 0xe6051032), /* PORT50CR */ |
| 2584 | PORTCR(51, 0xe6051033), /* PORT51CR */ |
| 2585 | PORTCR(52, 0xe6051034), /* PORT52CR */ |
| 2586 | PORTCR(53, 0xe6051035), /* PORT53CR */ |
| 2587 | PORTCR(54, 0xe6051036), /* PORT54CR */ |
| 2588 | PORTCR(55, 0xe6051037), /* PORT55CR */ |
| 2589 | PORTCR(56, 0xe6051038), /* PORT56CR */ |
| 2590 | PORTCR(57, 0xe6051039), /* PORT57CR */ |
| 2591 | PORTCR(58, 0xe605103a), /* PORT58CR */ |
| 2592 | PORTCR(59, 0xe605103b), /* PORT59CR */ |
| 2593 | |
| 2594 | PORTCR(60, 0xe605103c), /* PORT60CR */ |
| 2595 | PORTCR(61, 0xe605103d), /* PORT61CR */ |
| 2596 | PORTCR(62, 0xe605103e), /* PORT62CR */ |
| 2597 | PORTCR(63, 0xe605103f), /* PORT63CR */ |
| 2598 | PORTCR(64, 0xe6051040), /* PORT64CR */ |
| 2599 | PORTCR(65, 0xe6051041), /* PORT65CR */ |
| 2600 | PORTCR(66, 0xe6051042), /* PORT66CR */ |
| 2601 | PORTCR(67, 0xe6051043), /* PORT67CR */ |
| 2602 | PORTCR(68, 0xe6051044), /* PORT68CR */ |
| 2603 | PORTCR(69, 0xe6051045), /* PORT69CR */ |
| 2604 | |
| 2605 | PORTCR(70, 0xe6051046), /* PORT70CR */ |
| 2606 | PORTCR(71, 0xe6051047), /* PORT71CR */ |
| 2607 | PORTCR(72, 0xe6051048), /* PORT72CR */ |
| 2608 | PORTCR(73, 0xe6051049), /* PORT73CR */ |
| 2609 | PORTCR(74, 0xe605104a), /* PORT74CR */ |
| 2610 | PORTCR(75, 0xe605104b), /* PORT75CR */ |
| 2611 | PORTCR(76, 0xe605104c), /* PORT76CR */ |
| 2612 | PORTCR(77, 0xe605104d), /* PORT77CR */ |
| 2613 | PORTCR(78, 0xe605104e), /* PORT78CR */ |
| 2614 | PORTCR(79, 0xe605104f), /* PORT79CR */ |
| 2615 | |
| 2616 | PORTCR(80, 0xe6051050), /* PORT80CR */ |
| 2617 | PORTCR(81, 0xe6051051), /* PORT81CR */ |
| 2618 | PORTCR(82, 0xe6051052), /* PORT82CR */ |
| 2619 | PORTCR(83, 0xe6051053), /* PORT83CR */ |
| 2620 | PORTCR(84, 0xe6051054), /* PORT84CR */ |
| 2621 | PORTCR(85, 0xe6051055), /* PORT85CR */ |
| 2622 | PORTCR(86, 0xe6051056), /* PORT86CR */ |
| 2623 | PORTCR(87, 0xe6051057), /* PORT87CR */ |
| 2624 | PORTCR(88, 0xe6051058), /* PORT88CR */ |
| 2625 | PORTCR(89, 0xe6051059), /* PORT89CR */ |
| 2626 | |
| 2627 | PORTCR(90, 0xe605105a), /* PORT90CR */ |
| 2628 | PORTCR(91, 0xe605105b), /* PORT91CR */ |
| 2629 | PORTCR(92, 0xe605105c), /* PORT92CR */ |
| 2630 | PORTCR(93, 0xe605105d), /* PORT93CR */ |
| 2631 | PORTCR(94, 0xe605105e), /* PORT94CR */ |
| 2632 | PORTCR(95, 0xe605105f), /* PORT95CR */ |
| 2633 | PORTCR(96, 0xe6052060), /* PORT96CR */ |
| 2634 | PORTCR(97, 0xe6052061), /* PORT97CR */ |
| 2635 | PORTCR(98, 0xe6052062), /* PORT98CR */ |
| 2636 | PORTCR(99, 0xe6052063), /* PORT99CR */ |
| 2637 | |
| 2638 | PORTCR(100, 0xe6052064), /* PORT100CR */ |
| 2639 | PORTCR(101, 0xe6052065), /* PORT101CR */ |
| 2640 | PORTCR(102, 0xe6052066), /* PORT102CR */ |
| 2641 | PORTCR(103, 0xe6052067), /* PORT103CR */ |
| 2642 | PORTCR(104, 0xe6052068), /* PORT104CR */ |
| 2643 | PORTCR(105, 0xe6052069), /* PORT105CR */ |
| 2644 | PORTCR(106, 0xe605206a), /* PORT106CR */ |
| 2645 | PORTCR(107, 0xe605206b), /* PORT107CR */ |
| 2646 | PORTCR(108, 0xe605206c), /* PORT108CR */ |
| 2647 | PORTCR(109, 0xe605206d), /* PORT109CR */ |
| 2648 | |
| 2649 | PORTCR(110, 0xe605206e), /* PORT110CR */ |
| 2650 | PORTCR(111, 0xe605206f), /* PORT111CR */ |
| 2651 | PORTCR(112, 0xe6052070), /* PORT112CR */ |
| 2652 | PORTCR(113, 0xe6052071), /* PORT113CR */ |
| 2653 | PORTCR(114, 0xe6052072), /* PORT114CR */ |
| 2654 | PORTCR(115, 0xe6052073), /* PORT115CR */ |
| 2655 | PORTCR(116, 0xe6052074), /* PORT116CR */ |
| 2656 | PORTCR(117, 0xe6052075), /* PORT117CR */ |
| 2657 | PORTCR(118, 0xe6052076), /* PORT118CR */ |
| 2658 | |
| 2659 | PORTCR(128, 0xe6052080), /* PORT128CR */ |
| 2660 | PORTCR(129, 0xe6052081), /* PORT129CR */ |
| 2661 | |
| 2662 | PORTCR(130, 0xe6052082), /* PORT130CR */ |
| 2663 | PORTCR(131, 0xe6052083), /* PORT131CR */ |
| 2664 | PORTCR(132, 0xe6052084), /* PORT132CR */ |
| 2665 | PORTCR(133, 0xe6052085), /* PORT133CR */ |
| 2666 | PORTCR(134, 0xe6052086), /* PORT134CR */ |
| 2667 | PORTCR(135, 0xe6052087), /* PORT135CR */ |
| 2668 | PORTCR(136, 0xe6052088), /* PORT136CR */ |
| 2669 | PORTCR(137, 0xe6052089), /* PORT137CR */ |
| 2670 | PORTCR(138, 0xe605208a), /* PORT138CR */ |
| 2671 | PORTCR(139, 0xe605208b), /* PORT139CR */ |
| 2672 | |
| 2673 | PORTCR(140, 0xe605208c), /* PORT140CR */ |
| 2674 | PORTCR(141, 0xe605208d), /* PORT141CR */ |
| 2675 | PORTCR(142, 0xe605208e), /* PORT142CR */ |
| 2676 | PORTCR(143, 0xe605208f), /* PORT143CR */ |
| 2677 | PORTCR(144, 0xe6052090), /* PORT144CR */ |
| 2678 | PORTCR(145, 0xe6052091), /* PORT145CR */ |
| 2679 | PORTCR(146, 0xe6052092), /* PORT146CR */ |
| 2680 | PORTCR(147, 0xe6052093), /* PORT147CR */ |
| 2681 | PORTCR(148, 0xe6052094), /* PORT148CR */ |
| 2682 | PORTCR(149, 0xe6052095), /* PORT149CR */ |
| 2683 | |
| 2684 | PORTCR(150, 0xe6052096), /* PORT150CR */ |
| 2685 | PORTCR(151, 0xe6052097), /* PORT151CR */ |
| 2686 | PORTCR(152, 0xe6052098), /* PORT152CR */ |
| 2687 | PORTCR(153, 0xe6052099), /* PORT153CR */ |
| 2688 | PORTCR(154, 0xe605209a), /* PORT154CR */ |
| 2689 | PORTCR(155, 0xe605209b), /* PORT155CR */ |
| 2690 | PORTCR(156, 0xe605209c), /* PORT156CR */ |
| 2691 | PORTCR(157, 0xe605209d), /* PORT157CR */ |
| 2692 | PORTCR(158, 0xe605209e), /* PORT158CR */ |
| 2693 | PORTCR(159, 0xe605209f), /* PORT159CR */ |
| 2694 | |
| 2695 | PORTCR(160, 0xe60520a0), /* PORT160CR */ |
| 2696 | PORTCR(161, 0xe60520a1), /* PORT161CR */ |
| 2697 | PORTCR(162, 0xe60520a2), /* PORT162CR */ |
| 2698 | PORTCR(163, 0xe60520a3), /* PORT163CR */ |
| 2699 | PORTCR(164, 0xe60520a4), /* PORT164CR */ |
| 2700 | |
| 2701 | PORTCR(192, 0xe60520c0), /* PORT192CR */ |
| 2702 | PORTCR(193, 0xe60520c1), /* PORT193CR */ |
| 2703 | PORTCR(194, 0xe60520c2), /* PORT194CR */ |
| 2704 | PORTCR(195, 0xe60520c3), /* PORT195CR */ |
| 2705 | PORTCR(196, 0xe60520c4), /* PORT196CR */ |
| 2706 | PORTCR(197, 0xe60520c5), /* PORT197CR */ |
| 2707 | PORTCR(198, 0xe60520c6), /* PORT198CR */ |
| 2708 | PORTCR(199, 0xe60520c7), /* PORT199CR */ |
| 2709 | |
| 2710 | PORTCR(200, 0xe60520c8), /* PORT200CR */ |
| 2711 | PORTCR(201, 0xe60520c9), /* PORT201CR */ |
| 2712 | PORTCR(202, 0xe60520ca), /* PORT202CR */ |
| 2713 | PORTCR(203, 0xe60520cb), /* PORT203CR */ |
| 2714 | PORTCR(204, 0xe60520cc), /* PORT204CR */ |
| 2715 | PORTCR(205, 0xe60520cd), /* PORT205CR */ |
| 2716 | PORTCR(206, 0xe60520ce), /* PORT206CR */ |
| 2717 | PORTCR(207, 0xe60520cf), /* PORT207CR */ |
| 2718 | PORTCR(208, 0xe60520d0), /* PORT208CR */ |
| 2719 | PORTCR(209, 0xe60520d1), /* PORT209CR */ |
| 2720 | |
| 2721 | PORTCR(210, 0xe60520d2), /* PORT210CR */ |
| 2722 | PORTCR(211, 0xe60520d3), /* PORT211CR */ |
| 2723 | PORTCR(212, 0xe60520d4), /* PORT212CR */ |
| 2724 | PORTCR(213, 0xe60520d5), /* PORT213CR */ |
| 2725 | PORTCR(214, 0xe60520d6), /* PORT214CR */ |
| 2726 | PORTCR(215, 0xe60520d7), /* PORT215CR */ |
| 2727 | PORTCR(216, 0xe60520d8), /* PORT216CR */ |
| 2728 | PORTCR(217, 0xe60520d9), /* PORT217CR */ |
| 2729 | PORTCR(218, 0xe60520da), /* PORT218CR */ |
| 2730 | PORTCR(219, 0xe60520db), /* PORT219CR */ |
| 2731 | |
| 2732 | PORTCR(220, 0xe60520dc), /* PORT220CR */ |
| 2733 | PORTCR(221, 0xe60520dd), /* PORT221CR */ |
| 2734 | PORTCR(222, 0xe60520de), /* PORT222CR */ |
| 2735 | PORTCR(223, 0xe60520df), /* PORT223CR */ |
| 2736 | PORTCR(224, 0xe60530e0), /* PORT224CR */ |
| 2737 | PORTCR(225, 0xe60530e1), /* PORT225CR */ |
| 2738 | PORTCR(226, 0xe60530e2), /* PORT226CR */ |
| 2739 | PORTCR(227, 0xe60530e3), /* PORT227CR */ |
| 2740 | PORTCR(228, 0xe60530e4), /* PORT228CR */ |
| 2741 | PORTCR(229, 0xe60530e5), /* PORT229CR */ |
| 2742 | |
| 2743 | PORTCR(230, 0xe60530e6), /* PORT230CR */ |
| 2744 | PORTCR(231, 0xe60530e7), /* PORT231CR */ |
| 2745 | PORTCR(232, 0xe60530e8), /* PORT232CR */ |
| 2746 | PORTCR(233, 0xe60530e9), /* PORT233CR */ |
| 2747 | PORTCR(234, 0xe60530ea), /* PORT234CR */ |
| 2748 | PORTCR(235, 0xe60530eb), /* PORT235CR */ |
| 2749 | PORTCR(236, 0xe60530ec), /* PORT236CR */ |
| 2750 | PORTCR(237, 0xe60530ed), /* PORT237CR */ |
| 2751 | PORTCR(238, 0xe60530ee), /* PORT238CR */ |
| 2752 | PORTCR(239, 0xe60530ef), /* PORT239CR */ |
| 2753 | |
| 2754 | PORTCR(240, 0xe60530f0), /* PORT240CR */ |
| 2755 | PORTCR(241, 0xe60530f1), /* PORT241CR */ |
| 2756 | PORTCR(242, 0xe60530f2), /* PORT242CR */ |
| 2757 | PORTCR(243, 0xe60530f3), /* PORT243CR */ |
| 2758 | PORTCR(244, 0xe60530f4), /* PORT244CR */ |
| 2759 | PORTCR(245, 0xe60530f5), /* PORT245CR */ |
| 2760 | PORTCR(246, 0xe60530f6), /* PORT246CR */ |
| 2761 | PORTCR(247, 0xe60530f7), /* PORT247CR */ |
| 2762 | PORTCR(248, 0xe60530f8), /* PORT248CR */ |
| 2763 | PORTCR(249, 0xe60530f9), /* PORT249CR */ |
| 2764 | |
| 2765 | PORTCR(250, 0xe60530fa), /* PORT250CR */ |
| 2766 | PORTCR(251, 0xe60530fb), /* PORT251CR */ |
| 2767 | PORTCR(252, 0xe60530fc), /* PORT252CR */ |
| 2768 | PORTCR(253, 0xe60530fd), /* PORT253CR */ |
| 2769 | PORTCR(254, 0xe60530fe), /* PORT254CR */ |
| 2770 | PORTCR(255, 0xe60530ff), /* PORT255CR */ |
| 2771 | PORTCR(256, 0xe6053100), /* PORT256CR */ |
| 2772 | PORTCR(257, 0xe6053101), /* PORT257CR */ |
| 2773 | PORTCR(258, 0xe6053102), /* PORT258CR */ |
| 2774 | PORTCR(259, 0xe6053103), /* PORT259CR */ |
| 2775 | |
| 2776 | PORTCR(260, 0xe6053104), /* PORT260CR */ |
| 2777 | PORTCR(261, 0xe6053105), /* PORT261CR */ |
| 2778 | PORTCR(262, 0xe6053106), /* PORT262CR */ |
| 2779 | PORTCR(263, 0xe6053107), /* PORT263CR */ |
| 2780 | PORTCR(264, 0xe6053108), /* PORT264CR */ |
| 2781 | PORTCR(265, 0xe6053109), /* PORT265CR */ |
| 2782 | PORTCR(266, 0xe605310a), /* PORT266CR */ |
| 2783 | PORTCR(267, 0xe605310b), /* PORT267CR */ |
| 2784 | PORTCR(268, 0xe605310c), /* PORT268CR */ |
| 2785 | PORTCR(269, 0xe605310d), /* PORT269CR */ |
| 2786 | |
| 2787 | PORTCR(270, 0xe605310e), /* PORT270CR */ |
| 2788 | PORTCR(271, 0xe605310f), /* PORT271CR */ |
| 2789 | PORTCR(272, 0xe6053110), /* PORT272CR */ |
| 2790 | PORTCR(273, 0xe6053111), /* PORT273CR */ |
| 2791 | PORTCR(274, 0xe6053112), /* PORT274CR */ |
| 2792 | PORTCR(275, 0xe6053113), /* PORT275CR */ |
| 2793 | PORTCR(276, 0xe6053114), /* PORT276CR */ |
| 2794 | PORTCR(277, 0xe6053115), /* PORT277CR */ |
| 2795 | PORTCR(278, 0xe6053116), /* PORT278CR */ |
| 2796 | PORTCR(279, 0xe6053117), /* PORT279CR */ |
| 2797 | |
| 2798 | PORTCR(280, 0xe6053118), /* PORT280CR */ |
| 2799 | PORTCR(281, 0xe6053119), /* PORT281CR */ |
| 2800 | PORTCR(282, 0xe605311a), /* PORT282CR */ |
| 2801 | |
| 2802 | PORTCR(288, 0xe6052120), /* PORT288CR */ |
| 2803 | PORTCR(289, 0xe6052121), /* PORT289CR */ |
| 2804 | |
| 2805 | PORTCR(290, 0xe6052122), /* PORT290CR */ |
| 2806 | PORTCR(291, 0xe6052123), /* PORT291CR */ |
| 2807 | PORTCR(292, 0xe6052124), /* PORT292CR */ |
| 2808 | PORTCR(293, 0xe6052125), /* PORT293CR */ |
| 2809 | PORTCR(294, 0xe6052126), /* PORT294CR */ |
| 2810 | PORTCR(295, 0xe6052127), /* PORT295CR */ |
| 2811 | PORTCR(296, 0xe6052128), /* PORT296CR */ |
| 2812 | PORTCR(297, 0xe6052129), /* PORT297CR */ |
| 2813 | PORTCR(298, 0xe605212a), /* PORT298CR */ |
| 2814 | PORTCR(299, 0xe605212b), /* PORT299CR */ |
| 2815 | |
| 2816 | PORTCR(300, 0xe605212c), /* PORT300CR */ |
| 2817 | PORTCR(301, 0xe605212d), /* PORT301CR */ |
| 2818 | PORTCR(302, 0xe605212e), /* PORT302CR */ |
| 2819 | PORTCR(303, 0xe605212f), /* PORT303CR */ |
| 2820 | PORTCR(304, 0xe6052130), /* PORT304CR */ |
| 2821 | PORTCR(305, 0xe6052131), /* PORT305CR */ |
| 2822 | PORTCR(306, 0xe6052132), /* PORT306CR */ |
| 2823 | PORTCR(307, 0xe6052133), /* PORT307CR */ |
| 2824 | PORTCR(308, 0xe6052134), /* PORT308CR */ |
| 2825 | PORTCR(309, 0xe6052135), /* PORT309CR */ |
| 2826 | |
| 2827 | { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) { |
| 2828 | 0, 0, |
| 2829 | 0, 0, |
| 2830 | 0, 0, |
| 2831 | 0, 0, |
| 2832 | 0, 0, |
| 2833 | 0, 0, |
| 2834 | 0, 0, |
| 2835 | 0, 0, |
| 2836 | 0, 0, |
| 2837 | 0, 0, |
| 2838 | 0, 0, |
| 2839 | 0, 0, |
| 2840 | MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1, |
| 2841 | MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1, |
| 2842 | MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1, |
| 2843 | MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1, |
| 2844 | 0, 0, |
| 2845 | MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1, |
| 2846 | MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1, |
| 2847 | MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1, |
| 2848 | MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1, |
| 2849 | MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1, |
| 2850 | MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1, |
| 2851 | MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1, |
| 2852 | MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1, |
| 2853 | MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1, |
| 2854 | MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1, |
| 2855 | MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1, |
| 2856 | MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1, |
| 2857 | MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1, |
| 2858 | MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1, |
| 2859 | MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1, |
| 2860 | } |
| 2861 | }, |
| 2862 | { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) { |
| 2863 | 0, 0, |
| 2864 | 0, 0, |
| 2865 | 0, 0, |
| 2866 | MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1, |
| 2867 | 0, 0, |
| 2868 | 0, 0, |
| 2869 | 0, 0, |
| 2870 | 0, 0, |
| 2871 | 0, 0, |
| 2872 | 0, 0, |
| 2873 | 0, 0, |
| 2874 | 0, 0, |
| 2875 | 0, 0, |
| 2876 | 0, 0, |
| 2877 | 0, 0, |
| 2878 | 0, 0, |
| 2879 | MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1, |
| 2880 | 0, 0, |
| 2881 | 0, 0, |
| 2882 | 0, 0, |
| 2883 | MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1, |
| 2884 | 0, 0, |
| 2885 | MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1, |
| 2886 | 0, 0, |
| 2887 | 0, 0, |
| 2888 | MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1, |
| 2889 | 0, 0, |
| 2890 | 0, 0, |
| 2891 | 0, 0, |
| 2892 | MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1, |
| 2893 | 0, 0, |
| 2894 | 0, 0, |
| 2895 | } |
| 2896 | }, |
| 2897 | { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) { |
| 2898 | 0, 0, |
| 2899 | 0, 0, |
| 2900 | MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1, |
| 2901 | 0, 0, |
| 2902 | MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1, |
| 2903 | MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1, |
| 2904 | 0, 0, |
| 2905 | 0, 0, |
| 2906 | 0, 0, |
| 2907 | MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1, |
| 2908 | MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1, |
| 2909 | MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1, |
| 2910 | MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1, |
| 2911 | 0, 0, |
| 2912 | 0, 0, |
| 2913 | 0, 0, |
| 2914 | MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1, |
| 2915 | 0, 0, |
| 2916 | MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1, |
| 2917 | MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1, |
| 2918 | MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1, |
| 2919 | MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1, |
| 2920 | MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1, |
| 2921 | MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1, |
| 2922 | MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1, |
| 2923 | 0, 0, |
| 2924 | 0, 0, |
| 2925 | MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1, |
| 2926 | 0, 0, |
| 2927 | 0, 0, |
| 2928 | MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1, |
| 2929 | 0, 0, |
| 2930 | } |
| 2931 | }, |
| 2932 | { }, |
| 2933 | }; |
| 2934 | |
Laurent Pinchart | cd3c1be | 2013-02-16 18:47:05 +0100 | [diff] [blame] | 2935 | static const struct pinmux_data_reg pinmux_data_regs[] = { |
Laurent Pinchart | 5d5166d | 2012-12-15 23:51:24 +0100 | [diff] [blame] | 2936 | { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) { |
| 2937 | PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, |
| 2938 | PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, |
| 2939 | PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, |
| 2940 | PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA, |
| 2941 | PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA, |
| 2942 | PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, |
| 2943 | PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, |
| 2944 | PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA } |
| 2945 | }, |
| 2946 | { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) { |
| 2947 | PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA, |
| 2948 | PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA, |
| 2949 | PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA, |
| 2950 | PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA, |
| 2951 | PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA, |
| 2952 | PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA, |
| 2953 | PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, |
| 2954 | PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA } |
| 2955 | }, |
| 2956 | { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) { |
| 2957 | PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, |
| 2958 | PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, |
| 2959 | PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA, |
| 2960 | PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA, |
| 2961 | PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA, |
| 2962 | PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, |
| 2963 | PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, |
| 2964 | PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA } |
| 2965 | }, |
| 2966 | { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) { |
| 2967 | 0, 0, 0, 0, |
| 2968 | 0, 0, 0, 0, |
| 2969 | 0, PORT118_DATA, PORT117_DATA, PORT116_DATA, |
| 2970 | PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA, |
| 2971 | PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA, |
| 2972 | PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, |
| 2973 | PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, |
| 2974 | PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA } |
| 2975 | }, |
| 2976 | { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) { |
| 2977 | PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA, |
| 2978 | PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA, |
| 2979 | PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA, |
| 2980 | PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA, |
| 2981 | PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA, |
| 2982 | PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA, |
| 2983 | PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA, |
| 2984 | PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA } |
| 2985 | }, |
| 2986 | { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) { |
| 2987 | 0, 0, 0, 0, |
| 2988 | 0, 0, 0, 0, |
| 2989 | 0, 0, 0, 0, |
| 2990 | 0, 0, 0, 0, |
| 2991 | 0, 0, 0, 0, |
| 2992 | 0, 0, 0, 0, |
| 2993 | 0, 0, 0, PORT164_DATA, |
| 2994 | PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA } |
| 2995 | }, |
| 2996 | { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) { |
| 2997 | PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA, |
| 2998 | PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA, |
| 2999 | PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA, |
| 3000 | PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA, |
| 3001 | PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA, |
| 3002 | PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA, |
| 3003 | PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA, |
| 3004 | PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA } |
| 3005 | }, |
| 3006 | { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) { |
| 3007 | PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA, |
| 3008 | PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA, |
| 3009 | PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA, |
| 3010 | PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA, |
| 3011 | PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA, |
| 3012 | PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA, |
| 3013 | PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA, |
| 3014 | PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA } |
| 3015 | }, |
| 3016 | { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) { |
| 3017 | 0, 0, 0, 0, |
| 3018 | 0, PORT282_DATA, PORT281_DATA, PORT280_DATA, |
| 3019 | PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA, |
| 3020 | PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA, |
| 3021 | PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA, |
| 3022 | PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA, |
| 3023 | PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA, |
| 3024 | PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA } |
| 3025 | }, |
| 3026 | { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) { |
| 3027 | 0, 0, 0, 0, |
| 3028 | 0, 0, 0, 0, |
| 3029 | 0, 0, PORT309_DATA, PORT308_DATA, |
| 3030 | PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA, |
| 3031 | PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA, |
| 3032 | PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA, |
| 3033 | PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA, |
| 3034 | PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA } |
| 3035 | }, |
| 3036 | { }, |
| 3037 | }; |
| 3038 | |
| 3039 | /* IRQ pins through INTCS with IRQ0->15 from 0x200 and IRQ16-31 from 0x3200 */ |
| 3040 | #define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5)) |
| 3041 | #define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5)) |
| 3042 | |
Laurent Pinchart | cd3c1be | 2013-02-16 18:47:05 +0100 | [diff] [blame] | 3043 | static const struct pinmux_irq pinmux_irqs[] = { |
Guennadi Liakhovetski | b58e5fa | 2013-02-12 16:50:02 +0100 | [diff] [blame] | 3044 | PINMUX_IRQ(EXT_IRQ16H(19), 9), |
| 3045 | PINMUX_IRQ(EXT_IRQ16L(1), 10), |
| 3046 | PINMUX_IRQ(EXT_IRQ16L(0), 11), |
| 3047 | PINMUX_IRQ(EXT_IRQ16H(18), 13), |
| 3048 | PINMUX_IRQ(EXT_IRQ16H(20), 14), |
| 3049 | PINMUX_IRQ(EXT_IRQ16H(21), 15), |
| 3050 | PINMUX_IRQ(EXT_IRQ16H(31), 26), |
| 3051 | PINMUX_IRQ(EXT_IRQ16H(30), 27), |
| 3052 | PINMUX_IRQ(EXT_IRQ16H(29), 28), |
| 3053 | PINMUX_IRQ(EXT_IRQ16H(22), 40), |
| 3054 | PINMUX_IRQ(EXT_IRQ16H(23), 53), |
| 3055 | PINMUX_IRQ(EXT_IRQ16L(10), 54), |
| 3056 | PINMUX_IRQ(EXT_IRQ16L(9), 56), |
| 3057 | PINMUX_IRQ(EXT_IRQ16H(26), 115), |
| 3058 | PINMUX_IRQ(EXT_IRQ16H(27), 116), |
| 3059 | PINMUX_IRQ(EXT_IRQ16H(28), 117), |
| 3060 | PINMUX_IRQ(EXT_IRQ16H(24), 118), |
| 3061 | PINMUX_IRQ(EXT_IRQ16L(6), 147), |
| 3062 | PINMUX_IRQ(EXT_IRQ16L(2), 149), |
| 3063 | PINMUX_IRQ(EXT_IRQ16L(7), 150), |
| 3064 | PINMUX_IRQ(EXT_IRQ16L(12), 156), |
| 3065 | PINMUX_IRQ(EXT_IRQ16L(4), 159), |
| 3066 | PINMUX_IRQ(EXT_IRQ16H(25), 164), |
| 3067 | PINMUX_IRQ(EXT_IRQ16L(8), 223), |
| 3068 | PINMUX_IRQ(EXT_IRQ16L(3), 224), |
| 3069 | PINMUX_IRQ(EXT_IRQ16L(5), 227), |
| 3070 | PINMUX_IRQ(EXT_IRQ16H(17), 234), |
| 3071 | PINMUX_IRQ(EXT_IRQ16L(11), 238), |
| 3072 | PINMUX_IRQ(EXT_IRQ16L(13), 239), |
| 3073 | PINMUX_IRQ(EXT_IRQ16H(16), 249), |
| 3074 | PINMUX_IRQ(EXT_IRQ16L(14), 251), |
| 3075 | PINMUX_IRQ(EXT_IRQ16L(9), 308), |
Laurent Pinchart | 5d5166d | 2012-12-15 23:51:24 +0100 | [diff] [blame] | 3076 | }; |
| 3077 | |
Laurent Pinchart | b823899 | 2013-03-13 01:31:23 +0100 | [diff] [blame^] | 3078 | #define PORTnCR_PULMD_OFF (0 << 6) |
| 3079 | #define PORTnCR_PULMD_DOWN (2 << 6) |
| 3080 | #define PORTnCR_PULMD_UP (3 << 6) |
| 3081 | #define PORTnCR_PULMD_MASK (3 << 6) |
| 3082 | |
| 3083 | static const unsigned int sh73a0_portcr_offsets[] = { |
| 3084 | 0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000, |
| 3085 | 0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000, |
| 3086 | }; |
| 3087 | |
| 3088 | static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) |
| 3089 | { |
| 3090 | void __iomem *addr = pfc->window->virt |
| 3091 | + sh73a0_portcr_offsets[pin >> 5] + pin; |
| 3092 | u32 value = ioread8(addr) & PORTnCR_PULMD_MASK; |
| 3093 | |
| 3094 | switch (value) { |
| 3095 | case PORTnCR_PULMD_UP: |
| 3096 | return PIN_CONFIG_BIAS_PULL_UP; |
| 3097 | case PORTnCR_PULMD_DOWN: |
| 3098 | return PIN_CONFIG_BIAS_PULL_DOWN; |
| 3099 | case PORTnCR_PULMD_OFF: |
| 3100 | default: |
| 3101 | return PIN_CONFIG_BIAS_DISABLE; |
| 3102 | } |
| 3103 | } |
| 3104 | |
| 3105 | static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, |
| 3106 | unsigned int bias) |
| 3107 | { |
| 3108 | void __iomem *addr = pfc->window->virt |
| 3109 | + sh73a0_portcr_offsets[pin >> 5] + pin; |
| 3110 | u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK; |
| 3111 | |
| 3112 | switch (bias) { |
| 3113 | case PIN_CONFIG_BIAS_PULL_UP: |
| 3114 | value |= PORTnCR_PULMD_UP; |
| 3115 | break; |
| 3116 | case PIN_CONFIG_BIAS_PULL_DOWN: |
| 3117 | value |= PORTnCR_PULMD_DOWN; |
| 3118 | break; |
| 3119 | } |
| 3120 | |
| 3121 | iowrite8(value, addr); |
| 3122 | } |
| 3123 | |
| 3124 | static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = { |
| 3125 | .get_bias = sh73a0_pinmux_get_bias, |
| 3126 | .set_bias = sh73a0_pinmux_set_bias, |
| 3127 | }; |
| 3128 | |
Laurent Pinchart | cd3c1be | 2013-02-16 18:47:05 +0100 | [diff] [blame] | 3129 | const struct sh_pfc_soc_info sh73a0_pinmux_info = { |
Laurent Pinchart | 5d5166d | 2012-12-15 23:51:24 +0100 | [diff] [blame] | 3130 | .name = "sh73a0_pfc", |
Laurent Pinchart | b823899 | 2013-03-13 01:31:23 +0100 | [diff] [blame^] | 3131 | .ops = &sh73a0_pinmux_ops, |
| 3132 | |
Laurent Pinchart | 5d5166d | 2012-12-15 23:51:24 +0100 | [diff] [blame] | 3133 | .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, |
| 3134 | .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, |
| 3135 | .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, |
| 3136 | .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, |
Laurent Pinchart | 5d5166d | 2012-12-15 23:51:24 +0100 | [diff] [blame] | 3137 | .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, |
| 3138 | |
Laurent Pinchart | a373ed0 | 2012-11-29 13:24:07 +0100 | [diff] [blame] | 3139 | .pins = pinmux_pins, |
| 3140 | .nr_pins = ARRAY_SIZE(pinmux_pins), |
Guennadi Liakhovetski | b58e5fa | 2013-02-12 16:50:02 +0100 | [diff] [blame] | 3141 | .ranges = pinmux_ranges, |
| 3142 | .nr_ranges = ARRAY_SIZE(pinmux_ranges), |
Laurent Pinchart | a373ed0 | 2012-11-29 13:24:07 +0100 | [diff] [blame] | 3143 | .func_gpios = pinmux_func_gpios, |
| 3144 | .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), |
Laurent Pinchart | d7a7ca5 | 2012-11-28 17:51:00 +0100 | [diff] [blame] | 3145 | |
Laurent Pinchart | 5d5166d | 2012-12-15 23:51:24 +0100 | [diff] [blame] | 3146 | .cfg_regs = pinmux_config_regs, |
| 3147 | .data_regs = pinmux_data_regs, |
| 3148 | |
| 3149 | .gpio_data = pinmux_data, |
| 3150 | .gpio_data_size = ARRAY_SIZE(pinmux_data), |
| 3151 | |
| 3152 | .gpio_irq = pinmux_irqs, |
| 3153 | .gpio_irq_size = ARRAY_SIZE(pinmux_irqs), |
| 3154 | }; |