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Waiman Longa33fda32015-04-24 14:56:30 -04001/*
2 * Queued spinlock
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.
15 *
16 * Authors: Waiman Long <waiman.long@hp.com>
17 */
18#ifndef __ASM_GENERIC_QSPINLOCK_TYPES_H
19#define __ASM_GENERIC_QSPINLOCK_TYPES_H
20
21/*
22 * Including atomic.h with PARAVIRT on will cause compilation errors because
23 * of recursive header file incluson via paravirt_types.h. So don't include
24 * it if PARAVIRT is on.
25 */
26#ifndef CONFIG_PARAVIRT
27#include <linux/types.h>
28#include <linux/atomic.h>
29#endif
30
31typedef struct qspinlock {
32 atomic_t val;
33} arch_spinlock_t;
34
35/*
Dan Streetmanb82e5302016-02-19 13:49:27 -050036 * Initializier
37 */
38#define __ARCH_SPIN_LOCK_UNLOCKED { ATOMIC_INIT(0) }
39
40/*
Waiman Longa33fda32015-04-24 14:56:30 -040041 * Bitfields in the atomic value:
42 *
Peter Zijlstra (Intel)69f9cae2015-04-24 14:56:34 -040043 * When NR_CPUS < 16K
44 * 0- 7: locked byte
45 * 8: pending
46 * 9-15: not used
47 * 16-17: tail index
48 * 18-31: tail cpu (+1)
49 *
50 * When NR_CPUS >= 16K
Waiman Longa33fda32015-04-24 14:56:30 -040051 * 0- 7: locked byte
Peter Zijlstra (Intel)c1fb1592015-04-24 14:56:32 -040052 * 8: pending
53 * 9-10: tail index
54 * 11-31: tail cpu (+1)
Waiman Longa33fda32015-04-24 14:56:30 -040055 */
56#define _Q_SET_MASK(type) (((1U << _Q_ ## type ## _BITS) - 1)\
57 << _Q_ ## type ## _OFFSET)
58#define _Q_LOCKED_OFFSET 0
59#define _Q_LOCKED_BITS 8
60#define _Q_LOCKED_MASK _Q_SET_MASK(LOCKED)
61
Peter Zijlstra (Intel)c1fb1592015-04-24 14:56:32 -040062#define _Q_PENDING_OFFSET (_Q_LOCKED_OFFSET + _Q_LOCKED_BITS)
Peter Zijlstra (Intel)69f9cae2015-04-24 14:56:34 -040063#if CONFIG_NR_CPUS < (1U << 14)
64#define _Q_PENDING_BITS 8
65#else
Peter Zijlstra (Intel)c1fb1592015-04-24 14:56:32 -040066#define _Q_PENDING_BITS 1
Peter Zijlstra (Intel)69f9cae2015-04-24 14:56:34 -040067#endif
Peter Zijlstra (Intel)c1fb1592015-04-24 14:56:32 -040068#define _Q_PENDING_MASK _Q_SET_MASK(PENDING)
69
70#define _Q_TAIL_IDX_OFFSET (_Q_PENDING_OFFSET + _Q_PENDING_BITS)
Waiman Longa33fda32015-04-24 14:56:30 -040071#define _Q_TAIL_IDX_BITS 2
72#define _Q_TAIL_IDX_MASK _Q_SET_MASK(TAIL_IDX)
73
74#define _Q_TAIL_CPU_OFFSET (_Q_TAIL_IDX_OFFSET + _Q_TAIL_IDX_BITS)
75#define _Q_TAIL_CPU_BITS (32 - _Q_TAIL_CPU_OFFSET)
76#define _Q_TAIL_CPU_MASK _Q_SET_MASK(TAIL_CPU)
77
Peter Zijlstra (Intel)69f9cae2015-04-24 14:56:34 -040078#define _Q_TAIL_OFFSET _Q_TAIL_IDX_OFFSET
Waiman Long6403bd72015-04-24 14:56:33 -040079#define _Q_TAIL_MASK (_Q_TAIL_IDX_MASK | _Q_TAIL_CPU_MASK)
80
Waiman Longa33fda32015-04-24 14:56:30 -040081#define _Q_LOCKED_VAL (1U << _Q_LOCKED_OFFSET)
Peter Zijlstra (Intel)c1fb1592015-04-24 14:56:32 -040082#define _Q_PENDING_VAL (1U << _Q_PENDING_OFFSET)
Waiman Longa33fda32015-04-24 14:56:30 -040083
84#endif /* __ASM_GENERIC_QSPINLOCK_TYPES_H */