John Crispin | 87316f6 | 2016-02-19 08:17:18 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016 John Crispin <blogic@openwrt.org> |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #include <dt-bindings/pinctrl/mt65xx.h> |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/of.h> |
| 17 | #include <linux/of_device.h> |
| 18 | #include <linux/platform_device.h> |
| 19 | #include <linux/pinctrl/pinctrl.h> |
| 20 | #include <linux/regmap.h> |
| 21 | |
| 22 | #include "pinctrl-mtk-common.h" |
| 23 | #include "pinctrl-mtk-mt7623.h" |
| 24 | |
| 25 | static const struct mtk_drv_group_desc mt7623_drv_grp[] = { |
| 26 | /* 0E4E8SR 4/8/12/16 */ |
| 27 | MTK_DRV_GRP(4, 16, 1, 2, 4), |
| 28 | /* 0E2E4SR 2/4/6/8 */ |
| 29 | MTK_DRV_GRP(2, 8, 1, 2, 2), |
| 30 | /* E8E4E2 2/4/6/8/10/12/14/16 */ |
| 31 | MTK_DRV_GRP(2, 16, 0, 2, 2) |
| 32 | }; |
| 33 | |
| 34 | #define DRV_SEL0 0xf50 |
| 35 | #define DRV_SEL1 0xf60 |
| 36 | #define DRV_SEL2 0xf70 |
| 37 | #define DRV_SEL3 0xf80 |
| 38 | #define DRV_SEL4 0xf90 |
| 39 | #define DRV_SEL5 0xfa0 |
| 40 | #define DRV_SEL6 0xfb0 |
| 41 | #define DRV_SEL7 0xfe0 |
| 42 | #define DRV_SEL8 0xfd0 |
| 43 | #define DRV_SEL9 0xff0 |
| 44 | #define DRV_SEL10 0xf00 |
| 45 | |
| 46 | #define MSDC0_CTRL0 0xcc0 |
| 47 | #define MSDC0_CTRL1 0xcd0 |
| 48 | #define MSDC0_CTRL2 0xce0 |
| 49 | #define MSDC0_CTRL3 0xcf0 |
| 50 | #define MSDC0_CTRL4 0xd00 |
| 51 | #define MSDC0_CTRL5 0xd10 |
| 52 | #define MSDC0_CTRL6 0xd20 |
| 53 | #define MSDC1_CTRL0 0xd30 |
| 54 | #define MSDC1_CTRL1 0xd40 |
| 55 | #define MSDC1_CTRL2 0xd50 |
| 56 | #define MSDC1_CTRL3 0xd60 |
| 57 | #define MSDC1_CTRL4 0xd70 |
| 58 | #define MSDC1_CTRL5 0xd80 |
| 59 | #define MSDC1_CTRL6 0xd90 |
| 60 | |
| 61 | #define IES_EN0 0xb20 |
| 62 | #define IES_EN1 0xb30 |
| 63 | #define IES_EN2 0xb40 |
| 64 | |
| 65 | #define SMT_EN0 0xb50 |
| 66 | #define SMT_EN1 0xb60 |
| 67 | #define SMT_EN2 0xb70 |
| 68 | |
| 69 | static const struct mtk_pin_drv_grp mt7623_pin_drv[] = { |
| 70 | MTK_PIN_DRV_GRP(0, DRV_SEL0, 0, 1), |
| 71 | MTK_PIN_DRV_GRP(1, DRV_SEL0, 0, 1), |
| 72 | MTK_PIN_DRV_GRP(2, DRV_SEL0, 0, 1), |
| 73 | MTK_PIN_DRV_GRP(3, DRV_SEL0, 0, 1), |
| 74 | MTK_PIN_DRV_GRP(4, DRV_SEL0, 0, 1), |
| 75 | MTK_PIN_DRV_GRP(5, DRV_SEL0, 0, 1), |
| 76 | MTK_PIN_DRV_GRP(6, DRV_SEL0, 0, 1), |
| 77 | MTK_PIN_DRV_GRP(7, DRV_SEL0, 4, 1), |
| 78 | MTK_PIN_DRV_GRP(8, DRV_SEL0, 4, 1), |
| 79 | MTK_PIN_DRV_GRP(9, DRV_SEL0, 4, 1), |
| 80 | MTK_PIN_DRV_GRP(10, DRV_SEL0, 8, 1), |
| 81 | MTK_PIN_DRV_GRP(11, DRV_SEL0, 8, 1), |
| 82 | MTK_PIN_DRV_GRP(12, DRV_SEL0, 8, 1), |
| 83 | MTK_PIN_DRV_GRP(13, DRV_SEL0, 8, 1), |
| 84 | MTK_PIN_DRV_GRP(14, DRV_SEL0, 12, 0), |
| 85 | MTK_PIN_DRV_GRP(15, DRV_SEL0, 12, 0), |
| 86 | MTK_PIN_DRV_GRP(18, DRV_SEL1, 4, 0), |
| 87 | MTK_PIN_DRV_GRP(19, DRV_SEL1, 4, 0), |
| 88 | MTK_PIN_DRV_GRP(20, DRV_SEL1, 4, 0), |
| 89 | MTK_PIN_DRV_GRP(21, DRV_SEL1, 4, 0), |
| 90 | MTK_PIN_DRV_GRP(22, DRV_SEL1, 8, 0), |
| 91 | MTK_PIN_DRV_GRP(23, DRV_SEL1, 8, 0), |
| 92 | MTK_PIN_DRV_GRP(24, DRV_SEL1, 8, 0), |
| 93 | MTK_PIN_DRV_GRP(25, DRV_SEL1, 8, 0), |
| 94 | MTK_PIN_DRV_GRP(26, DRV_SEL1, 8, 0), |
| 95 | MTK_PIN_DRV_GRP(27, DRV_SEL1, 12, 0), |
| 96 | MTK_PIN_DRV_GRP(28, DRV_SEL1, 12, 0), |
| 97 | MTK_PIN_DRV_GRP(29, DRV_SEL1, 12, 0), |
| 98 | MTK_PIN_DRV_GRP(33, DRV_SEL2, 0, 0), |
| 99 | MTK_PIN_DRV_GRP(34, DRV_SEL2, 0, 0), |
| 100 | MTK_PIN_DRV_GRP(35, DRV_SEL2, 0, 0), |
| 101 | MTK_PIN_DRV_GRP(36, DRV_SEL2, 0, 0), |
| 102 | MTK_PIN_DRV_GRP(37, DRV_SEL2, 0, 0), |
| 103 | MTK_PIN_DRV_GRP(39, DRV_SEL2, 8, 1), |
| 104 | MTK_PIN_DRV_GRP(40, DRV_SEL2, 8, 1), |
| 105 | MTK_PIN_DRV_GRP(41, DRV_SEL2, 8, 1), |
| 106 | MTK_PIN_DRV_GRP(42, DRV_SEL2, 8, 1), |
| 107 | MTK_PIN_DRV_GRP(43, DRV_SEL2, 12, 0), |
| 108 | MTK_PIN_DRV_GRP(44, DRV_SEL2, 12, 0), |
| 109 | MTK_PIN_DRV_GRP(45, DRV_SEL2, 12, 0), |
| 110 | MTK_PIN_DRV_GRP(47, DRV_SEL3, 0, 0), |
| 111 | MTK_PIN_DRV_GRP(48, DRV_SEL3, 0, 0), |
| 112 | MTK_PIN_DRV_GRP(49, DRV_SEL3, 4, 0), |
| 113 | MTK_PIN_DRV_GRP(53, DRV_SEL3, 12, 0), |
| 114 | MTK_PIN_DRV_GRP(54, DRV_SEL3, 12, 0), |
| 115 | MTK_PIN_DRV_GRP(55, DRV_SEL3, 12, 0), |
| 116 | MTK_PIN_DRV_GRP(56, DRV_SEL3, 12, 0), |
| 117 | MTK_PIN_DRV_GRP(60, DRV_SEL4, 8, 1), |
| 118 | MTK_PIN_DRV_GRP(61, DRV_SEL4, 8, 1), |
| 119 | MTK_PIN_DRV_GRP(62, DRV_SEL4, 8, 1), |
| 120 | MTK_PIN_DRV_GRP(63, DRV_SEL4, 12, 1), |
| 121 | MTK_PIN_DRV_GRP(64, DRV_SEL4, 12, 1), |
| 122 | MTK_PIN_DRV_GRP(65, DRV_SEL4, 12, 1), |
| 123 | MTK_PIN_DRV_GRP(66, DRV_SEL5, 0, 1), |
| 124 | MTK_PIN_DRV_GRP(67, DRV_SEL5, 0, 1), |
| 125 | MTK_PIN_DRV_GRP(68, DRV_SEL5, 0, 1), |
| 126 | MTK_PIN_DRV_GRP(69, DRV_SEL5, 0, 1), |
| 127 | MTK_PIN_DRV_GRP(70, DRV_SEL5, 0, 1), |
| 128 | MTK_PIN_DRV_GRP(71, DRV_SEL5, 0, 1), |
| 129 | MTK_PIN_DRV_GRP(72, DRV_SEL3, 4, 0), |
| 130 | MTK_PIN_DRV_GRP(73, DRV_SEL3, 4, 0), |
| 131 | MTK_PIN_DRV_GRP(74, DRV_SEL3, 4, 0), |
| 132 | MTK_PIN_DRV_GRP(83, DRV_SEL5, 0, 1), |
| 133 | MTK_PIN_DRV_GRP(84, DRV_SEL5, 0, 1), |
| 134 | MTK_PIN_DRV_GRP(105, MSDC1_CTRL1, 0, 1), |
| 135 | MTK_PIN_DRV_GRP(106, MSDC1_CTRL0, 0, 1), |
| 136 | MTK_PIN_DRV_GRP(107, MSDC1_CTRL2, 0, 1), |
| 137 | MTK_PIN_DRV_GRP(108, MSDC1_CTRL2, 0, 1), |
| 138 | MTK_PIN_DRV_GRP(109, MSDC1_CTRL2, 0, 1), |
| 139 | MTK_PIN_DRV_GRP(110, MSDC1_CTRL2, 0, 1), |
| 140 | MTK_PIN_DRV_GRP(111, MSDC0_CTRL2, 0, 1), |
| 141 | MTK_PIN_DRV_GRP(112, MSDC0_CTRL2, 0, 1), |
| 142 | MTK_PIN_DRV_GRP(113, MSDC0_CTRL2, 0, 1), |
| 143 | MTK_PIN_DRV_GRP(114, MSDC0_CTRL2, 0, 1), |
| 144 | MTK_PIN_DRV_GRP(115, MSDC0_CTRL2, 0, 1), |
| 145 | MTK_PIN_DRV_GRP(116, MSDC0_CTRL1, 0, 1), |
| 146 | MTK_PIN_DRV_GRP(117, MSDC0_CTRL0, 0, 1), |
| 147 | MTK_PIN_DRV_GRP(118, MSDC0_CTRL2, 0, 1), |
| 148 | MTK_PIN_DRV_GRP(119, MSDC0_CTRL2, 0, 1), |
| 149 | MTK_PIN_DRV_GRP(120, MSDC0_CTRL2, 0, 1), |
| 150 | MTK_PIN_DRV_GRP(121, MSDC0_CTRL2, 0, 1), |
| 151 | MTK_PIN_DRV_GRP(126, DRV_SEL3, 4, 0), |
| 152 | MTK_PIN_DRV_GRP(199, DRV_SEL0, 4, 1), |
| 153 | MTK_PIN_DRV_GRP(200, DRV_SEL8, 0, 0), |
| 154 | MTK_PIN_DRV_GRP(201, DRV_SEL8, 0, 0), |
| 155 | MTK_PIN_DRV_GRP(203, DRV_SEL8, 4, 0), |
| 156 | MTK_PIN_DRV_GRP(204, DRV_SEL8, 4, 0), |
| 157 | MTK_PIN_DRV_GRP(205, DRV_SEL8, 4, 0), |
| 158 | MTK_PIN_DRV_GRP(206, DRV_SEL8, 4, 0), |
| 159 | MTK_PIN_DRV_GRP(207, DRV_SEL8, 4, 0), |
| 160 | MTK_PIN_DRV_GRP(208, DRV_SEL8, 8, 0), |
| 161 | MTK_PIN_DRV_GRP(209, DRV_SEL8, 8, 0), |
| 162 | MTK_PIN_DRV_GRP(236, DRV_SEL9, 4, 0), |
| 163 | MTK_PIN_DRV_GRP(237, DRV_SEL9, 4, 0), |
| 164 | MTK_PIN_DRV_GRP(238, DRV_SEL9, 4, 0), |
| 165 | MTK_PIN_DRV_GRP(239, DRV_SEL9, 4, 0), |
| 166 | MTK_PIN_DRV_GRP(240, DRV_SEL9, 4, 0), |
| 167 | MTK_PIN_DRV_GRP(241, DRV_SEL9, 4, 0), |
| 168 | MTK_PIN_DRV_GRP(242, DRV_SEL9, 8, 0), |
| 169 | MTK_PIN_DRV_GRP(243, DRV_SEL9, 8, 0), |
| 170 | MTK_PIN_DRV_GRP(257, MSDC0_CTRL2, 0, 1), |
| 171 | MTK_PIN_DRV_GRP(261, MSDC1_CTRL2, 0, 1), |
| 172 | MTK_PIN_DRV_GRP(262, DRV_SEL10, 8, 0), |
| 173 | MTK_PIN_DRV_GRP(263, DRV_SEL10, 8, 0), |
| 174 | MTK_PIN_DRV_GRP(264, DRV_SEL10, 8, 0), |
| 175 | MTK_PIN_DRV_GRP(265, DRV_SEL10, 8, 0), |
| 176 | MTK_PIN_DRV_GRP(266, DRV_SEL10, 8, 0), |
| 177 | MTK_PIN_DRV_GRP(267, DRV_SEL10, 8, 0), |
| 178 | MTK_PIN_DRV_GRP(268, DRV_SEL10, 8, 0), |
| 179 | MTK_PIN_DRV_GRP(269, DRV_SEL10, 8, 0), |
| 180 | MTK_PIN_DRV_GRP(270, DRV_SEL10, 8, 0), |
| 181 | MTK_PIN_DRV_GRP(271, DRV_SEL10, 8, 0), |
| 182 | MTK_PIN_DRV_GRP(272, DRV_SEL10, 8, 0), |
| 183 | MTK_PIN_DRV_GRP(274, DRV_SEL10, 8, 0), |
| 184 | MTK_PIN_DRV_GRP(275, DRV_SEL10, 8, 0), |
| 185 | MTK_PIN_DRV_GRP(276, DRV_SEL10, 8, 0), |
| 186 | MTK_PIN_DRV_GRP(278, DRV_SEL2, 8, 1), |
| 187 | }; |
| 188 | |
| 189 | static const struct mtk_pin_spec_pupd_set_samereg mt7623_spec_pupd[] = { |
| 190 | MTK_PIN_PUPD_SPEC_SR(105, MSDC1_CTRL1, 8, 9, 10), |
| 191 | MTK_PIN_PUPD_SPEC_SR(106, MSDC1_CTRL0, 8, 9, 10), |
| 192 | MTK_PIN_PUPD_SPEC_SR(107, MSDC1_CTRL3, 0, 1, 2), |
| 193 | MTK_PIN_PUPD_SPEC_SR(108, MSDC1_CTRL3, 4, 5, 6), |
| 194 | MTK_PIN_PUPD_SPEC_SR(109, MSDC1_CTRL3, 8, 9, 10), |
| 195 | MTK_PIN_PUPD_SPEC_SR(110, MSDC1_CTRL3, 12, 13, 14), |
| 196 | MTK_PIN_PUPD_SPEC_SR(111, MSDC0_CTRL4, 12, 13, 14), |
| 197 | MTK_PIN_PUPD_SPEC_SR(112, MSDC0_CTRL4, 8, 9, 10), |
| 198 | MTK_PIN_PUPD_SPEC_SR(113, MSDC0_CTRL4, 4, 5, 6), |
| 199 | MTK_PIN_PUPD_SPEC_SR(114, MSDC0_CTRL4, 0, 1, 2), |
| 200 | MTK_PIN_PUPD_SPEC_SR(115, MSDC0_CTRL5, 0, 1, 2), |
| 201 | MTK_PIN_PUPD_SPEC_SR(116, MSDC0_CTRL1, 8, 9, 10), |
| 202 | MTK_PIN_PUPD_SPEC_SR(117, MSDC0_CTRL0, 8, 9, 10), |
| 203 | MTK_PIN_PUPD_SPEC_SR(118, MSDC0_CTRL3, 12, 13, 14), |
| 204 | MTK_PIN_PUPD_SPEC_SR(119, MSDC0_CTRL3, 8, 9, 10), |
| 205 | MTK_PIN_PUPD_SPEC_SR(120, MSDC0_CTRL3, 4, 5, 6), |
| 206 | MTK_PIN_PUPD_SPEC_SR(121, MSDC0_CTRL3, 0, 1, 2), |
| 207 | }; |
| 208 | |
| 209 | static int mt7623_spec_pull_set(struct regmap *regmap, unsigned int pin, |
| 210 | unsigned char align, bool isup, unsigned int r1r0) |
| 211 | { |
| 212 | return mtk_pctrl_spec_pull_set_samereg(regmap, mt7623_spec_pupd, |
| 213 | ARRAY_SIZE(mt7623_spec_pupd), pin, align, isup, r1r0); |
| 214 | } |
| 215 | |
| 216 | static const struct mtk_pin_ies_smt_set mt7623_ies_set[] = { |
| 217 | MTK_PIN_IES_SMT_SPEC(0, 6, IES_EN0, 0), |
| 218 | MTK_PIN_IES_SMT_SPEC(7, 9, IES_EN0, 1), |
| 219 | MTK_PIN_IES_SMT_SPEC(10, 13, IES_EN0, 2), |
| 220 | MTK_PIN_IES_SMT_SPEC(14, 15, IES_EN0, 3), |
| 221 | MTK_PIN_IES_SMT_SPEC(18, 21, IES_EN0, 5), |
| 222 | MTK_PIN_IES_SMT_SPEC(22, 26, IES_EN0, 6), |
| 223 | MTK_PIN_IES_SMT_SPEC(27, 29, IES_EN0, 7), |
| 224 | MTK_PIN_IES_SMT_SPEC(33, 37, IES_EN0, 8), |
| 225 | MTK_PIN_IES_SMT_SPEC(39, 42, IES_EN0, 9), |
| 226 | MTK_PIN_IES_SMT_SPEC(43, 45, IES_EN0, 10), |
| 227 | MTK_PIN_IES_SMT_SPEC(47, 48, IES_EN0, 11), |
| 228 | MTK_PIN_IES_SMT_SPEC(49, 49, IES_EN0, 12), |
| 229 | MTK_PIN_IES_SMT_SPEC(53, 56, IES_EN0, 14), |
| 230 | MTK_PIN_IES_SMT_SPEC(60, 62, IES_EN1, 0), |
| 231 | MTK_PIN_IES_SMT_SPEC(63, 65, IES_EN1, 1), |
| 232 | MTK_PIN_IES_SMT_SPEC(66, 71, IES_EN1, 2), |
| 233 | MTK_PIN_IES_SMT_SPEC(72, 74, IES_EN0, 12), |
| 234 | MTK_PIN_IES_SMT_SPEC(75, 76, IES_EN1, 3), |
| 235 | MTK_PIN_IES_SMT_SPEC(83, 84, IES_EN1, 2), |
| 236 | MTK_PIN_IES_SMT_SPEC(105, 121, MSDC1_CTRL1, 4), |
| 237 | MTK_PIN_IES_SMT_SPEC(122, 125, IES_EN1, 7), |
| 238 | MTK_PIN_IES_SMT_SPEC(126, 126, IES_EN0, 12), |
| 239 | MTK_PIN_IES_SMT_SPEC(199, 201, IES_EN0, 1), |
| 240 | MTK_PIN_IES_SMT_SPEC(203, 207, IES_EN2, 2), |
| 241 | MTK_PIN_IES_SMT_SPEC(208, 209, IES_EN2, 3), |
| 242 | MTK_PIN_IES_SMT_SPEC(236, 241, IES_EN2, 6), |
| 243 | MTK_PIN_IES_SMT_SPEC(242, 243, IES_EN2, 7), |
| 244 | MTK_PIN_IES_SMT_SPEC(261, 261, MSDC1_CTRL2, 4), |
| 245 | MTK_PIN_IES_SMT_SPEC(262, 272, IES_EN2, 12), |
| 246 | MTK_PIN_IES_SMT_SPEC(274, 276, IES_EN2, 12), |
| 247 | MTK_PIN_IES_SMT_SPEC(278, 278, IES_EN2, 13), |
| 248 | }; |
| 249 | |
| 250 | static const struct mtk_pin_ies_smt_set mt7623_smt_set[] = { |
| 251 | MTK_PIN_IES_SMT_SPEC(0, 6, SMT_EN0, 0), |
| 252 | MTK_PIN_IES_SMT_SPEC(7, 9, SMT_EN0, 1), |
| 253 | MTK_PIN_IES_SMT_SPEC(10, 13, SMT_EN0, 2), |
| 254 | MTK_PIN_IES_SMT_SPEC(14, 15, SMT_EN0, 3), |
| 255 | MTK_PIN_IES_SMT_SPEC(18, 21, SMT_EN0, 5), |
| 256 | MTK_PIN_IES_SMT_SPEC(22, 26, SMT_EN0, 6), |
| 257 | MTK_PIN_IES_SMT_SPEC(27, 29, SMT_EN0, 7), |
| 258 | MTK_PIN_IES_SMT_SPEC(33, 37, SMT_EN0, 8), |
| 259 | MTK_PIN_IES_SMT_SPEC(39, 42, SMT_EN0, 9), |
| 260 | MTK_PIN_IES_SMT_SPEC(43, 45, SMT_EN0, 10), |
| 261 | MTK_PIN_IES_SMT_SPEC(47, 48, SMT_EN0, 11), |
| 262 | MTK_PIN_IES_SMT_SPEC(49, 49, SMT_EN0, 12), |
| 263 | MTK_PIN_IES_SMT_SPEC(53, 56, SMT_EN0, 14), |
| 264 | MTK_PIN_IES_SMT_SPEC(60, 62, SMT_EN1, 0), |
| 265 | MTK_PIN_IES_SMT_SPEC(63, 65, SMT_EN1, 1), |
| 266 | MTK_PIN_IES_SMT_SPEC(66, 71, SMT_EN1, 2), |
| 267 | MTK_PIN_IES_SMT_SPEC(72, 74, SMT_EN0, 12), |
| 268 | MTK_PIN_IES_SMT_SPEC(75, 76, SMT_EN1, 3), |
| 269 | MTK_PIN_IES_SMT_SPEC(83, 84, SMT_EN1, 2), |
| 270 | MTK_PIN_IES_SMT_SPEC(105, 106, MSDC1_CTRL1, 11), |
| 271 | MTK_PIN_IES_SMT_SPEC(107, 107, MSDC1_CTRL3, 3), |
| 272 | MTK_PIN_IES_SMT_SPEC(108, 108, MSDC1_CTRL3, 7), |
| 273 | MTK_PIN_IES_SMT_SPEC(109, 109, MSDC1_CTRL3, 11), |
| 274 | MTK_PIN_IES_SMT_SPEC(110, 111, MSDC1_CTRL3, 15), |
| 275 | MTK_PIN_IES_SMT_SPEC(112, 112, MSDC0_CTRL4, 11), |
| 276 | MTK_PIN_IES_SMT_SPEC(113, 113, MSDC0_CTRL4, 7), |
| 277 | MTK_PIN_IES_SMT_SPEC(114, 115, MSDC0_CTRL4, 3), |
| 278 | MTK_PIN_IES_SMT_SPEC(116, 117, MSDC0_CTRL1, 11), |
| 279 | MTK_PIN_IES_SMT_SPEC(118, 118, MSDC0_CTRL3, 15), |
| 280 | MTK_PIN_IES_SMT_SPEC(119, 119, MSDC0_CTRL3, 11), |
| 281 | MTK_PIN_IES_SMT_SPEC(120, 120, MSDC0_CTRL3, 7), |
| 282 | MTK_PIN_IES_SMT_SPEC(121, 121, MSDC0_CTRL3, 3), |
| 283 | MTK_PIN_IES_SMT_SPEC(122, 125, SMT_EN1, 7), |
| 284 | MTK_PIN_IES_SMT_SPEC(126, 126, SMT_EN0, 12), |
| 285 | MTK_PIN_IES_SMT_SPEC(199, 201, SMT_EN0, 1), |
| 286 | MTK_PIN_IES_SMT_SPEC(203, 207, SMT_EN2, 2), |
| 287 | MTK_PIN_IES_SMT_SPEC(208, 209, SMT_EN2, 3), |
| 288 | MTK_PIN_IES_SMT_SPEC(236, 241, SMT_EN2, 6), |
| 289 | MTK_PIN_IES_SMT_SPEC(242, 243, SMT_EN2, 7), |
| 290 | MTK_PIN_IES_SMT_SPEC(261, 261, MSDC1_CTRL6, 3), |
| 291 | MTK_PIN_IES_SMT_SPEC(262, 272, SMT_EN2, 12), |
| 292 | MTK_PIN_IES_SMT_SPEC(274, 276, SMT_EN2, 12), |
| 293 | MTK_PIN_IES_SMT_SPEC(278, 278, SMT_EN2, 13), |
| 294 | }; |
| 295 | |
| 296 | static int mt7623_ies_smt_set(struct regmap *regmap, unsigned int pin, |
| 297 | unsigned char align, int value, enum pin_config_param arg) |
| 298 | { |
| 299 | if (arg == PIN_CONFIG_INPUT_ENABLE) |
| 300 | return mtk_pconf_spec_set_ies_smt_range(regmap, mt7623_ies_set, |
| 301 | ARRAY_SIZE(mt7623_ies_set), pin, align, value); |
| 302 | else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) |
| 303 | return mtk_pconf_spec_set_ies_smt_range(regmap, mt7623_smt_set, |
| 304 | ARRAY_SIZE(mt7623_smt_set), pin, align, value); |
| 305 | return -EINVAL; |
| 306 | } |
| 307 | |
| 308 | static const struct mtk_pinctrl_devdata mt7623_pinctrl_data = { |
| 309 | .pins = mtk_pins_mt7623, |
| 310 | .npins = ARRAY_SIZE(mtk_pins_mt7623), |
| 311 | .grp_desc = mt7623_drv_grp, |
| 312 | .n_grp_cls = ARRAY_SIZE(mt7623_drv_grp), |
| 313 | .pin_drv_grp = mt7623_pin_drv, |
| 314 | .n_pin_drv_grps = ARRAY_SIZE(mt7623_pin_drv), |
| 315 | .spec_pull_set = mt7623_spec_pull_set, |
| 316 | .spec_ies_smt_set = mt7623_ies_smt_set, |
| 317 | .dir_offset = 0x0000, |
| 318 | .pullen_offset = 0x0150, |
| 319 | .pullsel_offset = 0x0280, |
| 320 | .dout_offset = 0x0500, |
| 321 | .din_offset = 0x0630, |
| 322 | .pinmux_offset = 0x0760, |
| 323 | .type1_start = 280, |
| 324 | .type1_end = 280, |
| 325 | .port_shf = 4, |
| 326 | .port_mask = 0x1f, |
| 327 | .port_align = 4, |
| 328 | .eint_offsets = { |
| 329 | .name = "mt7623_eint", |
| 330 | .stat = 0x000, |
| 331 | .ack = 0x040, |
| 332 | .mask = 0x080, |
| 333 | .mask_set = 0x0c0, |
| 334 | .mask_clr = 0x100, |
| 335 | .sens = 0x140, |
| 336 | .sens_set = 0x180, |
| 337 | .sens_clr = 0x1c0, |
| 338 | .soft = 0x200, |
| 339 | .soft_set = 0x240, |
| 340 | .soft_clr = 0x280, |
| 341 | .pol = 0x300, |
| 342 | .pol_set = 0x340, |
| 343 | .pol_clr = 0x380, |
| 344 | .dom_en = 0x400, |
| 345 | .dbnc_ctrl = 0x500, |
| 346 | .dbnc_set = 0x600, |
| 347 | .dbnc_clr = 0x700, |
| 348 | .port_mask = 6, |
| 349 | .ports = 6, |
| 350 | }, |
| 351 | .ap_num = 169, |
| 352 | .db_cnt = 16, |
| 353 | }; |
| 354 | |
| 355 | static int mt7623_pinctrl_probe(struct platform_device *pdev) |
| 356 | { |
| 357 | return mtk_pctrl_init(pdev, &mt7623_pinctrl_data, NULL); |
| 358 | } |
| 359 | |
| 360 | static const struct of_device_id mt7623_pctrl_match[] = { |
| 361 | { .compatible = "mediatek,mt7623-pinctrl", }, |
| 362 | {} |
| 363 | }; |
| 364 | MODULE_DEVICE_TABLE(of, mt7623_pctrl_match); |
| 365 | |
| 366 | static struct platform_driver mtk_pinctrl_driver = { |
| 367 | .probe = mt7623_pinctrl_probe, |
| 368 | .driver = { |
| 369 | .name = "mediatek-mt7623-pinctrl", |
John Crispin | 87316f6 | 2016-02-19 08:17:18 +0100 | [diff] [blame] | 370 | .of_match_table = mt7623_pctrl_match, |
| 371 | }, |
| 372 | }; |
| 373 | |
| 374 | static int __init mtk_pinctrl_init(void) |
| 375 | { |
| 376 | return platform_driver_register(&mtk_pinctrl_driver); |
| 377 | } |
| 378 | |
| 379 | arch_initcall(mtk_pinctrl_init); |