Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver |
| 3 | * |
| 4 | * Copyright (C) 2013 Freescale Semiconductor, Inc. |
| 5 | * |
| 6 | * Based on stmp3xxx_spdif_dai.c |
| 7 | * Vladimir Barinov <vbarinov@embeddedalley.com> |
| 8 | * Copyright 2008 SigmaTel, Inc |
| 9 | * Copyright 2008 Embedded Alley Solutions, Inc |
| 10 | * |
| 11 | * This file is licensed under the terms of the GNU General Public License |
| 12 | * version 2. This program is licensed "as is" without any warranty of any |
| 13 | * kind, whether express or implied. |
| 14 | */ |
| 15 | |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/clk.h> |
| 18 | #include <linux/clk-private.h> |
| 19 | #include <linux/bitrev.h> |
| 20 | #include <linux/regmap.h> |
| 21 | #include <linux/of_address.h> |
| 22 | #include <linux/of_device.h> |
| 23 | #include <linux/of_irq.h> |
| 24 | |
| 25 | #include <sound/asoundef.h> |
| 26 | #include <sound/soc.h> |
| 27 | #include <sound/dmaengine_pcm.h> |
| 28 | |
| 29 | #include "fsl_spdif.h" |
| 30 | #include "imx-pcm.h" |
| 31 | |
| 32 | #define FSL_SPDIF_TXFIFO_WML 0x8 |
| 33 | #define FSL_SPDIF_RXFIFO_WML 0x8 |
| 34 | |
| 35 | #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC) |
| 36 | #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL | INT_URX_OV|\ |
| 37 | INT_QRX_FUL | INT_QRX_OV | INT_UQ_SYNC | INT_UQ_ERR |\ |
| 38 | INT_RXFIFO_RESYNC | INT_LOSS_LOCK | INT_DPLL_LOCKED) |
| 39 | |
| 40 | /* Index list for the values that has if (DPLL Locked) condition */ |
| 41 | static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb }; |
| 42 | #define SRPC_NODPLL_START1 0x5 |
| 43 | #define SRPC_NODPLL_START2 0xc |
| 44 | |
| 45 | #define DEFAULT_RXCLK_SRC 1 |
| 46 | |
| 47 | /* |
| 48 | * SPDIF control structure |
| 49 | * Defines channel status, subcode and Q sub |
| 50 | */ |
| 51 | struct spdif_mixer_control { |
| 52 | /* spinlock to access control data */ |
| 53 | spinlock_t ctl_lock; |
| 54 | |
| 55 | /* IEC958 channel tx status bit */ |
| 56 | unsigned char ch_status[4]; |
| 57 | |
| 58 | /* User bits */ |
| 59 | unsigned char subcode[2 * SPDIF_UBITS_SIZE]; |
| 60 | |
| 61 | /* Q subcode part of user bits */ |
| 62 | unsigned char qsub[2 * SPDIF_QSUB_SIZE]; |
| 63 | |
| 64 | /* Buffer offset for U/Q */ |
| 65 | u32 upos; |
| 66 | u32 qpos; |
| 67 | |
| 68 | /* Ready buffer index of the two buffers */ |
| 69 | u32 ready_buf; |
| 70 | }; |
| 71 | |
| 72 | struct fsl_spdif_priv { |
| 73 | struct spdif_mixer_control fsl_spdif_control; |
| 74 | struct snd_soc_dai_driver cpu_dai_drv; |
| 75 | struct platform_device *pdev; |
| 76 | struct regmap *regmap; |
| 77 | bool dpll_locked; |
Nicolin Chen | 527cda7 | 2014-04-30 18:54:08 +0800 | [diff] [blame^] | 78 | u16 txrate[SPDIF_TXRATE_MAX]; |
Nicolin Chen | e41a4a7 | 2014-04-30 18:54:06 +0800 | [diff] [blame] | 79 | u8 txclk_df[SPDIF_TXRATE_MAX]; |
Nicolin Chen | 27c647b | 2014-04-30 18:54:07 +0800 | [diff] [blame] | 80 | u8 sysclk_df[SPDIF_TXRATE_MAX]; |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 81 | u8 txclk_src[SPDIF_TXRATE_MAX]; |
| 82 | u8 rxclk_src; |
| 83 | struct clk *txclk[SPDIF_TXRATE_MAX]; |
| 84 | struct clk *rxclk; |
Nicolin Chen | 08f7336 | 2014-04-24 18:52:24 +0800 | [diff] [blame] | 85 | struct clk *coreclk; |
Nicolin Chen | 0b86439 | 2014-04-28 23:07:51 +0800 | [diff] [blame] | 86 | struct clk *sysclk; |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 87 | struct snd_dmaengine_dai_dma_data dma_params_tx; |
| 88 | struct snd_dmaengine_dai_dma_data dma_params_rx; |
| 89 | |
| 90 | /* The name space will be allocated dynamically */ |
| 91 | char name[0]; |
| 92 | }; |
| 93 | |
| 94 | |
| 95 | /* DPLL locked and lock loss interrupt handler */ |
| 96 | static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv) |
| 97 | { |
| 98 | struct regmap *regmap = spdif_priv->regmap; |
| 99 | struct platform_device *pdev = spdif_priv->pdev; |
| 100 | u32 locked; |
| 101 | |
| 102 | regmap_read(regmap, REG_SPDIF_SRPC, &locked); |
| 103 | locked &= SRPC_DPLL_LOCKED; |
| 104 | |
| 105 | dev_dbg(&pdev->dev, "isr: Rx dpll %s \n", |
| 106 | locked ? "locked" : "loss lock"); |
| 107 | |
| 108 | spdif_priv->dpll_locked = locked ? true : false; |
| 109 | } |
| 110 | |
| 111 | /* Receiver found illegal symbol interrupt handler */ |
| 112 | static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv) |
| 113 | { |
| 114 | struct regmap *regmap = spdif_priv->regmap; |
| 115 | struct platform_device *pdev = spdif_priv->pdev; |
| 116 | |
| 117 | dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n"); |
| 118 | |
| 119 | if (!spdif_priv->dpll_locked) { |
| 120 | /* DPLL unlocked seems no audio stream */ |
| 121 | regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0); |
| 122 | } |
| 123 | } |
| 124 | |
| 125 | /* U/Q Channel receive register full */ |
| 126 | static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name) |
| 127 | { |
| 128 | struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; |
| 129 | struct regmap *regmap = spdif_priv->regmap; |
| 130 | struct platform_device *pdev = spdif_priv->pdev; |
| 131 | u32 *pos, size, val, reg; |
| 132 | |
| 133 | switch (name) { |
| 134 | case 'U': |
| 135 | pos = &ctrl->upos; |
| 136 | size = SPDIF_UBITS_SIZE; |
| 137 | reg = REG_SPDIF_SRU; |
| 138 | break; |
| 139 | case 'Q': |
| 140 | pos = &ctrl->qpos; |
| 141 | size = SPDIF_QSUB_SIZE; |
| 142 | reg = REG_SPDIF_SRQ; |
| 143 | break; |
| 144 | default: |
| 145 | dev_err(&pdev->dev, "unsupported channel name\n"); |
| 146 | return; |
| 147 | } |
| 148 | |
| 149 | dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name); |
| 150 | |
| 151 | if (*pos >= size * 2) { |
| 152 | *pos = 0; |
| 153 | } else if (unlikely((*pos % size) + 3 > size)) { |
| 154 | dev_err(&pdev->dev, "User bit receivce buffer overflow\n"); |
| 155 | return; |
| 156 | } |
| 157 | |
| 158 | regmap_read(regmap, reg, &val); |
| 159 | ctrl->subcode[*pos++] = val >> 16; |
| 160 | ctrl->subcode[*pos++] = val >> 8; |
| 161 | ctrl->subcode[*pos++] = val; |
| 162 | } |
| 163 | |
| 164 | /* U/Q Channel sync found */ |
| 165 | static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv) |
| 166 | { |
| 167 | struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; |
| 168 | struct platform_device *pdev = spdif_priv->pdev; |
| 169 | |
| 170 | dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n"); |
| 171 | |
| 172 | /* U/Q buffer reset */ |
| 173 | if (ctrl->qpos == 0) |
| 174 | return; |
| 175 | |
| 176 | /* Set ready to this buffer */ |
| 177 | ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1; |
| 178 | } |
| 179 | |
| 180 | /* U/Q Channel framing error */ |
| 181 | static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv) |
| 182 | { |
| 183 | struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; |
| 184 | struct regmap *regmap = spdif_priv->regmap; |
| 185 | struct platform_device *pdev = spdif_priv->pdev; |
| 186 | u32 val; |
| 187 | |
| 188 | dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n"); |
| 189 | |
| 190 | /* Read U/Q data to clear the irq and do buffer reset */ |
| 191 | regmap_read(regmap, REG_SPDIF_SRU, &val); |
| 192 | regmap_read(regmap, REG_SPDIF_SRQ, &val); |
| 193 | |
| 194 | /* Drop this U/Q buffer */ |
| 195 | ctrl->ready_buf = 0; |
| 196 | ctrl->upos = 0; |
| 197 | ctrl->qpos = 0; |
| 198 | } |
| 199 | |
| 200 | /* Get spdif interrupt status and clear the interrupt */ |
| 201 | static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv) |
| 202 | { |
| 203 | struct regmap *regmap = spdif_priv->regmap; |
| 204 | u32 val, val2; |
| 205 | |
| 206 | regmap_read(regmap, REG_SPDIF_SIS, &val); |
| 207 | regmap_read(regmap, REG_SPDIF_SIE, &val2); |
| 208 | |
| 209 | regmap_write(regmap, REG_SPDIF_SIC, val & val2); |
| 210 | |
| 211 | return val; |
| 212 | } |
| 213 | |
| 214 | static irqreturn_t spdif_isr(int irq, void *devid) |
| 215 | { |
| 216 | struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid; |
| 217 | struct platform_device *pdev = spdif_priv->pdev; |
| 218 | u32 sis; |
| 219 | |
| 220 | sis = spdif_intr_status_clear(spdif_priv); |
| 221 | |
| 222 | if (sis & INT_DPLL_LOCKED) |
| 223 | spdif_irq_dpll_lock(spdif_priv); |
| 224 | |
| 225 | if (sis & INT_TXFIFO_UNOV) |
| 226 | dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n"); |
| 227 | |
| 228 | if (sis & INT_TXFIFO_RESYNC) |
| 229 | dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n"); |
| 230 | |
| 231 | if (sis & INT_CNEW) |
| 232 | dev_dbg(&pdev->dev, "isr: cstatus new\n"); |
| 233 | |
| 234 | if (sis & INT_VAL_NOGOOD) |
| 235 | dev_dbg(&pdev->dev, "isr: validity flag no good\n"); |
| 236 | |
| 237 | if (sis & INT_SYM_ERR) |
| 238 | spdif_irq_sym_error(spdif_priv); |
| 239 | |
| 240 | if (sis & INT_BIT_ERR) |
| 241 | dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n"); |
| 242 | |
| 243 | if (sis & INT_URX_FUL) |
| 244 | spdif_irq_uqrx_full(spdif_priv, 'U'); |
| 245 | |
| 246 | if (sis & INT_URX_OV) |
| 247 | dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n"); |
| 248 | |
| 249 | if (sis & INT_QRX_FUL) |
| 250 | spdif_irq_uqrx_full(spdif_priv, 'Q'); |
| 251 | |
| 252 | if (sis & INT_QRX_OV) |
| 253 | dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n"); |
| 254 | |
| 255 | if (sis & INT_UQ_SYNC) |
| 256 | spdif_irq_uq_sync(spdif_priv); |
| 257 | |
| 258 | if (sis & INT_UQ_ERR) |
| 259 | spdif_irq_uq_err(spdif_priv); |
| 260 | |
| 261 | if (sis & INT_RXFIFO_UNOV) |
| 262 | dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n"); |
| 263 | |
| 264 | if (sis & INT_RXFIFO_RESYNC) |
| 265 | dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n"); |
| 266 | |
| 267 | if (sis & INT_LOSS_LOCK) |
| 268 | spdif_irq_dpll_lock(spdif_priv); |
| 269 | |
| 270 | /* FIXME: Write Tx FIFO to clear TxEm */ |
| 271 | if (sis & INT_TX_EM) |
| 272 | dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n"); |
| 273 | |
| 274 | /* FIXME: Read Rx FIFO to clear RxFIFOFul */ |
| 275 | if (sis & INT_RXFIFO_FUL) |
| 276 | dev_dbg(&pdev->dev, "isr: Rx FIFO full\n"); |
| 277 | |
| 278 | return IRQ_HANDLED; |
| 279 | } |
| 280 | |
| 281 | static int spdif_softreset(struct fsl_spdif_priv *spdif_priv) |
| 282 | { |
| 283 | struct regmap *regmap = spdif_priv->regmap; |
| 284 | u32 val, cycle = 1000; |
| 285 | |
| 286 | regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET); |
| 287 | |
| 288 | /* |
| 289 | * RESET bit would be cleared after finishing its reset procedure, |
| 290 | * which typically lasts 8 cycles. 1000 cycles will keep it safe. |
| 291 | */ |
| 292 | do { |
| 293 | regmap_read(regmap, REG_SPDIF_SCR, &val); |
| 294 | } while ((val & SCR_SOFT_RESET) && cycle--); |
| 295 | |
| 296 | if (cycle) |
| 297 | return 0; |
| 298 | else |
| 299 | return -EBUSY; |
| 300 | } |
| 301 | |
| 302 | static void spdif_set_cstatus(struct spdif_mixer_control *ctrl, |
| 303 | u8 mask, u8 cstatus) |
| 304 | { |
| 305 | ctrl->ch_status[3] &= ~mask; |
| 306 | ctrl->ch_status[3] |= cstatus & mask; |
| 307 | } |
| 308 | |
| 309 | static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv) |
| 310 | { |
| 311 | struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; |
| 312 | struct regmap *regmap = spdif_priv->regmap; |
| 313 | struct platform_device *pdev = spdif_priv->pdev; |
| 314 | u32 ch_status; |
| 315 | |
| 316 | ch_status = (bitrev8(ctrl->ch_status[0]) << 16) | |
| 317 | (bitrev8(ctrl->ch_status[1]) << 8) | |
| 318 | bitrev8(ctrl->ch_status[2]); |
| 319 | regmap_write(regmap, REG_SPDIF_STCSCH, ch_status); |
| 320 | |
| 321 | dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status); |
| 322 | |
| 323 | ch_status = bitrev8(ctrl->ch_status[3]) << 16; |
| 324 | regmap_write(regmap, REG_SPDIF_STCSCL, ch_status); |
| 325 | |
| 326 | dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status); |
| 327 | } |
| 328 | |
| 329 | /* Set SPDIF PhaseConfig register for rx clock */ |
| 330 | static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv, |
| 331 | enum spdif_gainsel gainsel, int dpll_locked) |
| 332 | { |
| 333 | struct regmap *regmap = spdif_priv->regmap; |
| 334 | u8 clksrc = spdif_priv->rxclk_src; |
| 335 | |
| 336 | if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX) |
| 337 | return -EINVAL; |
| 338 | |
| 339 | regmap_update_bits(regmap, REG_SPDIF_SRPC, |
| 340 | SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK, |
| 341 | SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel)); |
| 342 | |
| 343 | return 0; |
| 344 | } |
| 345 | |
| 346 | static int spdif_set_sample_rate(struct snd_pcm_substream *substream, |
| 347 | int sample_rate) |
| 348 | { |
| 349 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 350 | struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
| 351 | struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; |
| 352 | struct regmap *regmap = spdif_priv->regmap; |
| 353 | struct platform_device *pdev = spdif_priv->pdev; |
| 354 | unsigned long csfs = 0; |
| 355 | u32 stc, mask, rate; |
Nicolin Chen | 27c647b | 2014-04-30 18:54:07 +0800 | [diff] [blame] | 356 | u8 clk, txclk_df, sysclk_df; |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 357 | int ret; |
| 358 | |
| 359 | switch (sample_rate) { |
| 360 | case 32000: |
| 361 | rate = SPDIF_TXRATE_32000; |
| 362 | csfs = IEC958_AES3_CON_FS_32000; |
| 363 | break; |
| 364 | case 44100: |
| 365 | rate = SPDIF_TXRATE_44100; |
| 366 | csfs = IEC958_AES3_CON_FS_44100; |
| 367 | break; |
| 368 | case 48000: |
| 369 | rate = SPDIF_TXRATE_48000; |
| 370 | csfs = IEC958_AES3_CON_FS_48000; |
| 371 | break; |
| 372 | default: |
| 373 | dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate); |
| 374 | return -EINVAL; |
| 375 | } |
| 376 | |
| 377 | clk = spdif_priv->txclk_src[rate]; |
| 378 | if (clk >= STC_TXCLK_SRC_MAX) { |
| 379 | dev_err(&pdev->dev, "tx clock source is out of range\n"); |
| 380 | return -EINVAL; |
| 381 | } |
| 382 | |
Nicolin Chen | e41a4a7 | 2014-04-30 18:54:06 +0800 | [diff] [blame] | 383 | txclk_df = spdif_priv->txclk_df[rate]; |
| 384 | if (txclk_df == 0) { |
| 385 | dev_err(&pdev->dev, "the txclk_df can't be zero\n"); |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 386 | return -EINVAL; |
| 387 | } |
| 388 | |
Nicolin Chen | 27c647b | 2014-04-30 18:54:07 +0800 | [diff] [blame] | 389 | sysclk_df = spdif_priv->sysclk_df[rate]; |
| 390 | |
Nicolin Chen | 9c6344b | 2014-04-30 18:54:05 +0800 | [diff] [blame] | 391 | /* Don't mess up the clocks from other modules */ |
| 392 | if (clk != STC_TXCLK_SPDIF_ROOT) |
| 393 | goto clk_set_bypass; |
| 394 | |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 395 | /* |
Nicolin Chen | e41a4a7 | 2014-04-30 18:54:06 +0800 | [diff] [blame] | 396 | * The S/PDIF block needs a clock of 64 * fs * txclk_df. |
| 397 | * So request 64 * fs * (txclk_df + 1) to get rounded. |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 398 | */ |
Nicolin Chen | e41a4a7 | 2014-04-30 18:54:06 +0800 | [diff] [blame] | 399 | ret = clk_set_rate(spdif_priv->txclk[rate], 64 * sample_rate * (txclk_df + 1)); |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 400 | if (ret) { |
| 401 | dev_err(&pdev->dev, "failed to set tx clock rate\n"); |
| 402 | return ret; |
| 403 | } |
| 404 | |
Nicolin Chen | 9c6344b | 2014-04-30 18:54:05 +0800 | [diff] [blame] | 405 | clk_set_bypass: |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 406 | dev_dbg(&pdev->dev, "expected clock rate = %d\n", |
Nicolin Chen | 27c647b | 2014-04-30 18:54:07 +0800 | [diff] [blame] | 407 | (64 * sample_rate * txclk_df * sysclk_df)); |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 408 | dev_dbg(&pdev->dev, "actual clock rate = %ld\n", |
| 409 | clk_get_rate(spdif_priv->txclk[rate])); |
| 410 | |
| 411 | /* set fs field in consumer channel status */ |
| 412 | spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs); |
| 413 | |
| 414 | /* select clock source and divisor */ |
Nicolin Chen | e41a4a7 | 2014-04-30 18:54:06 +0800 | [diff] [blame] | 415 | stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) | STC_TXCLK_DF(txclk_df); |
| 416 | mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK | STC_TXCLK_DF_MASK; |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 417 | regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc); |
| 418 | |
Nicolin Chen | 27c647b | 2014-04-30 18:54:07 +0800 | [diff] [blame] | 419 | regmap_update_bits(regmap, REG_SPDIF_STC, |
| 420 | STC_SYSCLK_DF_MASK, STC_SYSCLK_DF(sysclk_df)); |
| 421 | |
Nicolin Chen | 527cda7 | 2014-04-30 18:54:08 +0800 | [diff] [blame^] | 422 | dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n", |
| 423 | spdif_priv->txrate[rate], sample_rate); |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 424 | |
| 425 | return 0; |
| 426 | } |
| 427 | |
Mark Brown | 6b4c80f | 2013-08-31 16:40:51 +0100 | [diff] [blame] | 428 | static int fsl_spdif_startup(struct snd_pcm_substream *substream, |
| 429 | struct snd_soc_dai *cpu_dai) |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 430 | { |
| 431 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 432 | struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
| 433 | struct platform_device *pdev = spdif_priv->pdev; |
| 434 | struct regmap *regmap = spdif_priv->regmap; |
| 435 | u32 scr, mask, i; |
| 436 | int ret; |
| 437 | |
| 438 | /* Reset module and interrupts only for first initialization */ |
| 439 | if (!cpu_dai->active) { |
Nicolin Chen | 08f7336 | 2014-04-24 18:52:24 +0800 | [diff] [blame] | 440 | ret = clk_prepare_enable(spdif_priv->coreclk); |
| 441 | if (ret) { |
| 442 | dev_err(&pdev->dev, "failed to enable core clock\n"); |
| 443 | return ret; |
| 444 | } |
| 445 | |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 446 | ret = spdif_softreset(spdif_priv); |
| 447 | if (ret) { |
| 448 | dev_err(&pdev->dev, "failed to soft reset\n"); |
Nicolin Chen | 08f7336 | 2014-04-24 18:52:24 +0800 | [diff] [blame] | 449 | goto err; |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 450 | } |
| 451 | |
| 452 | /* Disable all the interrupts */ |
| 453 | regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0); |
| 454 | } |
| 455 | |
| 456 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
| 457 | scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL | |
| 458 | SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP | |
| 459 | SCR_TXFIFO_FSEL_IF8; |
| 460 | mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | |
| 461 | SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | |
| 462 | SCR_TXFIFO_FSEL_MASK; |
| 463 | for (i = 0; i < SPDIF_TXRATE_MAX; i++) |
| 464 | clk_prepare_enable(spdif_priv->txclk[i]); |
| 465 | } else { |
| 466 | scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC; |
| 467 | mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| |
| 468 | SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; |
| 469 | clk_prepare_enable(spdif_priv->rxclk); |
| 470 | } |
| 471 | regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); |
| 472 | |
| 473 | /* Power up SPDIF module */ |
| 474 | regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0); |
| 475 | |
| 476 | return 0; |
Nicolin Chen | 08f7336 | 2014-04-24 18:52:24 +0800 | [diff] [blame] | 477 | |
| 478 | err: |
| 479 | clk_disable_unprepare(spdif_priv->coreclk); |
| 480 | |
| 481 | return ret; |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 482 | } |
| 483 | |
| 484 | static void fsl_spdif_shutdown(struct snd_pcm_substream *substream, |
| 485 | struct snd_soc_dai *cpu_dai) |
| 486 | { |
| 487 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 488 | struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
| 489 | struct regmap *regmap = spdif_priv->regmap; |
| 490 | u32 scr, mask, i; |
| 491 | |
| 492 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
| 493 | scr = 0; |
| 494 | mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | |
| 495 | SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | |
| 496 | SCR_TXFIFO_FSEL_MASK; |
| 497 | for (i = 0; i < SPDIF_TXRATE_MAX; i++) |
| 498 | clk_disable_unprepare(spdif_priv->txclk[i]); |
| 499 | } else { |
| 500 | scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO; |
| 501 | mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| |
| 502 | SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; |
| 503 | clk_disable_unprepare(spdif_priv->rxclk); |
| 504 | } |
| 505 | regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); |
| 506 | |
| 507 | /* Power down SPDIF module only if tx&rx are both inactive */ |
| 508 | if (!cpu_dai->active) { |
| 509 | spdif_intr_status_clear(spdif_priv); |
| 510 | regmap_update_bits(regmap, REG_SPDIF_SCR, |
| 511 | SCR_LOW_POWER, SCR_LOW_POWER); |
Nicolin Chen | 08f7336 | 2014-04-24 18:52:24 +0800 | [diff] [blame] | 512 | clk_disable_unprepare(spdif_priv->coreclk); |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 513 | } |
| 514 | } |
| 515 | |
| 516 | static int fsl_spdif_hw_params(struct snd_pcm_substream *substream, |
| 517 | struct snd_pcm_hw_params *params, |
| 518 | struct snd_soc_dai *dai) |
| 519 | { |
| 520 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 521 | struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
| 522 | struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; |
| 523 | struct platform_device *pdev = spdif_priv->pdev; |
| 524 | u32 sample_rate = params_rate(params); |
| 525 | int ret = 0; |
| 526 | |
| 527 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
| 528 | ret = spdif_set_sample_rate(substream, sample_rate); |
| 529 | if (ret) { |
| 530 | dev_err(&pdev->dev, "%s: set sample rate failed: %d\n", |
| 531 | __func__, sample_rate); |
| 532 | return ret; |
| 533 | } |
| 534 | spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK, |
| 535 | IEC958_AES3_CON_CLOCK_1000PPM); |
| 536 | spdif_write_channel_status(spdif_priv); |
| 537 | } else { |
| 538 | /* Setup rx clock source */ |
| 539 | ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1); |
| 540 | } |
| 541 | |
| 542 | return ret; |
| 543 | } |
| 544 | |
| 545 | static int fsl_spdif_trigger(struct snd_pcm_substream *substream, |
| 546 | int cmd, struct snd_soc_dai *dai) |
| 547 | { |
| 548 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 549 | struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
| 550 | struct regmap *regmap = spdif_priv->regmap; |
| 551 | int is_playack = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
| 552 | u32 intr = is_playack ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE; |
| 553 | u32 dmaen = is_playack ? SCR_DMA_TX_EN : SCR_DMA_RX_EN;; |
| 554 | |
| 555 | switch (cmd) { |
| 556 | case SNDRV_PCM_TRIGGER_START: |
| 557 | case SNDRV_PCM_TRIGGER_RESUME: |
| 558 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
| 559 | regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr); |
| 560 | regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen); |
| 561 | break; |
| 562 | case SNDRV_PCM_TRIGGER_STOP: |
| 563 | case SNDRV_PCM_TRIGGER_SUSPEND: |
| 564 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
| 565 | regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0); |
| 566 | regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0); |
| 567 | break; |
| 568 | default: |
| 569 | return -EINVAL; |
| 570 | } |
| 571 | |
| 572 | return 0; |
| 573 | } |
| 574 | |
Mark Brown | 6b4c80f | 2013-08-31 16:40:51 +0100 | [diff] [blame] | 575 | static struct snd_soc_dai_ops fsl_spdif_dai_ops = { |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 576 | .startup = fsl_spdif_startup, |
| 577 | .hw_params = fsl_spdif_hw_params, |
| 578 | .trigger = fsl_spdif_trigger, |
| 579 | .shutdown = fsl_spdif_shutdown, |
| 580 | }; |
| 581 | |
| 582 | |
| 583 | /* |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 584 | * FSL SPDIF IEC958 controller(mixer) functions |
| 585 | * |
| 586 | * Channel status get/put control |
| 587 | * User bit value get/put control |
| 588 | * Valid bit value get control |
| 589 | * DPLL lock status get control |
| 590 | * User bit sync mode selection control |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 591 | */ |
| 592 | |
| 593 | static int fsl_spdif_info(struct snd_kcontrol *kcontrol, |
| 594 | struct snd_ctl_elem_info *uinfo) |
| 595 | { |
| 596 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; |
| 597 | uinfo->count = 1; |
| 598 | |
| 599 | return 0; |
| 600 | } |
| 601 | |
| 602 | static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol, |
| 603 | struct snd_ctl_elem_value *uvalue) |
| 604 | { |
| 605 | struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); |
| 606 | struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); |
| 607 | struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; |
| 608 | |
| 609 | uvalue->value.iec958.status[0] = ctrl->ch_status[0]; |
| 610 | uvalue->value.iec958.status[1] = ctrl->ch_status[1]; |
| 611 | uvalue->value.iec958.status[2] = ctrl->ch_status[2]; |
| 612 | uvalue->value.iec958.status[3] = ctrl->ch_status[3]; |
| 613 | |
| 614 | return 0; |
| 615 | } |
| 616 | |
| 617 | static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol, |
| 618 | struct snd_ctl_elem_value *uvalue) |
| 619 | { |
| 620 | struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); |
| 621 | struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); |
| 622 | struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; |
| 623 | |
| 624 | ctrl->ch_status[0] = uvalue->value.iec958.status[0]; |
| 625 | ctrl->ch_status[1] = uvalue->value.iec958.status[1]; |
| 626 | ctrl->ch_status[2] = uvalue->value.iec958.status[2]; |
| 627 | ctrl->ch_status[3] = uvalue->value.iec958.status[3]; |
| 628 | |
| 629 | spdif_write_channel_status(spdif_priv); |
| 630 | |
| 631 | return 0; |
| 632 | } |
| 633 | |
| 634 | /* Get channel status from SPDIF_RX_CCHAN register */ |
| 635 | static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol, |
| 636 | struct snd_ctl_elem_value *ucontrol) |
| 637 | { |
| 638 | struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); |
| 639 | struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); |
| 640 | struct regmap *regmap = spdif_priv->regmap; |
| 641 | u32 cstatus, val; |
| 642 | |
| 643 | regmap_read(regmap, REG_SPDIF_SIS, &val); |
| 644 | if (!(val & INT_CNEW)) { |
| 645 | return -EAGAIN; |
| 646 | } |
| 647 | |
| 648 | regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus); |
| 649 | ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF; |
| 650 | ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF; |
| 651 | ucontrol->value.iec958.status[2] = cstatus & 0xFF; |
| 652 | |
| 653 | regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus); |
| 654 | ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF; |
| 655 | ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF; |
| 656 | ucontrol->value.iec958.status[5] = cstatus & 0xFF; |
| 657 | |
| 658 | /* Clear intr */ |
| 659 | regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW); |
| 660 | |
| 661 | return 0; |
| 662 | } |
| 663 | |
| 664 | /* |
| 665 | * Get User bits (subcode) from chip value which readed out |
| 666 | * in UChannel register. |
| 667 | */ |
| 668 | static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol, |
| 669 | struct snd_ctl_elem_value *ucontrol) |
| 670 | { |
| 671 | struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); |
| 672 | struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); |
| 673 | struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; |
| 674 | unsigned long flags; |
| 675 | int ret = 0; |
| 676 | |
| 677 | spin_lock_irqsave(&ctrl->ctl_lock, flags); |
| 678 | if (ctrl->ready_buf) { |
| 679 | int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE; |
| 680 | memcpy(&ucontrol->value.iec958.subcode[0], |
| 681 | &ctrl->subcode[idx], SPDIF_UBITS_SIZE); |
| 682 | } else { |
| 683 | ret = -EAGAIN; |
| 684 | } |
| 685 | spin_unlock_irqrestore(&ctrl->ctl_lock, flags); |
| 686 | |
| 687 | return ret; |
| 688 | } |
| 689 | |
| 690 | /* Q-subcode infomation. The byte size is SPDIF_UBITS_SIZE/8 */ |
| 691 | static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol, |
| 692 | struct snd_ctl_elem_info *uinfo) |
| 693 | { |
| 694 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; |
| 695 | uinfo->count = SPDIF_QSUB_SIZE; |
| 696 | |
| 697 | return 0; |
| 698 | } |
| 699 | |
| 700 | /* Get Q subcode from chip value which readed out in QChannel register */ |
| 701 | static int fsl_spdif_qget(struct snd_kcontrol *kcontrol, |
| 702 | struct snd_ctl_elem_value *ucontrol) |
| 703 | { |
| 704 | struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); |
| 705 | struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); |
| 706 | struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; |
| 707 | unsigned long flags; |
| 708 | int ret = 0; |
| 709 | |
| 710 | spin_lock_irqsave(&ctrl->ctl_lock, flags); |
| 711 | if (ctrl->ready_buf) { |
| 712 | int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE; |
| 713 | memcpy(&ucontrol->value.bytes.data[0], |
| 714 | &ctrl->qsub[idx], SPDIF_QSUB_SIZE); |
| 715 | } else { |
| 716 | ret = -EAGAIN; |
| 717 | } |
| 718 | spin_unlock_irqrestore(&ctrl->ctl_lock, flags); |
| 719 | |
| 720 | return ret; |
| 721 | } |
| 722 | |
| 723 | /* Valid bit infomation */ |
| 724 | static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol, |
| 725 | struct snd_ctl_elem_info *uinfo) |
| 726 | { |
| 727 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; |
| 728 | uinfo->count = 1; |
| 729 | uinfo->value.integer.min = 0; |
| 730 | uinfo->value.integer.max = 1; |
| 731 | |
| 732 | return 0; |
| 733 | } |
| 734 | |
| 735 | /* Get valid good bit from interrupt status register */ |
| 736 | static int fsl_spdif_vbit_get(struct snd_kcontrol *kcontrol, |
| 737 | struct snd_ctl_elem_value *ucontrol) |
| 738 | { |
| 739 | struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); |
| 740 | struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); |
| 741 | struct regmap *regmap = spdif_priv->regmap; |
| 742 | u32 val; |
| 743 | |
| 744 | val = regmap_read(regmap, REG_SPDIF_SIS, &val); |
| 745 | ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0; |
| 746 | regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD); |
| 747 | |
| 748 | return 0; |
| 749 | } |
| 750 | |
| 751 | /* DPLL lock infomation */ |
| 752 | static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol, |
| 753 | struct snd_ctl_elem_info *uinfo) |
| 754 | { |
| 755 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; |
| 756 | uinfo->count = 1; |
| 757 | uinfo->value.integer.min = 16000; |
| 758 | uinfo->value.integer.max = 96000; |
| 759 | |
| 760 | return 0; |
| 761 | } |
| 762 | |
| 763 | static u32 gainsel_multi[GAINSEL_MULTI_MAX] = { |
| 764 | 24, 16, 12, 8, 6, 4, 3, |
| 765 | }; |
| 766 | |
| 767 | /* Get RX data clock rate given the SPDIF bus_clk */ |
| 768 | static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv, |
| 769 | enum spdif_gainsel gainsel) |
| 770 | { |
| 771 | struct regmap *regmap = spdif_priv->regmap; |
| 772 | struct platform_device *pdev = spdif_priv->pdev; |
| 773 | u64 tmpval64, busclk_freq = 0; |
| 774 | u32 freqmeas, phaseconf; |
| 775 | u8 clksrc; |
| 776 | |
| 777 | regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas); |
| 778 | regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf); |
| 779 | |
| 780 | clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf; |
| 781 | if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) { |
| 782 | /* Get bus clock from system */ |
Nicolin Chen | 0b86439 | 2014-04-28 23:07:51 +0800 | [diff] [blame] | 783 | busclk_freq = clk_get_rate(spdif_priv->sysclk); |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 784 | } |
| 785 | |
| 786 | /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */ |
| 787 | tmpval64 = (u64) busclk_freq * freqmeas; |
| 788 | do_div(tmpval64, gainsel_multi[gainsel] * 1024); |
| 789 | do_div(tmpval64, 128 * 1024); |
| 790 | |
| 791 | dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas); |
| 792 | dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq); |
| 793 | dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64); |
| 794 | |
| 795 | return (int)tmpval64; |
| 796 | } |
| 797 | |
| 798 | /* |
| 799 | * Get DPLL lock or not info from stable interrupt status register. |
| 800 | * User application must use this control to get locked, |
| 801 | * then can do next PCM operation |
| 802 | */ |
| 803 | static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol, |
| 804 | struct snd_ctl_elem_value *ucontrol) |
| 805 | { |
| 806 | struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); |
| 807 | struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); |
| 808 | int rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL); |
| 809 | |
| 810 | if (spdif_priv->dpll_locked) |
| 811 | ucontrol->value.integer.value[0] = rate; |
| 812 | else |
| 813 | ucontrol->value.integer.value[0] = 0; |
| 814 | |
| 815 | return 0; |
| 816 | } |
| 817 | |
| 818 | /* User bit sync mode info */ |
| 819 | static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol, |
| 820 | struct snd_ctl_elem_info *uinfo) |
| 821 | { |
| 822 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; |
| 823 | uinfo->count = 1; |
| 824 | uinfo->value.integer.min = 0; |
| 825 | uinfo->value.integer.max = 1; |
| 826 | |
| 827 | return 0; |
| 828 | } |
| 829 | |
| 830 | /* |
| 831 | * User bit sync mode: |
| 832 | * 1 CD User channel subcode |
| 833 | * 0 Non-CD data |
| 834 | */ |
| 835 | static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol, |
| 836 | struct snd_ctl_elem_value *ucontrol) |
| 837 | { |
| 838 | struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); |
| 839 | struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); |
| 840 | struct regmap *regmap = spdif_priv->regmap; |
| 841 | u32 val; |
| 842 | |
| 843 | regmap_read(regmap, REG_SPDIF_SRCD, &val); |
| 844 | ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0; |
| 845 | |
| 846 | return 0; |
| 847 | } |
| 848 | |
| 849 | /* |
| 850 | * User bit sync mode: |
| 851 | * 1 CD User channel subcode |
| 852 | * 0 Non-CD data |
| 853 | */ |
| 854 | static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol, |
| 855 | struct snd_ctl_elem_value *ucontrol) |
| 856 | { |
| 857 | struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); |
| 858 | struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); |
| 859 | struct regmap *regmap = spdif_priv->regmap; |
| 860 | u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET; |
| 861 | |
| 862 | regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val); |
| 863 | |
| 864 | return 0; |
| 865 | } |
| 866 | |
| 867 | /* FSL SPDIF IEC958 controller defines */ |
| 868 | static struct snd_kcontrol_new fsl_spdif_ctrls[] = { |
| 869 | /* Status cchanel controller */ |
| 870 | { |
| 871 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
| 872 | .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), |
| 873 | .access = SNDRV_CTL_ELEM_ACCESS_READ | |
| 874 | SNDRV_CTL_ELEM_ACCESS_WRITE | |
| 875 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, |
| 876 | .info = fsl_spdif_info, |
| 877 | .get = fsl_spdif_pb_get, |
| 878 | .put = fsl_spdif_pb_put, |
| 879 | }, |
| 880 | { |
| 881 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
| 882 | .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), |
| 883 | .access = SNDRV_CTL_ELEM_ACCESS_READ | |
| 884 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, |
| 885 | .info = fsl_spdif_info, |
| 886 | .get = fsl_spdif_capture_get, |
| 887 | }, |
| 888 | /* User bits controller */ |
| 889 | { |
| 890 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
| 891 | .name = "IEC958 Subcode Capture Default", |
| 892 | .access = SNDRV_CTL_ELEM_ACCESS_READ | |
| 893 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, |
| 894 | .info = fsl_spdif_info, |
| 895 | .get = fsl_spdif_subcode_get, |
| 896 | }, |
| 897 | { |
| 898 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
| 899 | .name = "IEC958 Q-subcode Capture Default", |
| 900 | .access = SNDRV_CTL_ELEM_ACCESS_READ | |
| 901 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, |
| 902 | .info = fsl_spdif_qinfo, |
| 903 | .get = fsl_spdif_qget, |
| 904 | }, |
| 905 | /* Valid bit error controller */ |
| 906 | { |
| 907 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
| 908 | .name = "IEC958 V-Bit Errors", |
| 909 | .access = SNDRV_CTL_ELEM_ACCESS_READ | |
| 910 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, |
| 911 | .info = fsl_spdif_vbit_info, |
| 912 | .get = fsl_spdif_vbit_get, |
| 913 | }, |
| 914 | /* DPLL lock info get controller */ |
| 915 | { |
| 916 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
| 917 | .name = "RX Sample Rate", |
| 918 | .access = SNDRV_CTL_ELEM_ACCESS_READ | |
| 919 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, |
| 920 | .info = fsl_spdif_rxrate_info, |
| 921 | .get = fsl_spdif_rxrate_get, |
| 922 | }, |
| 923 | /* User bit sync mode set/get controller */ |
| 924 | { |
| 925 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
| 926 | .name = "IEC958 USyncMode CDText", |
| 927 | .access = SNDRV_CTL_ELEM_ACCESS_READ | |
| 928 | SNDRV_CTL_ELEM_ACCESS_WRITE | |
| 929 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, |
| 930 | .info = fsl_spdif_usync_info, |
| 931 | .get = fsl_spdif_usync_get, |
| 932 | .put = fsl_spdif_usync_put, |
| 933 | }, |
| 934 | }; |
| 935 | |
| 936 | static int fsl_spdif_dai_probe(struct snd_soc_dai *dai) |
| 937 | { |
| 938 | struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai); |
| 939 | |
Xiubo Li | 05cf482 | 2014-01-20 15:27:26 +0800 | [diff] [blame] | 940 | snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx, |
| 941 | &spdif_private->dma_params_rx); |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 942 | |
| 943 | snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls)); |
| 944 | |
| 945 | return 0; |
| 946 | } |
| 947 | |
Mark Brown | 6b4c80f | 2013-08-31 16:40:51 +0100 | [diff] [blame] | 948 | static struct snd_soc_dai_driver fsl_spdif_dai = { |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 949 | .probe = &fsl_spdif_dai_probe, |
| 950 | .playback = { |
| 951 | .channels_min = 2, |
| 952 | .channels_max = 2, |
| 953 | .rates = FSL_SPDIF_RATES_PLAYBACK, |
| 954 | .formats = FSL_SPDIF_FORMATS_PLAYBACK, |
| 955 | }, |
| 956 | .capture = { |
| 957 | .channels_min = 2, |
| 958 | .channels_max = 2, |
| 959 | .rates = FSL_SPDIF_RATES_CAPTURE, |
| 960 | .formats = FSL_SPDIF_FORMATS_CAPTURE, |
| 961 | }, |
| 962 | .ops = &fsl_spdif_dai_ops, |
| 963 | }; |
| 964 | |
| 965 | static const struct snd_soc_component_driver fsl_spdif_component = { |
| 966 | .name = "fsl-spdif", |
| 967 | }; |
| 968 | |
Fabio Estevam | 6d22db4 | 2013-08-23 18:14:46 -0300 | [diff] [blame] | 969 | /* FSL SPDIF REGMAP */ |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 970 | |
| 971 | static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg) |
| 972 | { |
| 973 | switch (reg) { |
| 974 | case REG_SPDIF_SCR: |
| 975 | case REG_SPDIF_SRCD: |
| 976 | case REG_SPDIF_SRPC: |
| 977 | case REG_SPDIF_SIE: |
| 978 | case REG_SPDIF_SIS: |
| 979 | case REG_SPDIF_SRL: |
| 980 | case REG_SPDIF_SRR: |
| 981 | case REG_SPDIF_SRCSH: |
| 982 | case REG_SPDIF_SRCSL: |
| 983 | case REG_SPDIF_SRU: |
| 984 | case REG_SPDIF_SRQ: |
| 985 | case REG_SPDIF_STCSCH: |
| 986 | case REG_SPDIF_STCSCL: |
| 987 | case REG_SPDIF_SRFM: |
| 988 | case REG_SPDIF_STC: |
| 989 | return true; |
| 990 | default: |
| 991 | return false; |
Sachin Kamat | e19bcb6 | 2013-09-13 15:52:42 +0530 | [diff] [blame] | 992 | } |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 993 | } |
| 994 | |
| 995 | static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg) |
| 996 | { |
| 997 | switch (reg) { |
| 998 | case REG_SPDIF_SCR: |
| 999 | case REG_SPDIF_SRCD: |
| 1000 | case REG_SPDIF_SRPC: |
| 1001 | case REG_SPDIF_SIE: |
| 1002 | case REG_SPDIF_SIC: |
| 1003 | case REG_SPDIF_STL: |
| 1004 | case REG_SPDIF_STR: |
| 1005 | case REG_SPDIF_STCSCH: |
| 1006 | case REG_SPDIF_STCSCL: |
| 1007 | case REG_SPDIF_STC: |
| 1008 | return true; |
| 1009 | default: |
| 1010 | return false; |
Sachin Kamat | e19bcb6 | 2013-09-13 15:52:42 +0530 | [diff] [blame] | 1011 | } |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1012 | } |
| 1013 | |
Xiubo Li | 86f28d7 | 2014-02-11 15:42:48 +0800 | [diff] [blame] | 1014 | static struct regmap_config fsl_spdif_regmap_config = { |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1015 | .reg_bits = 32, |
| 1016 | .reg_stride = 4, |
| 1017 | .val_bits = 32, |
| 1018 | |
| 1019 | .max_register = REG_SPDIF_STC, |
| 1020 | .readable_reg = fsl_spdif_readable_reg, |
| 1021 | .writeable_reg = fsl_spdif_writeable_reg, |
| 1022 | }; |
| 1023 | |
| 1024 | static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv, |
| 1025 | struct clk *clk, u64 savesub, |
Nicolin Chen | 9c6344b | 2014-04-30 18:54:05 +0800 | [diff] [blame] | 1026 | enum spdif_txrate index, bool round) |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1027 | { |
| 1028 | const u32 rate[] = { 32000, 44100, 48000 }; |
Nicolin Chen | 27c647b | 2014-04-30 18:54:07 +0800 | [diff] [blame] | 1029 | bool is_sysclk = clk == spdif_priv->sysclk; |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1030 | u64 rate_ideal, rate_actual, sub; |
Nicolin Chen | 27c647b | 2014-04-30 18:54:07 +0800 | [diff] [blame] | 1031 | u32 sysclk_dfmin, sysclk_dfmax; |
| 1032 | u32 txclk_df, sysclk_df, arate; |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1033 | |
Nicolin Chen | 27c647b | 2014-04-30 18:54:07 +0800 | [diff] [blame] | 1034 | /* The sysclk has an extra divisor [2, 512] */ |
| 1035 | sysclk_dfmin = is_sysclk ? 2 : 1; |
| 1036 | sysclk_dfmax = is_sysclk ? 512 : 1; |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1037 | |
Nicolin Chen | 27c647b | 2014-04-30 18:54:07 +0800 | [diff] [blame] | 1038 | for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) { |
| 1039 | for (txclk_df = 1; txclk_df <= 128; txclk_df++) { |
| 1040 | rate_ideal = rate[index] * (txclk_df + 1) * 64; |
| 1041 | if (round) |
| 1042 | rate_actual = clk_round_rate(clk, rate_ideal); |
| 1043 | else |
| 1044 | rate_actual = clk_get_rate(clk); |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1045 | |
Nicolin Chen | 27c647b | 2014-04-30 18:54:07 +0800 | [diff] [blame] | 1046 | arate = rate_actual / 64; |
| 1047 | arate /= txclk_df * sysclk_df; |
| 1048 | |
| 1049 | if (arate == rate[index]) { |
| 1050 | /* We are lucky */ |
| 1051 | savesub = 0; |
| 1052 | spdif_priv->txclk_df[index] = txclk_df; |
| 1053 | spdif_priv->sysclk_df[index] = sysclk_df; |
Nicolin Chen | 527cda7 | 2014-04-30 18:54:08 +0800 | [diff] [blame^] | 1054 | spdif_priv->txrate[index] = arate; |
Nicolin Chen | 27c647b | 2014-04-30 18:54:07 +0800 | [diff] [blame] | 1055 | goto out; |
| 1056 | } else if (arate / rate[index] == 1) { |
| 1057 | /* A little bigger than expect */ |
| 1058 | sub = (arate - rate[index]) * 100000; |
| 1059 | do_div(sub, rate[index]); |
| 1060 | if (sub >= savesub) |
| 1061 | continue; |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1062 | savesub = sub; |
Nicolin Chen | e41a4a7 | 2014-04-30 18:54:06 +0800 | [diff] [blame] | 1063 | spdif_priv->txclk_df[index] = txclk_df; |
Nicolin Chen | 27c647b | 2014-04-30 18:54:07 +0800 | [diff] [blame] | 1064 | spdif_priv->sysclk_df[index] = sysclk_df; |
Nicolin Chen | 527cda7 | 2014-04-30 18:54:08 +0800 | [diff] [blame^] | 1065 | spdif_priv->txrate[index] = arate; |
Nicolin Chen | 27c647b | 2014-04-30 18:54:07 +0800 | [diff] [blame] | 1066 | } else if (rate[index] / arate == 1) { |
| 1067 | /* A little smaller than expect */ |
| 1068 | sub = (rate[index] - arate) * 100000; |
| 1069 | do_div(sub, rate[index]); |
| 1070 | if (sub >= savesub) |
| 1071 | continue; |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1072 | savesub = sub; |
Nicolin Chen | e41a4a7 | 2014-04-30 18:54:06 +0800 | [diff] [blame] | 1073 | spdif_priv->txclk_df[index] = txclk_df; |
Nicolin Chen | 27c647b | 2014-04-30 18:54:07 +0800 | [diff] [blame] | 1074 | spdif_priv->sysclk_df[index] = sysclk_df; |
Nicolin Chen | 527cda7 | 2014-04-30 18:54:08 +0800 | [diff] [blame^] | 1075 | spdif_priv->txrate[index] = arate; |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1076 | } |
| 1077 | } |
| 1078 | } |
| 1079 | |
Nicolin Chen | 27c647b | 2014-04-30 18:54:07 +0800 | [diff] [blame] | 1080 | out: |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1081 | return savesub; |
| 1082 | } |
| 1083 | |
| 1084 | static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv, |
| 1085 | enum spdif_txrate index) |
| 1086 | { |
| 1087 | const u32 rate[] = { 32000, 44100, 48000 }; |
| 1088 | struct platform_device *pdev = spdif_priv->pdev; |
| 1089 | struct device *dev = &pdev->dev; |
| 1090 | u64 savesub = 100000, ret; |
| 1091 | struct clk *clk; |
| 1092 | char tmp[16]; |
| 1093 | int i; |
| 1094 | |
| 1095 | for (i = 0; i < STC_TXCLK_SRC_MAX; i++) { |
| 1096 | sprintf(tmp, "rxtx%d", i); |
| 1097 | clk = devm_clk_get(&pdev->dev, tmp); |
| 1098 | if (IS_ERR(clk)) { |
| 1099 | dev_err(dev, "no rxtx%d clock in devicetree\n", i); |
| 1100 | return PTR_ERR(clk); |
| 1101 | } |
| 1102 | if (!clk_get_rate(clk)) |
| 1103 | continue; |
| 1104 | |
Nicolin Chen | 9c6344b | 2014-04-30 18:54:05 +0800 | [diff] [blame] | 1105 | ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index, |
| 1106 | i == STC_TXCLK_SPDIF_ROOT); |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1107 | if (savesub == ret) |
| 1108 | continue; |
| 1109 | |
| 1110 | savesub = ret; |
| 1111 | spdif_priv->txclk[index] = clk; |
| 1112 | spdif_priv->txclk_src[index] = i; |
| 1113 | |
| 1114 | /* To quick catch a divisor, we allow a 0.1% deviation */ |
| 1115 | if (savesub < 100) |
| 1116 | break; |
| 1117 | } |
| 1118 | |
Nicolin Chen | 8a309d7 | 2013-08-30 17:38:08 +0800 | [diff] [blame] | 1119 | dev_dbg(&pdev->dev, "use rxtx%d as tx clock source for %dHz sample rate\n", |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1120 | spdif_priv->txclk_src[index], rate[index]); |
Nicolin Chen | e41a4a7 | 2014-04-30 18:54:06 +0800 | [diff] [blame] | 1121 | dev_dbg(&pdev->dev, "use txclk df %d for %dHz sample rate\n", |
| 1122 | spdif_priv->txclk_df[index], rate[index]); |
Nicolin Chen | 27c647b | 2014-04-30 18:54:07 +0800 | [diff] [blame] | 1123 | if (spdif_priv->txclk[index] == spdif_priv->sysclk) |
| 1124 | dev_dbg(&pdev->dev, "use sysclk df %d for %dHz sample rate\n", |
| 1125 | spdif_priv->sysclk_df[index], rate[index]); |
Nicolin Chen | 527cda7 | 2014-04-30 18:54:08 +0800 | [diff] [blame^] | 1126 | dev_dbg(&pdev->dev, "the best rate for %dHz sample rate is %dHz\n", |
| 1127 | rate[index], spdif_priv->txrate[index]); |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1128 | |
| 1129 | return 0; |
| 1130 | } |
| 1131 | |
| 1132 | static int fsl_spdif_probe(struct platform_device *pdev) |
| 1133 | { |
| 1134 | struct device_node *np = pdev->dev.of_node; |
| 1135 | struct fsl_spdif_priv *spdif_priv; |
| 1136 | struct spdif_mixer_control *ctrl; |
| 1137 | struct resource *res; |
| 1138 | void __iomem *regs; |
| 1139 | int irq, ret, i; |
| 1140 | |
| 1141 | if (!np) |
| 1142 | return -ENODEV; |
| 1143 | |
| 1144 | spdif_priv = devm_kzalloc(&pdev->dev, |
| 1145 | sizeof(struct fsl_spdif_priv) + strlen(np->name) + 1, |
| 1146 | GFP_KERNEL); |
| 1147 | if (!spdif_priv) |
| 1148 | return -ENOMEM; |
| 1149 | |
| 1150 | strcpy(spdif_priv->name, np->name); |
| 1151 | |
| 1152 | spdif_priv->pdev = pdev; |
| 1153 | |
| 1154 | /* Initialize this copy of the CPU DAI driver structure */ |
| 1155 | memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai)); |
| 1156 | spdif_priv->cpu_dai_drv.name = spdif_priv->name; |
| 1157 | |
Xiubo Li | 86f28d7 | 2014-02-11 15:42:48 +0800 | [diff] [blame] | 1158 | if (of_property_read_bool(np, "big-endian")) |
| 1159 | fsl_spdif_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG; |
| 1160 | |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1161 | /* Get the addresses and IRQ */ |
| 1162 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1163 | regs = devm_ioremap_resource(&pdev->dev, res); |
Wei Yongjun | bfd7d1a | 2013-08-29 08:00:05 +0800 | [diff] [blame] | 1164 | if (IS_ERR(regs)) |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1165 | return PTR_ERR(regs); |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1166 | |
| 1167 | spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, |
| 1168 | "core", regs, &fsl_spdif_regmap_config); |
| 1169 | if (IS_ERR(spdif_priv->regmap)) { |
| 1170 | dev_err(&pdev->dev, "regmap init failed\n"); |
| 1171 | return PTR_ERR(spdif_priv->regmap); |
| 1172 | } |
| 1173 | |
| 1174 | irq = platform_get_irq(pdev, 0); |
| 1175 | if (irq < 0) { |
| 1176 | dev_err(&pdev->dev, "no irq for node %s\n", np->full_name); |
| 1177 | return irq; |
| 1178 | } |
| 1179 | |
| 1180 | ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0, |
| 1181 | spdif_priv->name, spdif_priv); |
| 1182 | if (ret) { |
| 1183 | dev_err(&pdev->dev, "could not claim irq %u\n", irq); |
| 1184 | return ret; |
| 1185 | } |
| 1186 | |
Nicolin Chen | 0b86439 | 2014-04-28 23:07:51 +0800 | [diff] [blame] | 1187 | /* Get system clock for rx clock rate calculation */ |
| 1188 | spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5"); |
| 1189 | if (IS_ERR(spdif_priv->sysclk)) { |
| 1190 | dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n"); |
| 1191 | return PTR_ERR(spdif_priv->sysclk); |
| 1192 | } |
| 1193 | |
Nicolin Chen | 08f7336 | 2014-04-24 18:52:24 +0800 | [diff] [blame] | 1194 | /* Get core clock for data register access via DMA */ |
| 1195 | spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core"); |
| 1196 | if (IS_ERR(spdif_priv->coreclk)) { |
| 1197 | dev_err(&pdev->dev, "no core clock in devicetree\n"); |
| 1198 | return PTR_ERR(spdif_priv->coreclk); |
| 1199 | } |
| 1200 | |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1201 | /* Select clock source for rx/tx clock */ |
| 1202 | spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1"); |
| 1203 | if (IS_ERR(spdif_priv->rxclk)) { |
| 1204 | dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n"); |
| 1205 | return PTR_ERR(spdif_priv->rxclk); |
| 1206 | } |
| 1207 | spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC; |
| 1208 | |
| 1209 | for (i = 0; i < SPDIF_TXRATE_MAX; i++) { |
| 1210 | ret = fsl_spdif_probe_txclk(spdif_priv, i); |
| 1211 | if (ret) |
| 1212 | return ret; |
| 1213 | } |
| 1214 | |
| 1215 | /* Initial spinlock for control data */ |
| 1216 | ctrl = &spdif_priv->fsl_spdif_control; |
| 1217 | spin_lock_init(&ctrl->ctl_lock); |
| 1218 | |
| 1219 | /* Init tx channel status default value */ |
| 1220 | ctrl->ch_status[0] = |
| 1221 | IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_5015; |
| 1222 | ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID; |
| 1223 | ctrl->ch_status[2] = 0x00; |
| 1224 | ctrl->ch_status[3] = |
| 1225 | IEC958_AES3_CON_FS_44100 | IEC958_AES3_CON_CLOCK_1000PPM; |
| 1226 | |
| 1227 | spdif_priv->dpll_locked = false; |
| 1228 | |
| 1229 | spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML; |
| 1230 | spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML; |
| 1231 | spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL; |
| 1232 | spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL; |
| 1233 | |
| 1234 | /* Register with ASoC */ |
| 1235 | dev_set_drvdata(&pdev->dev, spdif_priv); |
| 1236 | |
Sachin Kamat | 256218a | 2013-09-17 10:13:49 +0530 | [diff] [blame] | 1237 | ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component, |
| 1238 | &spdif_priv->cpu_dai_drv, 1); |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1239 | if (ret) { |
| 1240 | dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); |
Fabio Estevam | 5af407c | 2013-08-23 18:14:45 -0300 | [diff] [blame] | 1241 | return ret; |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1242 | } |
| 1243 | |
| 1244 | ret = imx_pcm_dma_init(pdev); |
Sachin Kamat | 256218a | 2013-09-17 10:13:49 +0530 | [diff] [blame] | 1245 | if (ret) |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1246 | dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret); |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1247 | |
| 1248 | return ret; |
| 1249 | } |
| 1250 | |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1251 | static const struct of_device_id fsl_spdif_dt_ids[] = { |
| 1252 | { .compatible = "fsl,imx35-spdif", }, |
| 1253 | {} |
| 1254 | }; |
| 1255 | MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids); |
| 1256 | |
| 1257 | static struct platform_driver fsl_spdif_driver = { |
| 1258 | .driver = { |
| 1259 | .name = "fsl-spdif-dai", |
| 1260 | .owner = THIS_MODULE, |
| 1261 | .of_match_table = fsl_spdif_dt_ids, |
| 1262 | }, |
| 1263 | .probe = fsl_spdif_probe, |
Nicolin Chen | a2388a4 | 2013-08-21 11:13:16 +0800 | [diff] [blame] | 1264 | }; |
| 1265 | |
| 1266 | module_platform_driver(fsl_spdif_driver); |
| 1267 | |
| 1268 | MODULE_AUTHOR("Freescale Semiconductor, Inc."); |
| 1269 | MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver"); |
| 1270 | MODULE_LICENSE("GPL v2"); |
| 1271 | MODULE_ALIAS("platform:fsl-spdif-dai"); |