Dave Kleikamp | 3162d92 | 2010-02-08 11:51:05 +0000 | [diff] [blame] | 1 | GDB intends to support the following hardware debug features of BookE |
| 2 | processors: |
| 3 | |
| 4 | 4 hardware breakpoints (IAC) |
| 5 | 2 hardware watchpoints (read, write and read-write) (DAC) |
| 6 | 2 value conditions for the hardware watchpoints (DVC) |
| 7 | |
| 8 | For that, we need to extend ptrace so that GDB can query and set these |
| 9 | resources. Since we're extending, we're trying to create an interface |
| 10 | that's extendable and that covers both BookE and server processors, so |
| 11 | that GDB doesn't need to special-case each of them. We added the |
| 12 | following 3 new ptrace requests. |
| 13 | |
| 14 | 1. PTRACE_PPC_GETHWDEBUGINFO |
| 15 | |
| 16 | Query for GDB to discover the hardware debug features. The main info to |
| 17 | be returned here is the minimum alignment for the hardware watchpoints. |
| 18 | BookE processors don't have restrictions here, but server processors have |
| 19 | an 8-byte alignment restriction for hardware watchpoints. We'd like to avoid |
| 20 | adding special cases to GDB based on what it sees in AUXV. |
| 21 | |
| 22 | Since we're at it, we added other useful info that the kernel can return to |
| 23 | GDB: this query will return the number of hardware breakpoints, hardware |
| 24 | watchpoints and whether it supports a range of addresses and a condition. |
| 25 | The query will fill the following structure provided by the requesting process: |
| 26 | |
| 27 | struct ppc_debug_info { |
| 28 | unit32_t version; |
| 29 | unit32_t num_instruction_bps; |
| 30 | unit32_t num_data_bps; |
| 31 | unit32_t num_condition_regs; |
| 32 | unit32_t data_bp_alignment; |
| 33 | unit32_t sizeof_condition; /* size of the DVC register */ |
| 34 | uint64_t features; /* bitmask of the individual flags */ |
| 35 | }; |
| 36 | |
| 37 | features will have bits indicating whether there is support for: |
| 38 | |
| 39 | #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1 |
| 40 | #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2 |
| 41 | #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4 |
| 42 | #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8 |
Michael Neuling | 517b731 | 2013-03-21 20:12:33 +0000 | [diff] [blame] | 43 | #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10 |
Dave Kleikamp | 3162d92 | 2010-02-08 11:51:05 +0000 | [diff] [blame] | 44 | |
| 45 | 2. PTRACE_SETHWDEBUG |
| 46 | |
| 47 | Sets a hardware breakpoint or watchpoint, according to the provided structure: |
| 48 | |
| 49 | struct ppc_hw_breakpoint { |
| 50 | uint32_t version; |
| 51 | #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1 |
| 52 | #define PPC_BREAKPOINT_TRIGGER_READ 0x2 |
| 53 | #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4 |
| 54 | uint32_t trigger_type; /* only some combinations allowed */ |
| 55 | #define PPC_BREAKPOINT_MODE_EXACT 0x0 |
| 56 | #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1 |
| 57 | #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2 |
| 58 | #define PPC_BREAKPOINT_MODE_MASK 0x3 |
| 59 | uint32_t addr_mode; /* address match mode */ |
| 60 | |
| 61 | #define PPC_BREAKPOINT_CONDITION_MODE 0x3 |
| 62 | #define PPC_BREAKPOINT_CONDITION_NONE 0x0 |
| 63 | #define PPC_BREAKPOINT_CONDITION_AND 0x1 |
| 64 | #define PPC_BREAKPOINT_CONDITION_EXACT 0x1 /* different name for the same thing as above */ |
| 65 | #define PPC_BREAKPOINT_CONDITION_OR 0x2 |
| 66 | #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3 |
| 67 | #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 /* byte enable bits */ |
| 68 | #define PPC_BREAKPOINT_CONDITION_BE(n) (1<<((n)+16)) |
| 69 | uint32_t condition_mode; /* break/watchpoint condition flags */ |
| 70 | |
| 71 | uint64_t addr; |
| 72 | uint64_t addr2; |
| 73 | uint64_t condition_value; |
| 74 | }; |
| 75 | |
| 76 | A request specifies one event, not necessarily just one register to be set. |
| 77 | For instance, if the request is for a watchpoint with a condition, both the |
| 78 | DAC and DVC registers will be set in the same request. |
| 79 | |
| 80 | With this GDB can ask for all kinds of hardware breakpoints and watchpoints |
| 81 | that the BookE supports. COMEFROM breakpoints available in server processors |
| 82 | are not contemplated, but that is out of the scope of this work. |
| 83 | |
| 84 | ptrace will return an integer (handle) uniquely identifying the breakpoint or |
| 85 | watchpoint just created. This integer will be used in the PTRACE_DELHWDEBUG |
| 86 | request to ask for its removal. Return -ENOSPC if the requested breakpoint |
| 87 | can't be allocated on the registers. |
| 88 | |
| 89 | Some examples of using the structure to: |
| 90 | |
| 91 | - set a breakpoint in the first breakpoint register |
| 92 | |
| 93 | p.version = PPC_DEBUG_CURRENT_VERSION; |
| 94 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; |
| 95 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; |
| 96 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
| 97 | p.addr = (uint64_t) address; |
| 98 | p.addr2 = 0; |
| 99 | p.condition_value = 0; |
| 100 | |
| 101 | - set a watchpoint which triggers on reads in the second watchpoint register |
| 102 | |
| 103 | p.version = PPC_DEBUG_CURRENT_VERSION; |
| 104 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_READ; |
| 105 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; |
| 106 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
| 107 | p.addr = (uint64_t) address; |
| 108 | p.addr2 = 0; |
| 109 | p.condition_value = 0; |
| 110 | |
| 111 | - set a watchpoint which triggers only with a specific value |
| 112 | |
| 113 | p.version = PPC_DEBUG_CURRENT_VERSION; |
| 114 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_READ; |
| 115 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; |
| 116 | p.condition_mode = PPC_BREAKPOINT_CONDITION_AND | PPC_BREAKPOINT_CONDITION_BE_ALL; |
| 117 | p.addr = (uint64_t) address; |
| 118 | p.addr2 = 0; |
| 119 | p.condition_value = (uint64_t) condition; |
| 120 | |
| 121 | - set a ranged hardware breakpoint |
| 122 | |
| 123 | p.version = PPC_DEBUG_CURRENT_VERSION; |
| 124 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; |
| 125 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; |
| 126 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
| 127 | p.addr = (uint64_t) begin_range; |
| 128 | p.addr2 = (uint64_t) end_range; |
| 129 | p.condition_value = 0; |
| 130 | |
K.Prasad | 6c7a285 | 2012-10-28 15:13:15 +0000 | [diff] [blame] | 131 | - set a watchpoint in server processors (BookS) |
| 132 | |
| 133 | p.version = 1; |
| 134 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_RW; |
| 135 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; |
| 136 | or |
| 137 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; |
| 138 | |
| 139 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
| 140 | p.addr = (uint64_t) begin_range; |
| 141 | /* For PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE addr2 needs to be specified, where |
| 142 | * addr2 - addr <= 8 Bytes. |
| 143 | */ |
| 144 | p.addr2 = (uint64_t) end_range; |
| 145 | p.condition_value = 0; |
| 146 | |
Dave Kleikamp | 3162d92 | 2010-02-08 11:51:05 +0000 | [diff] [blame] | 147 | 3. PTRACE_DELHWDEBUG |
| 148 | |
| 149 | Takes an integer which identifies an existing breakpoint or watchpoint |
| 150 | (i.e., the value returned from PTRACE_SETHWDEBUG), and deletes the |
| 151 | corresponding breakpoint or watchpoint.. |