blob: fa1326e5a4b06d61c2c5fc7756121acc4a8f44bc [file] [log] [blame]
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -07001/*
2 * Intel 3200/3210 Memory Controller kernel module
3 * Copyright (C) 2008-2009 Akamai Technologies, Inc.
4 * Portions by Hitoshi Mitake <h.mitake@gmail.com>.
5 *
6 * This file may be distributed under the terms of the
7 * GNU General Public License.
8 */
9
10#include <linux/module.h>
11#include <linux/init.h>
12#include <linux/pci.h>
13#include <linux/pci_ids.h>
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -070014#include <linux/edac.h>
15#include <linux/io.h>
16#include "edac_core.h"
17
Hitoshi Mitake797a7962012-02-07 11:45:33 +090018#include <asm-generic/io-64-nonatomic-lo-hi.h>
19
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -070020#define I3200_REVISION "1.1"
21
22#define EDAC_MOD_STR "i3200_edac"
23
24#define PCI_DEVICE_ID_INTEL_3200_HB 0x29f0
25
Mauro Carvalho Chehab95b93282012-04-16 15:09:38 -030026#define I3200_DIMMS 4
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -070027#define I3200_RANKS 8
28#define I3200_RANKS_PER_CHANNEL 4
29#define I3200_CHANNELS 2
30
31/* Intel 3200 register addresses - device 0 function 0 - DRAM Controller */
32
33#define I3200_MCHBAR_LOW 0x48 /* MCH Memory Mapped Register BAR */
34#define I3200_MCHBAR_HIGH 0x4c
35#define I3200_MCHBAR_MASK 0xfffffc000ULL /* bits 35:14 */
36#define I3200_MMR_WINDOW_SIZE 16384
37
38#define I3200_TOM 0xa0 /* Top of Memory (16b)
39 *
40 * 15:10 reserved
41 * 9:0 total populated physical memory
42 */
43#define I3200_TOM_MASK 0x3ff /* bits 9:0 */
44#define I3200_TOM_SHIFT 26 /* 64MiB grain */
45
46#define I3200_ERRSTS 0xc8 /* Error Status Register (16b)
47 *
48 * 15 reserved
49 * 14 Isochronous TBWRR Run Behind FIFO Full
50 * (ITCV)
51 * 13 Isochronous TBWRR Run Behind FIFO Put
52 * (ITSTV)
53 * 12 reserved
54 * 11 MCH Thermal Sensor Event
55 * for SMI/SCI/SERR (GTSE)
56 * 10 reserved
57 * 9 LOCK to non-DRAM Memory Flag (LCKF)
58 * 8 reserved
59 * 7 DRAM Throttle Flag (DTF)
60 * 6:2 reserved
61 * 1 Multi-bit DRAM ECC Error Flag (DMERR)
62 * 0 Single-bit DRAM ECC Error Flag (DSERR)
63 */
64#define I3200_ERRSTS_UE 0x0002
65#define I3200_ERRSTS_CE 0x0001
66#define I3200_ERRSTS_BITS (I3200_ERRSTS_UE | I3200_ERRSTS_CE)
67
68
69/* Intel MMIO register space - device 0 function 0 - MMR space */
70
71#define I3200_C0DRB 0x200 /* Channel 0 DRAM Rank Boundary (16b x 4)
72 *
73 * 15:10 reserved
74 * 9:0 Channel 0 DRAM Rank Boundary Address
75 */
76#define I3200_C1DRB 0x600 /* Channel 1 DRAM Rank Boundary (16b x 4) */
77#define I3200_DRB_MASK 0x3ff /* bits 9:0 */
78#define I3200_DRB_SHIFT 26 /* 64MiB grain */
79
80#define I3200_C0ECCERRLOG 0x280 /* Channel 0 ECC Error Log (64b)
81 *
82 * 63:48 Error Column Address (ERRCOL)
83 * 47:32 Error Row Address (ERRROW)
84 * 31:29 Error Bank Address (ERRBANK)
85 * 28:27 Error Rank Address (ERRRANK)
86 * 26:24 reserved
87 * 23:16 Error Syndrome (ERRSYND)
88 * 15: 2 reserved
89 * 1 Multiple Bit Error Status (MERRSTS)
90 * 0 Correctable Error Status (CERRSTS)
91 */
92#define I3200_C1ECCERRLOG 0x680 /* Chan 1 ECC Error Log (64b) */
93#define I3200_ECCERRLOG_CE 0x1
94#define I3200_ECCERRLOG_UE 0x2
95#define I3200_ECCERRLOG_RANK_BITS 0x18000000
96#define I3200_ECCERRLOG_RANK_SHIFT 27
97#define I3200_ECCERRLOG_SYNDROME_BITS 0xff0000
98#define I3200_ECCERRLOG_SYNDROME_SHIFT 16
99#define I3200_CAPID0 0xe0 /* P.95 of spec for details */
100
101struct i3200_priv {
102 void __iomem *window;
103};
104
105static int nr_channels;
106
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700107static int how_many_channels(struct pci_dev *pdev)
108{
Mauro Carvalho Chehab5f466cb2013-01-10 13:31:43 -0300109 int n_channels;
110
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700111 unsigned char capid0_8b; /* 8th byte of CAPID0 */
112
113 pci_read_config_byte(pdev, I3200_CAPID0 + 8, &capid0_8b);
Mauro Carvalho Chehab5f466cb2013-01-10 13:31:43 -0300114
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700115 if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */
Joe Perches956b9ba2012-04-29 17:08:39 -0300116 edac_dbg(0, "In single channel mode\n");
Mauro Carvalho Chehab5f466cb2013-01-10 13:31:43 -0300117 n_channels = 1;
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700118 } else {
Joe Perches956b9ba2012-04-29 17:08:39 -0300119 edac_dbg(0, "In dual channel mode\n");
Mauro Carvalho Chehab5f466cb2013-01-10 13:31:43 -0300120 n_channels = 2;
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700121 }
Mauro Carvalho Chehab5f466cb2013-01-10 13:31:43 -0300122
123 if (capid0_8b & 0x10) /* check if both channels are filled */
124 edac_dbg(0, "2 DIMMS per channel disabled\n");
125 else
126 edac_dbg(0, "2 DIMMS per channel enabled\n");
127
128 return n_channels;
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700129}
130
131static unsigned long eccerrlog_syndrome(u64 log)
132{
133 return (log & I3200_ECCERRLOG_SYNDROME_BITS) >>
134 I3200_ECCERRLOG_SYNDROME_SHIFT;
135}
136
137static int eccerrlog_row(int channel, u64 log)
138{
139 u64 rank = ((log & I3200_ECCERRLOG_RANK_BITS) >>
140 I3200_ECCERRLOG_RANK_SHIFT);
141 return rank | (channel * I3200_RANKS_PER_CHANNEL);
142}
143
144enum i3200_chips {
145 I3200 = 0,
146};
147
148struct i3200_dev_info {
149 const char *ctl_name;
150};
151
152struct i3200_error_info {
153 u16 errsts;
154 u16 errsts2;
155 u64 eccerrlog[I3200_CHANNELS];
156};
157
158static const struct i3200_dev_info i3200_devs[] = {
159 [I3200] = {
160 .ctl_name = "i3200"
161 },
162};
163
164static struct pci_dev *mci_pdev;
165static int i3200_registered = 1;
166
167
168static void i3200_clear_error_info(struct mem_ctl_info *mci)
169{
170 struct pci_dev *pdev;
171
Mauro Carvalho Chehabfd687502012-03-16 07:44:18 -0300172 pdev = to_pci_dev(mci->pdev);
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700173
174 /*
175 * Clear any error bits.
176 * (Yes, we really clear bits by writing 1 to them.)
177 */
178 pci_write_bits16(pdev, I3200_ERRSTS, I3200_ERRSTS_BITS,
179 I3200_ERRSTS_BITS);
180}
181
182static void i3200_get_and_clear_error_info(struct mem_ctl_info *mci,
183 struct i3200_error_info *info)
184{
185 struct pci_dev *pdev;
186 struct i3200_priv *priv = mci->pvt_info;
187 void __iomem *window = priv->window;
188
Mauro Carvalho Chehabfd687502012-03-16 07:44:18 -0300189 pdev = to_pci_dev(mci->pdev);
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700190
191 /*
192 * This is a mess because there is no atomic way to read all the
193 * registers at once and the registers can transition from CE being
194 * overwritten by UE.
195 */
196 pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts);
197 if (!(info->errsts & I3200_ERRSTS_BITS))
198 return;
199
200 info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);
201 if (nr_channels == 2)
202 info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);
203
204 pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts2);
205
206 /*
207 * If the error is the same for both reads then the first set
208 * of reads is valid. If there is a change then there is a CE
209 * with no info and the second set of reads is valid and
210 * should be UE info.
211 */
212 if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) {
213 info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);
214 if (nr_channels == 2)
215 info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);
216 }
217
218 i3200_clear_error_info(mci);
219}
220
221static void i3200_process_error_info(struct mem_ctl_info *mci,
222 struct i3200_error_info *info)
223{
224 int channel;
225 u64 log;
226
227 if (!(info->errsts & I3200_ERRSTS_BITS))
228 return;
229
230 if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) {
Mauro Carvalho Chehab9eb07a72012-06-04 13:27:43 -0300231 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
Mauro Carvalho Chehab03f7eae2012-06-04 11:29:25 -0300232 -1, -1, -1, "UE overwrote CE", "");
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700233 info->errsts = info->errsts2;
234 }
235
236 for (channel = 0; channel < nr_channels; channel++) {
237 log = info->eccerrlog[channel];
238 if (log & I3200_ECCERRLOG_UE) {
Mauro Carvalho Chehab9eb07a72012-06-04 13:27:43 -0300239 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
Mauro Carvalho Chehab95b93282012-04-16 15:09:38 -0300240 0, 0, 0,
241 eccerrlog_row(channel, log),
242 -1, -1,
Mauro Carvalho Chehab03f7eae2012-06-04 11:29:25 -0300243 "i3000 UE", "");
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700244 } else if (log & I3200_ECCERRLOG_CE) {
Mauro Carvalho Chehab9eb07a72012-06-04 13:27:43 -0300245 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
Mauro Carvalho Chehab95b93282012-04-16 15:09:38 -0300246 0, 0, eccerrlog_syndrome(log),
247 eccerrlog_row(channel, log),
248 -1, -1,
Mauro Carvalho Chehab03f7eae2012-06-04 11:29:25 -0300249 "i3000 UE", "");
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700250 }
251 }
252}
253
254static void i3200_check(struct mem_ctl_info *mci)
255{
256 struct i3200_error_info info;
257
Joe Perches956b9ba2012-04-29 17:08:39 -0300258 edac_dbg(1, "MC%d\n", mci->mc_idx);
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700259 i3200_get_and_clear_error_info(mci, &info);
260 i3200_process_error_info(mci, &info);
261}
262
Jingoo Han166e9332013-08-09 18:02:45 +0900263static void __iomem *i3200_map_mchbar(struct pci_dev *pdev)
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700264{
265 union {
266 u64 mchbar;
267 struct {
268 u32 mchbar_low;
269 u32 mchbar_high;
270 };
271 } u;
272 void __iomem *window;
273
274 pci_read_config_dword(pdev, I3200_MCHBAR_LOW, &u.mchbar_low);
275 pci_read_config_dword(pdev, I3200_MCHBAR_HIGH, &u.mchbar_high);
276 u.mchbar &= I3200_MCHBAR_MASK;
277
278 if (u.mchbar != (resource_size_t)u.mchbar) {
279 printk(KERN_ERR
280 "i3200: mmio space beyond accessible range (0x%llx)\n",
281 (unsigned long long)u.mchbar);
282 return NULL;
283 }
284
285 window = ioremap_nocache(u.mchbar, I3200_MMR_WINDOW_SIZE);
286 if (!window)
287 printk(KERN_ERR "i3200: cannot map mmio space at 0x%llx\n",
288 (unsigned long long)u.mchbar);
289
290 return window;
291}
292
293
294static void i3200_get_drbs(void __iomem *window,
295 u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL])
296{
297 int i;
298
299 for (i = 0; i < I3200_RANKS_PER_CHANNEL; i++) {
300 drbs[0][i] = readw(window + I3200_C0DRB + 2*i) & I3200_DRB_MASK;
301 drbs[1][i] = readw(window + I3200_C1DRB + 2*i) & I3200_DRB_MASK;
Mauro Carvalho Chehab5f466cb2013-01-10 13:31:43 -0300302
303 edac_dbg(0, "drb[0][%d] = %d, drb[1][%d] = %d\n", i, drbs[0][i], i, drbs[1][i]);
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700304 }
305}
306
307static bool i3200_is_stacked(struct pci_dev *pdev,
308 u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL])
309{
310 u16 tom;
311
312 pci_read_config_word(pdev, I3200_TOM, &tom);
313 tom &= I3200_TOM_MASK;
314
315 return drbs[I3200_CHANNELS - 1][I3200_RANKS_PER_CHANNEL - 1] == tom;
316}
317
318static unsigned long drb_to_nr_pages(
319 u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL], bool stacked,
320 int channel, int rank)
321{
322 int n;
323
324 n = drbs[channel][rank];
Mauro Carvalho Chehab61734e12013-01-10 13:31:47 -0300325 if (!n)
326 return 0;
327
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700328 if (rank > 0)
329 n -= drbs[channel][rank - 1];
330 if (stacked && (channel == 1) &&
331 drbs[channel][rank] == drbs[channel][I3200_RANKS_PER_CHANNEL - 1])
332 n -= drbs[0][I3200_RANKS_PER_CHANNEL - 1];
333
334 n <<= (I3200_DRB_SHIFT - PAGE_SHIFT);
335 return n;
336}
337
338static int i3200_probe1(struct pci_dev *pdev, int dev_idx)
339{
340 int rc;
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300341 int i, j;
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700342 struct mem_ctl_info *mci = NULL;
Mauro Carvalho Chehab95b93282012-04-16 15:09:38 -0300343 struct edac_mc_layer layers[2];
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700344 u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL];
345 bool stacked;
346 void __iomem *window;
347 struct i3200_priv *priv;
348
Joe Perches956b9ba2012-04-29 17:08:39 -0300349 edac_dbg(0, "MC:\n");
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700350
351 window = i3200_map_mchbar(pdev);
352 if (!window)
353 return -ENODEV;
354
355 i3200_get_drbs(window, drbs);
356 nr_channels = how_many_channels(pdev);
357
Mauro Carvalho Chehab95b93282012-04-16 15:09:38 -0300358 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
359 layers[0].size = I3200_DIMMS;
360 layers[0].is_virt_csrow = true;
361 layers[1].type = EDAC_MC_LAYER_CHANNEL;
362 layers[1].size = nr_channels;
363 layers[1].is_virt_csrow = false;
Mauro Carvalho Chehabca0907b2012-05-02 14:37:00 -0300364 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
Mauro Carvalho Chehab95b93282012-04-16 15:09:38 -0300365 sizeof(struct i3200_priv));
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700366 if (!mci)
367 return -ENOMEM;
368
Joe Perches956b9ba2012-04-29 17:08:39 -0300369 edac_dbg(3, "MC: init mci\n");
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700370
Mauro Carvalho Chehabfd687502012-03-16 07:44:18 -0300371 mci->pdev = &pdev->dev;
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700372 mci->mtype_cap = MEM_FLAG_DDR2;
373
374 mci->edac_ctl_cap = EDAC_FLAG_SECDED;
375 mci->edac_cap = EDAC_FLAG_SECDED;
376
377 mci->mod_name = EDAC_MOD_STR;
378 mci->mod_ver = I3200_REVISION;
379 mci->ctl_name = i3200_devs[dev_idx].ctl_name;
380 mci->dev_name = pci_name(pdev);
381 mci->edac_check = i3200_check;
382 mci->ctl_page_to_phys = NULL;
383 priv = mci->pvt_info;
384 priv->window = window;
385
386 stacked = i3200_is_stacked(pdev, drbs);
387
388 /*
389 * The dram rank boundary (DRB) reg values are boundary addresses
390 * for each DRAM rank with a granularity of 64MB. DRB regs are
391 * cumulative; the last one will contain the total memory
392 * contained in all ranks.
393 */
Mauro Carvalho Chehab61734e12013-01-10 13:31:47 -0300394 for (i = 0; i < I3200_DIMMS; i++) {
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700395 unsigned long nr_pages;
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700396
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300397 for (j = 0; j < nr_channels; j++) {
Mauro Carvalho Chehab61734e12013-01-10 13:31:47 -0300398 struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
399 mci->n_layers, i, j, 0);
400
401 nr_pages = drb_to_nr_pages(drbs, stacked, j, i);
402 if (nr_pages == 0)
403 continue;
404
405 edac_dbg(0, "csrow %d, channel %d%s, size = %ld Mb\n", i, j,
406 stacked ? " (stacked)" : "", PAGES_TO_MiB(nr_pages));
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300407
Mauro Carvalho Chehab582a8992012-08-02 17:58:23 -0300408 dimm->nr_pages = nr_pages;
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300409 dimm->grain = nr_pages << PAGE_SHIFT;
410 dimm->mtype = MEM_DDR2;
411 dimm->dtype = DEV_UNKNOWN;
412 dimm->edac_mode = EDAC_UNKNOWN;
413 }
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700414 }
415
416 i3200_clear_error_info(mci);
417
418 rc = -ENODEV;
419 if (edac_mc_add_mc(mci)) {
Joe Perches956b9ba2012-04-29 17:08:39 -0300420 edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700421 goto fail;
422 }
423
424 /* get this far and it's successful */
Joe Perches956b9ba2012-04-29 17:08:39 -0300425 edac_dbg(3, "MC: success\n");
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700426 return 0;
427
428fail:
429 iounmap(window);
430 if (mci)
431 edac_mc_free(mci);
432
433 return rc;
434}
435
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800436static int i3200_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700437{
438 int rc;
439
Joe Perches956b9ba2012-04-29 17:08:39 -0300440 edac_dbg(0, "MC:\n");
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700441
442 if (pci_enable_device(pdev) < 0)
443 return -EIO;
444
445 rc = i3200_probe1(pdev, ent->driver_data);
446 if (!mci_pdev)
447 mci_pdev = pci_dev_get(pdev);
448
449 return rc;
450}
451
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800452static void i3200_remove_one(struct pci_dev *pdev)
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700453{
454 struct mem_ctl_info *mci;
455 struct i3200_priv *priv;
456
Joe Perches956b9ba2012-04-29 17:08:39 -0300457 edac_dbg(0, "\n");
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700458
459 mci = edac_mc_del_mc(&pdev->dev);
460 if (!mci)
461 return;
462
463 priv = mci->pvt_info;
464 iounmap(priv->window);
465
466 edac_mc_free(mci);
467}
468
Jingoo Hanba935f42013-12-06 10:23:08 +0100469static const struct pci_device_id i3200_pci_tbl[] = {
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700470 {
471 PCI_VEND_DEV(INTEL, 3200_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
472 I3200},
473 {
474 0,
475 } /* 0 terminated list. */
476};
477
478MODULE_DEVICE_TABLE(pci, i3200_pci_tbl);
479
480static struct pci_driver i3200_driver = {
481 .name = EDAC_MOD_STR,
482 .probe = i3200_init_one,
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800483 .remove = i3200_remove_one,
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700484 .id_table = i3200_pci_tbl,
485};
486
487static int __init i3200_init(void)
488{
489 int pci_rc;
490
Joe Perches956b9ba2012-04-29 17:08:39 -0300491 edac_dbg(3, "MC:\n");
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700492
493 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
494 opstate_init();
495
496 pci_rc = pci_register_driver(&i3200_driver);
497 if (pci_rc < 0)
498 goto fail0;
499
500 if (!mci_pdev) {
501 i3200_registered = 0;
502 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
503 PCI_DEVICE_ID_INTEL_3200_HB, NULL);
504 if (!mci_pdev) {
Joe Perches956b9ba2012-04-29 17:08:39 -0300505 edac_dbg(0, "i3200 pci_get_device fail\n");
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700506 pci_rc = -ENODEV;
507 goto fail1;
508 }
509
510 pci_rc = i3200_init_one(mci_pdev, i3200_pci_tbl);
511 if (pci_rc < 0) {
Joe Perches956b9ba2012-04-29 17:08:39 -0300512 edac_dbg(0, "i3200 init fail\n");
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700513 pci_rc = -ENODEV;
514 goto fail1;
515 }
516 }
517
518 return 0;
519
520fail1:
521 pci_unregister_driver(&i3200_driver);
522
523fail0:
524 if (mci_pdev)
525 pci_dev_put(mci_pdev);
526
527 return pci_rc;
528}
529
530static void __exit i3200_exit(void)
531{
Joe Perches956b9ba2012-04-29 17:08:39 -0300532 edac_dbg(3, "MC:\n");
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700533
534 pci_unregister_driver(&i3200_driver);
535 if (!i3200_registered) {
536 i3200_remove_one(mci_pdev);
537 pci_dev_put(mci_pdev);
538 }
539}
540
541module_init(i3200_init);
542module_exit(i3200_exit);
543
544MODULE_LICENSE("GPL");
545MODULE_AUTHOR("Akamai Technologies, Inc.");
546MODULE_DESCRIPTION("MC support for Intel 3200 memory hub controllers");
547
548module_param(edac_op_state, int, 0444);
549MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");