Hisashi Nakamura | 0d0771ab | 2013-09-04 12:45:57 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Device Tree Source for the r8a7791 SoC |
| 3 | * |
Kazuya Mizuguchi | 118e4e6 | 2015-02-19 10:43:10 -0500 | [diff] [blame] | 4 | * Copyright (C) 2013-2015 Renesas Electronics Corporation |
Sergei Shtylyov | 2e5d55c | 2014-02-20 02:27:04 +0300 | [diff] [blame] | 5 | * Copyright (C) 2013-2014 Renesas Solutions Corp. |
| 6 | * Copyright (C) 2014 Cogent Embedded Inc. |
Hisashi Nakamura | 0d0771ab | 2013-09-04 12:45:57 +0900 | [diff] [blame] | 7 | * |
| 8 | * This file is licensed under the terms of the GNU General Public License |
| 9 | * version 2. This program is licensed "as is" without any warranty of any |
| 10 | * kind, whether express or implied. |
| 11 | */ |
| 12 | |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 13 | #include <dt-bindings/clock/r8a7791-clock.h> |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 14 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 15 | #include <dt-bindings/interrupt-controller/irq.h> |
| 16 | |
Hisashi Nakamura | 0d0771ab | 2013-09-04 12:45:57 +0900 | [diff] [blame] | 17 | / { |
| 18 | compatible = "renesas,r8a7791"; |
| 19 | interrupt-parent = <&gic>; |
| 20 | #address-cells = <2>; |
| 21 | #size-cells = <2>; |
| 22 | |
Wolfram Sang | 5bd3de7 | 2014-02-17 11:44:41 +0100 | [diff] [blame] | 23 | aliases { |
| 24 | i2c0 = &i2c0; |
| 25 | i2c1 = &i2c1; |
| 26 | i2c2 = &i2c2; |
| 27 | i2c3 = &i2c3; |
| 28 | i2c4 = &i2c4; |
| 29 | i2c5 = &i2c5; |
Wolfram Sang | 36408d9 | 2014-03-10 12:26:58 +0100 | [diff] [blame] | 30 | i2c6 = &i2c6; |
| 31 | i2c7 = &i2c7; |
| 32 | i2c8 = &i2c8; |
Geert Uytterhoeven | 6f3e4ee | 2014-02-25 11:30:14 +0100 | [diff] [blame] | 33 | spi0 = &qspi; |
Geert Uytterhoeven | 7713d3a | 2014-02-25 11:30:16 +0100 | [diff] [blame] | 34 | spi1 = &msiof0; |
| 35 | spi2 = &msiof1; |
| 36 | spi3 = &msiof2; |
Sergei Shtylyov | 0b8d1d5 | 2014-08-02 04:04:21 +0400 | [diff] [blame] | 37 | vin0 = &vin0; |
| 38 | vin1 = &vin1; |
| 39 | vin2 = &vin2; |
Wolfram Sang | 5bd3de7 | 2014-02-17 11:44:41 +0100 | [diff] [blame] | 40 | }; |
| 41 | |
Hisashi Nakamura | 0d0771ab | 2013-09-04 12:45:57 +0900 | [diff] [blame] | 42 | cpus { |
| 43 | #address-cells = <1>; |
| 44 | #size-cells = <0>; |
| 45 | |
| 46 | cpu0: cpu@0 { |
| 47 | device_type = "cpu"; |
| 48 | compatible = "arm,cortex-a15"; |
| 49 | reg = <0>; |
Magnus Damm | 896b79d | 2014-03-06 12:15:36 +0900 | [diff] [blame] | 50 | clock-frequency = <1500000000>; |
Gaku Inami | a57004ec | 2014-06-03 21:03:10 +0900 | [diff] [blame] | 51 | voltage-tolerance = <1>; /* 1% */ |
| 52 | clocks = <&cpg_clocks R8A7791_CLK_Z>; |
| 53 | clock-latency = <300000>; /* 300 us */ |
| 54 | |
| 55 | /* kHz - uV - OPPs unknown yet */ |
| 56 | operating-points = <1500000 1000000>, |
| 57 | <1312500 1000000>, |
| 58 | <1125000 1000000>, |
| 59 | < 937500 1000000>, |
| 60 | < 750000 1000000>, |
| 61 | < 375000 1000000>; |
Hisashi Nakamura | 0d0771ab | 2013-09-04 12:45:57 +0900 | [diff] [blame] | 62 | }; |
Magnus Damm | 15ab426 | 2013-10-01 17:13:07 +0900 | [diff] [blame] | 63 | |
| 64 | cpu1: cpu@1 { |
| 65 | device_type = "cpu"; |
| 66 | compatible = "arm,cortex-a15"; |
| 67 | reg = <1>; |
Magnus Damm | 896b79d | 2014-03-06 12:15:36 +0900 | [diff] [blame] | 68 | clock-frequency = <1500000000>; |
Magnus Damm | 15ab426 | 2013-10-01 17:13:07 +0900 | [diff] [blame] | 69 | }; |
Hisashi Nakamura | 0d0771ab | 2013-09-04 12:45:57 +0900 | [diff] [blame] | 70 | }; |
| 71 | |
| 72 | gic: interrupt-controller@f1001000 { |
Geert Uytterhoeven | d238b5e | 2015-06-17 15:03:34 +0200 | [diff] [blame] | 73 | compatible = "arm,gic-400"; |
Hisashi Nakamura | 0d0771ab | 2013-09-04 12:45:57 +0900 | [diff] [blame] | 74 | #interrupt-cells = <3>; |
| 75 | #address-cells = <0>; |
| 76 | interrupt-controller; |
| 77 | reg = <0 0xf1001000 0 0x1000>, |
| 78 | <0 0xf1002000 0 0x1000>, |
| 79 | <0 0xf1004000 0 0x2000>, |
| 80 | <0 0xf1006000 0 0x2000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 81 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
Hisashi Nakamura | 0d0771ab | 2013-09-04 12:45:57 +0900 | [diff] [blame] | 82 | }; |
Magnus Damm | d77db73 | 2013-10-01 17:12:29 +0900 | [diff] [blame] | 83 | |
Magnus Damm | 89fbba1 | 2013-11-21 14:22:00 +0900 | [diff] [blame] | 84 | gpio0: gpio@e6050000 { |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 85 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
Magnus Damm | 89fbba1 | 2013-11-21 14:22:00 +0900 | [diff] [blame] | 86 | reg = <0 0xe6050000 0 0x50>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 87 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 88 | #gpio-cells = <2>; |
| 89 | gpio-controller; |
| 90 | gpio-ranges = <&pfc 0 0 32>; |
| 91 | #interrupt-cells = <2>; |
| 92 | interrupt-controller; |
Geert Uytterhoeven | 4faf9c5 | 2014-04-23 10:25:28 +0200 | [diff] [blame] | 93 | clocks = <&mstp9_clks R8A7791_CLK_GPIO0>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 94 | power-domains = <&cpg_clocks>; |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 95 | }; |
| 96 | |
Magnus Damm | 89fbba1 | 2013-11-21 14:22:00 +0900 | [diff] [blame] | 97 | gpio1: gpio@e6051000 { |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 98 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
Magnus Damm | 89fbba1 | 2013-11-21 14:22:00 +0900 | [diff] [blame] | 99 | reg = <0 0xe6051000 0 0x50>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 100 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 101 | #gpio-cells = <2>; |
| 102 | gpio-controller; |
Sergei Shtylyov | 1329f6d | 2015-10-22 02:05:19 +0300 | [diff] [blame] | 103 | gpio-ranges = <&pfc 0 32 26>; |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 104 | #interrupt-cells = <2>; |
| 105 | interrupt-controller; |
Geert Uytterhoeven | 4faf9c5 | 2014-04-23 10:25:28 +0200 | [diff] [blame] | 106 | clocks = <&mstp9_clks R8A7791_CLK_GPIO1>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 107 | power-domains = <&cpg_clocks>; |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 108 | }; |
| 109 | |
Magnus Damm | 89fbba1 | 2013-11-21 14:22:00 +0900 | [diff] [blame] | 110 | gpio2: gpio@e6052000 { |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 111 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
Magnus Damm | 89fbba1 | 2013-11-21 14:22:00 +0900 | [diff] [blame] | 112 | reg = <0 0xe6052000 0 0x50>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 113 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 114 | #gpio-cells = <2>; |
| 115 | gpio-controller; |
| 116 | gpio-ranges = <&pfc 0 64 32>; |
| 117 | #interrupt-cells = <2>; |
| 118 | interrupt-controller; |
Geert Uytterhoeven | 4faf9c5 | 2014-04-23 10:25:28 +0200 | [diff] [blame] | 119 | clocks = <&mstp9_clks R8A7791_CLK_GPIO2>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 120 | power-domains = <&cpg_clocks>; |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 121 | }; |
| 122 | |
Magnus Damm | 89fbba1 | 2013-11-21 14:22:00 +0900 | [diff] [blame] | 123 | gpio3: gpio@e6053000 { |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 124 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
Magnus Damm | 89fbba1 | 2013-11-21 14:22:00 +0900 | [diff] [blame] | 125 | reg = <0 0xe6053000 0 0x50>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 126 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 127 | #gpio-cells = <2>; |
| 128 | gpio-controller; |
| 129 | gpio-ranges = <&pfc 0 96 32>; |
| 130 | #interrupt-cells = <2>; |
| 131 | interrupt-controller; |
Geert Uytterhoeven | 4faf9c5 | 2014-04-23 10:25:28 +0200 | [diff] [blame] | 132 | clocks = <&mstp9_clks R8A7791_CLK_GPIO3>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 133 | power-domains = <&cpg_clocks>; |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 134 | }; |
| 135 | |
Magnus Damm | 89fbba1 | 2013-11-21 14:22:00 +0900 | [diff] [blame] | 136 | gpio4: gpio@e6054000 { |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 137 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
Magnus Damm | 89fbba1 | 2013-11-21 14:22:00 +0900 | [diff] [blame] | 138 | reg = <0 0xe6054000 0 0x50>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 139 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 140 | #gpio-cells = <2>; |
| 141 | gpio-controller; |
| 142 | gpio-ranges = <&pfc 0 128 32>; |
| 143 | #interrupt-cells = <2>; |
| 144 | interrupt-controller; |
Geert Uytterhoeven | 4faf9c5 | 2014-04-23 10:25:28 +0200 | [diff] [blame] | 145 | clocks = <&mstp9_clks R8A7791_CLK_GPIO4>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 146 | power-domains = <&cpg_clocks>; |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 147 | }; |
| 148 | |
Magnus Damm | 89fbba1 | 2013-11-21 14:22:00 +0900 | [diff] [blame] | 149 | gpio5: gpio@e6055000 { |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 150 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
Magnus Damm | 89fbba1 | 2013-11-21 14:22:00 +0900 | [diff] [blame] | 151 | reg = <0 0xe6055000 0 0x50>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 152 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 153 | #gpio-cells = <2>; |
| 154 | gpio-controller; |
| 155 | gpio-ranges = <&pfc 0 160 32>; |
| 156 | #interrupt-cells = <2>; |
| 157 | interrupt-controller; |
Geert Uytterhoeven | 4faf9c5 | 2014-04-23 10:25:28 +0200 | [diff] [blame] | 158 | clocks = <&mstp9_clks R8A7791_CLK_GPIO5>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 159 | power-domains = <&cpg_clocks>; |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 160 | }; |
| 161 | |
Magnus Damm | 89fbba1 | 2013-11-21 14:22:00 +0900 | [diff] [blame] | 162 | gpio6: gpio@e6055400 { |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 163 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
Magnus Damm | 89fbba1 | 2013-11-21 14:22:00 +0900 | [diff] [blame] | 164 | reg = <0 0xe6055400 0 0x50>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 165 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 166 | #gpio-cells = <2>; |
| 167 | gpio-controller; |
| 168 | gpio-ranges = <&pfc 0 192 32>; |
| 169 | #interrupt-cells = <2>; |
| 170 | interrupt-controller; |
Geert Uytterhoeven | 4faf9c5 | 2014-04-23 10:25:28 +0200 | [diff] [blame] | 171 | clocks = <&mstp9_clks R8A7791_CLK_GPIO6>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 172 | power-domains = <&cpg_clocks>; |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 173 | }; |
| 174 | |
Magnus Damm | 89fbba1 | 2013-11-21 14:22:00 +0900 | [diff] [blame] | 175 | gpio7: gpio@e6055800 { |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 176 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
Magnus Damm | 89fbba1 | 2013-11-21 14:22:00 +0900 | [diff] [blame] | 177 | reg = <0 0xe6055800 0 0x50>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 178 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 179 | #gpio-cells = <2>; |
| 180 | gpio-controller; |
| 181 | gpio-ranges = <&pfc 0 224 26>; |
| 182 | #interrupt-cells = <2>; |
| 183 | interrupt-controller; |
Geert Uytterhoeven | 4faf9c5 | 2014-04-23 10:25:28 +0200 | [diff] [blame] | 184 | clocks = <&mstp9_clks R8A7791_CLK_GPIO7>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 185 | power-domains = <&cpg_clocks>; |
Magnus Damm | ab87e3f | 2013-10-08 12:39:30 +0900 | [diff] [blame] | 186 | }; |
| 187 | |
Magnus Damm | d103f4d | 2013-11-20 16:59:48 +0900 | [diff] [blame] | 188 | thermal@e61f0000 { |
| 189 | compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal"; |
| 190 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 191 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 563bc8e | 2014-01-07 19:57:13 +0100 | [diff] [blame] | 192 | clocks = <&mstp5_clks R8A7791_CLK_THERMAL>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 193 | power-domains = <&cpg_clocks>; |
Magnus Damm | d103f4d | 2013-11-20 16:59:48 +0900 | [diff] [blame] | 194 | }; |
| 195 | |
Magnus Damm | 03586ac | 2013-10-01 17:12:38 +0900 | [diff] [blame] | 196 | timer { |
| 197 | compatible = "arm,armv7-timer"; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 198 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 199 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 200 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 201 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; |
Magnus Damm | 03586ac | 2013-10-01 17:12:38 +0900 | [diff] [blame] | 202 | }; |
| 203 | |
Laurent Pinchart | ceaa189 | 2014-07-09 15:12:38 +0200 | [diff] [blame] | 204 | cmt0: timer@ffca0000 { |
Simon Horman | 4217f32 | 2014-09-08 09:27:46 +0900 | [diff] [blame] | 205 | compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2"; |
Laurent Pinchart | ceaa189 | 2014-07-09 15:12:38 +0200 | [diff] [blame] | 206 | reg = <0 0xffca0000 0 0x1004>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 207 | interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 208 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | ceaa189 | 2014-07-09 15:12:38 +0200 | [diff] [blame] | 209 | clocks = <&mstp1_clks R8A7791_CLK_CMT0>; |
| 210 | clock-names = "fck"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 211 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | ceaa189 | 2014-07-09 15:12:38 +0200 | [diff] [blame] | 212 | |
| 213 | renesas,channels-mask = <0x60>; |
| 214 | |
| 215 | status = "disabled"; |
| 216 | }; |
| 217 | |
| 218 | cmt1: timer@e6130000 { |
Simon Horman | 4217f32 | 2014-09-08 09:27:46 +0900 | [diff] [blame] | 219 | compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2"; |
Laurent Pinchart | ceaa189 | 2014-07-09 15:12:38 +0200 | [diff] [blame] | 220 | reg = <0 0xe6130000 0 0x1004>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 221 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, |
| 222 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
| 223 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, |
| 224 | <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, |
| 225 | <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, |
| 226 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, |
| 227 | <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, |
| 228 | <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | ceaa189 | 2014-07-09 15:12:38 +0200 | [diff] [blame] | 229 | clocks = <&mstp3_clks R8A7791_CLK_CMT1>; |
| 230 | clock-names = "fck"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 231 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | ceaa189 | 2014-07-09 15:12:38 +0200 | [diff] [blame] | 232 | |
| 233 | renesas,channels-mask = <0xff>; |
| 234 | |
| 235 | status = "disabled"; |
| 236 | }; |
| 237 | |
Magnus Damm | d77db73 | 2013-10-01 17:12:29 +0900 | [diff] [blame] | 238 | irqc0: interrupt-controller@e61c0000 { |
Magnus Damm | 26041b0 | 2013-11-20 13:18:05 +0900 | [diff] [blame] | 239 | compatible = "renesas,irqc-r8a7791", "renesas,irqc"; |
Magnus Damm | d77db73 | 2013-10-01 17:12:29 +0900 | [diff] [blame] | 240 | #interrupt-cells = <2>; |
| 241 | interrupt-controller; |
| 242 | reg = <0 0xe61c0000 0 0x200>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 243 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 244 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| 245 | <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, |
| 246 | <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, |
| 247 | <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
| 248 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| 249 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, |
| 250 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, |
| 251 | <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, |
| 252 | <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 62d386c | 2015-03-18 19:56:00 +0100 | [diff] [blame] | 253 | clocks = <&mstp4_clks R8A7791_CLK_IRQC>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 254 | power-domains = <&cpg_clocks>; |
Magnus Damm | d77db73 | 2013-10-01 17:12:29 +0900 | [diff] [blame] | 255 | }; |
Magnus Damm | 5514692 | 2013-10-08 12:39:01 +0900 | [diff] [blame] | 256 | |
Laurent Pinchart | fde8fee | 2014-07-19 01:50:25 +0200 | [diff] [blame] | 257 | dmac0: dma-controller@e6700000 { |
Simon Horman | e6d12b4 | 2015-11-13 11:23:49 +0900 | [diff] [blame] | 258 | compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; |
Laurent Pinchart | fde8fee | 2014-07-19 01:50:25 +0200 | [diff] [blame] | 259 | reg = <0 0xe6700000 0 0x20000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 260 | interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH |
| 261 | GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH |
| 262 | GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH |
| 263 | GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH |
| 264 | GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH |
| 265 | GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH |
| 266 | GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH |
| 267 | GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH |
| 268 | GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH |
| 269 | GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH |
| 270 | GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH |
| 271 | GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH |
| 272 | GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH |
| 273 | GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH |
| 274 | GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH |
| 275 | GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | fde8fee | 2014-07-19 01:50:25 +0200 | [diff] [blame] | 276 | interrupt-names = "error", |
| 277 | "ch0", "ch1", "ch2", "ch3", |
| 278 | "ch4", "ch5", "ch6", "ch7", |
| 279 | "ch8", "ch9", "ch10", "ch11", |
| 280 | "ch12", "ch13", "ch14"; |
| 281 | clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>; |
| 282 | clock-names = "fck"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 283 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | fde8fee | 2014-07-19 01:50:25 +0200 | [diff] [blame] | 284 | #dma-cells = <1>; |
| 285 | dma-channels = <15>; |
| 286 | }; |
| 287 | |
| 288 | dmac1: dma-controller@e6720000 { |
Simon Horman | e6d12b4 | 2015-11-13 11:23:49 +0900 | [diff] [blame] | 289 | compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; |
Laurent Pinchart | fde8fee | 2014-07-19 01:50:25 +0200 | [diff] [blame] | 290 | reg = <0 0xe6720000 0 0x20000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 291 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH |
| 292 | GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH |
| 293 | GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH |
| 294 | GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH |
| 295 | GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH |
| 296 | GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH |
| 297 | GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH |
| 298 | GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH |
| 299 | GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH |
| 300 | GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH |
| 301 | GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH |
| 302 | GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH |
| 303 | GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH |
| 304 | GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH |
| 305 | GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH |
| 306 | GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | fde8fee | 2014-07-19 01:50:25 +0200 | [diff] [blame] | 307 | interrupt-names = "error", |
| 308 | "ch0", "ch1", "ch2", "ch3", |
| 309 | "ch4", "ch5", "ch6", "ch7", |
| 310 | "ch8", "ch9", "ch10", "ch11", |
| 311 | "ch12", "ch13", "ch14"; |
| 312 | clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>; |
| 313 | clock-names = "fck"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 314 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | fde8fee | 2014-07-19 01:50:25 +0200 | [diff] [blame] | 315 | #dma-cells = <1>; |
| 316 | dma-channels = <15>; |
| 317 | }; |
| 318 | |
Kuninori Morimoto | 8994fff | 2014-11-03 17:45:37 -0800 | [diff] [blame] | 319 | audma0: dma-controller@ec700000 { |
Simon Horman | e6d12b4 | 2015-11-13 11:23:49 +0900 | [diff] [blame] | 320 | compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; |
Kuninori Morimoto | 8994fff | 2014-11-03 17:45:37 -0800 | [diff] [blame] | 321 | reg = <0 0xec700000 0 0x10000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 322 | interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH |
| 323 | GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH |
| 324 | GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH |
| 325 | GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH |
| 326 | GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH |
| 327 | GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH |
| 328 | GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH |
| 329 | GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH |
| 330 | GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH |
| 331 | GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH |
| 332 | GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH |
| 333 | GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH |
| 334 | GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH |
| 335 | GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 8994fff | 2014-11-03 17:45:37 -0800 | [diff] [blame] | 336 | interrupt-names = "error", |
| 337 | "ch0", "ch1", "ch2", "ch3", |
| 338 | "ch4", "ch5", "ch6", "ch7", |
| 339 | "ch8", "ch9", "ch10", "ch11", |
| 340 | "ch12"; |
| 341 | clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>; |
| 342 | clock-names = "fck"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 343 | power-domains = <&cpg_clocks>; |
Kuninori Morimoto | 8994fff | 2014-11-03 17:45:37 -0800 | [diff] [blame] | 344 | #dma-cells = <1>; |
| 345 | dma-channels = <13>; |
| 346 | }; |
| 347 | |
| 348 | audma1: dma-controller@ec720000 { |
Simon Horman | e6d12b4 | 2015-11-13 11:23:49 +0900 | [diff] [blame] | 349 | compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; |
Kuninori Morimoto | 8994fff | 2014-11-03 17:45:37 -0800 | [diff] [blame] | 350 | reg = <0 0xec720000 0 0x10000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 351 | interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH |
| 352 | GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH |
| 353 | GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH |
| 354 | GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH |
| 355 | GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH |
| 356 | GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH |
| 357 | GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH |
| 358 | GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH |
| 359 | GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH |
| 360 | GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH |
| 361 | GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH |
| 362 | GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH |
| 363 | GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH |
| 364 | GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 8994fff | 2014-11-03 17:45:37 -0800 | [diff] [blame] | 365 | interrupt-names = "error", |
| 366 | "ch0", "ch1", "ch2", "ch3", |
| 367 | "ch4", "ch5", "ch6", "ch7", |
| 368 | "ch8", "ch9", "ch10", "ch11", |
| 369 | "ch12"; |
| 370 | clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>; |
| 371 | clock-names = "fck"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 372 | power-domains = <&cpg_clocks>; |
Kuninori Morimoto | 8994fff | 2014-11-03 17:45:37 -0800 | [diff] [blame] | 373 | #dma-cells = <1>; |
| 374 | dma-channels = <13>; |
| 375 | }; |
| 376 | |
Yoshihiro Shimoda | e3e25ed | 2015-05-08 16:13:33 +0900 | [diff] [blame] | 377 | usb_dmac0: dma-controller@e65a0000 { |
Simon Horman | d01c8be | 2015-12-11 11:59:38 +0900 | [diff] [blame] | 378 | compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac"; |
Yoshihiro Shimoda | e3e25ed | 2015-05-08 16:13:33 +0900 | [diff] [blame] | 379 | reg = <0 0xe65a0000 0 0x100>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 380 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH |
| 381 | GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; |
Yoshihiro Shimoda | e3e25ed | 2015-05-08 16:13:33 +0900 | [diff] [blame] | 382 | interrupt-names = "ch0", "ch1"; |
| 383 | clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 384 | power-domains = <&cpg_clocks>; |
Yoshihiro Shimoda | e3e25ed | 2015-05-08 16:13:33 +0900 | [diff] [blame] | 385 | #dma-cells = <1>; |
| 386 | dma-channels = <2>; |
| 387 | }; |
| 388 | |
| 389 | usb_dmac1: dma-controller@e65b0000 { |
Simon Horman | d01c8be | 2015-12-11 11:59:38 +0900 | [diff] [blame] | 390 | compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac"; |
Yoshihiro Shimoda | e3e25ed | 2015-05-08 16:13:33 +0900 | [diff] [blame] | 391 | reg = <0 0xe65b0000 0 0x100>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 392 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH |
| 393 | GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
Yoshihiro Shimoda | e3e25ed | 2015-05-08 16:13:33 +0900 | [diff] [blame] | 394 | interrupt-names = "ch0", "ch1"; |
| 395 | clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 396 | power-domains = <&cpg_clocks>; |
Yoshihiro Shimoda | e3e25ed | 2015-05-08 16:13:33 +0900 | [diff] [blame] | 397 | #dma-cells = <1>; |
| 398 | dma-channels = <2>; |
| 399 | }; |
| 400 | |
Wolfram Sang | 36408d9 | 2014-03-10 12:26:58 +0100 | [diff] [blame] | 401 | /* The memory map in the User's Manual maps the cores to bus numbers */ |
Wolfram Sang | 5bd3de7 | 2014-02-17 11:44:41 +0100 | [diff] [blame] | 402 | i2c0: i2c@e6508000 { |
| 403 | #address-cells = <1>; |
| 404 | #size-cells = <0>; |
| 405 | compatible = "renesas,i2c-r8a7791"; |
| 406 | reg = <0 0xe6508000 0 0x40>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 407 | interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; |
Wolfram Sang | 5bd3de7 | 2014-02-17 11:44:41 +0100 | [diff] [blame] | 408 | clocks = <&mstp9_clks R8A7791_CLK_I2C0>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 409 | power-domains = <&cpg_clocks>; |
Wolfram Sang | 49160dc | 2015-12-08 10:37:51 +0100 | [diff] [blame] | 410 | i2c-scl-internal-delay-ns = <6>; |
Wolfram Sang | 5bd3de7 | 2014-02-17 11:44:41 +0100 | [diff] [blame] | 411 | status = "disabled"; |
| 412 | }; |
| 413 | |
| 414 | i2c1: i2c@e6518000 { |
| 415 | #address-cells = <1>; |
| 416 | #size-cells = <0>; |
| 417 | compatible = "renesas,i2c-r8a7791"; |
| 418 | reg = <0 0xe6518000 0 0x40>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 419 | interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; |
Wolfram Sang | 5bd3de7 | 2014-02-17 11:44:41 +0100 | [diff] [blame] | 420 | clocks = <&mstp9_clks R8A7791_CLK_I2C1>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 421 | power-domains = <&cpg_clocks>; |
Wolfram Sang | 49160dc | 2015-12-08 10:37:51 +0100 | [diff] [blame] | 422 | i2c-scl-internal-delay-ns = <6>; |
Wolfram Sang | 5bd3de7 | 2014-02-17 11:44:41 +0100 | [diff] [blame] | 423 | status = "disabled"; |
| 424 | }; |
| 425 | |
| 426 | i2c2: i2c@e6530000 { |
| 427 | #address-cells = <1>; |
| 428 | #size-cells = <0>; |
| 429 | compatible = "renesas,i2c-r8a7791"; |
| 430 | reg = <0 0xe6530000 0 0x40>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 431 | interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; |
Wolfram Sang | 5bd3de7 | 2014-02-17 11:44:41 +0100 | [diff] [blame] | 432 | clocks = <&mstp9_clks R8A7791_CLK_I2C2>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 433 | power-domains = <&cpg_clocks>; |
Wolfram Sang | 49160dc | 2015-12-08 10:37:51 +0100 | [diff] [blame] | 434 | i2c-scl-internal-delay-ns = <6>; |
Wolfram Sang | 5bd3de7 | 2014-02-17 11:44:41 +0100 | [diff] [blame] | 435 | status = "disabled"; |
| 436 | }; |
| 437 | |
| 438 | i2c3: i2c@e6540000 { |
| 439 | #address-cells = <1>; |
| 440 | #size-cells = <0>; |
| 441 | compatible = "renesas,i2c-r8a7791"; |
| 442 | reg = <0 0xe6540000 0 0x40>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 443 | interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; |
Wolfram Sang | 5bd3de7 | 2014-02-17 11:44:41 +0100 | [diff] [blame] | 444 | clocks = <&mstp9_clks R8A7791_CLK_I2C3>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 445 | power-domains = <&cpg_clocks>; |
Wolfram Sang | 49160dc | 2015-12-08 10:37:51 +0100 | [diff] [blame] | 446 | i2c-scl-internal-delay-ns = <6>; |
Wolfram Sang | 5bd3de7 | 2014-02-17 11:44:41 +0100 | [diff] [blame] | 447 | status = "disabled"; |
| 448 | }; |
| 449 | |
| 450 | i2c4: i2c@e6520000 { |
| 451 | #address-cells = <1>; |
| 452 | #size-cells = <0>; |
| 453 | compatible = "renesas,i2c-r8a7791"; |
| 454 | reg = <0 0xe6520000 0 0x40>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 455 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
Wolfram Sang | 5bd3de7 | 2014-02-17 11:44:41 +0100 | [diff] [blame] | 456 | clocks = <&mstp9_clks R8A7791_CLK_I2C4>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 457 | power-domains = <&cpg_clocks>; |
Wolfram Sang | 49160dc | 2015-12-08 10:37:51 +0100 | [diff] [blame] | 458 | i2c-scl-internal-delay-ns = <6>; |
Wolfram Sang | 5bd3de7 | 2014-02-17 11:44:41 +0100 | [diff] [blame] | 459 | status = "disabled"; |
| 460 | }; |
| 461 | |
| 462 | i2c5: i2c@e6528000 { |
Wolfram Sang | 36408d9 | 2014-03-10 12:26:58 +0100 | [diff] [blame] | 463 | /* doesn't need pinmux */ |
Wolfram Sang | 5bd3de7 | 2014-02-17 11:44:41 +0100 | [diff] [blame] | 464 | #address-cells = <1>; |
| 465 | #size-cells = <0>; |
| 466 | compatible = "renesas,i2c-r8a7791"; |
| 467 | reg = <0 0xe6528000 0 0x40>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 468 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
Wolfram Sang | 5bd3de7 | 2014-02-17 11:44:41 +0100 | [diff] [blame] | 469 | clocks = <&mstp9_clks R8A7791_CLK_I2C5>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 470 | power-domains = <&cpg_clocks>; |
Wolfram Sang | 49160dc | 2015-12-08 10:37:51 +0100 | [diff] [blame] | 471 | i2c-scl-internal-delay-ns = <110>; |
Wolfram Sang | 5bd3de7 | 2014-02-17 11:44:41 +0100 | [diff] [blame] | 472 | status = "disabled"; |
| 473 | }; |
| 474 | |
Wolfram Sang | 36408d9 | 2014-03-10 12:26:58 +0100 | [diff] [blame] | 475 | i2c6: i2c@e60b0000 { |
| 476 | /* doesn't need pinmux */ |
| 477 | #address-cells = <1>; |
| 478 | #size-cells = <0>; |
| 479 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; |
| 480 | reg = <0 0xe60b0000 0 0x425>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 481 | interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; |
Wolfram Sang | 36408d9 | 2014-03-10 12:26:58 +0100 | [diff] [blame] | 482 | clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; |
Wolfram Sang | 3f58c54 | 2014-11-07 11:11:44 +0100 | [diff] [blame] | 483 | dmas = <&dmac0 0x77>, <&dmac0 0x78>; |
| 484 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 485 | power-domains = <&cpg_clocks>; |
Wolfram Sang | 36408d9 | 2014-03-10 12:26:58 +0100 | [diff] [blame] | 486 | status = "disabled"; |
| 487 | }; |
| 488 | |
| 489 | i2c7: i2c@e6500000 { |
| 490 | #address-cells = <1>; |
| 491 | #size-cells = <0>; |
| 492 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; |
| 493 | reg = <0 0xe6500000 0 0x425>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 494 | interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; |
Wolfram Sang | 36408d9 | 2014-03-10 12:26:58 +0100 | [diff] [blame] | 495 | clocks = <&mstp3_clks R8A7791_CLK_IIC0>; |
Wolfram Sang | 3f58c54 | 2014-11-07 11:11:44 +0100 | [diff] [blame] | 496 | dmas = <&dmac0 0x61>, <&dmac0 0x62>; |
| 497 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 498 | power-domains = <&cpg_clocks>; |
Wolfram Sang | 36408d9 | 2014-03-10 12:26:58 +0100 | [diff] [blame] | 499 | status = "disabled"; |
| 500 | }; |
| 501 | |
| 502 | i2c8: i2c@e6510000 { |
| 503 | #address-cells = <1>; |
| 504 | #size-cells = <0>; |
| 505 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; |
| 506 | reg = <0 0xe6510000 0 0x425>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 507 | interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; |
Wolfram Sang | 36408d9 | 2014-03-10 12:26:58 +0100 | [diff] [blame] | 508 | clocks = <&mstp3_clks R8A7791_CLK_IIC1>; |
Wolfram Sang | 3f58c54 | 2014-11-07 11:11:44 +0100 | [diff] [blame] | 509 | dmas = <&dmac0 0x65>, <&dmac0 0x66>; |
| 510 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 511 | power-domains = <&cpg_clocks>; |
Wolfram Sang | 36408d9 | 2014-03-10 12:26:58 +0100 | [diff] [blame] | 512 | status = "disabled"; |
| 513 | }; |
| 514 | |
Magnus Damm | 5514692 | 2013-10-08 12:39:01 +0900 | [diff] [blame] | 515 | pfc: pfc@e6060000 { |
| 516 | compatible = "renesas,pfc-r8a7791"; |
| 517 | reg = <0 0xe6060000 0 0x250>; |
Magnus Damm | 5514692 | 2013-10-08 12:39:01 +0900 | [diff] [blame] | 518 | }; |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 519 | |
Laurent Pinchart | 8edae49 | 2014-10-26 19:40:12 +0200 | [diff] [blame] | 520 | mmcif0: mmc@ee200000 { |
| 521 | compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif"; |
| 522 | reg = <0 0xee200000 0 0x80>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 523 | interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 8edae49 | 2014-10-26 19:40:12 +0200 | [diff] [blame] | 524 | clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>; |
Laurent Pinchart | 16b355b | 2014-10-26 19:40:14 +0200 | [diff] [blame] | 525 | dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; |
| 526 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 527 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 8edae49 | 2014-10-26 19:40:12 +0200 | [diff] [blame] | 528 | reg-io-width = <4>; |
| 529 | status = "disabled"; |
Kuninori Morimoto | d957ab8 | 2015-05-14 07:23:20 +0000 | [diff] [blame] | 530 | max-frequency = <97500000>; |
Laurent Pinchart | 8edae49 | 2014-10-26 19:40:12 +0200 | [diff] [blame] | 531 | }; |
| 532 | |
Magnus Damm | b7ed8a0 | 2014-02-12 18:53:55 +0900 | [diff] [blame] | 533 | sdhi0: sd@ee100000 { |
| 534 | compatible = "renesas,sdhi-r8a7791"; |
Kuninori Morimoto | e849b06 | 2015-02-24 02:20:52 +0000 | [diff] [blame] | 535 | reg = <0 0xee100000 0 0x328>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 536 | interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; |
Magnus Damm | b7ed8a0 | 2014-02-12 18:53:55 +0900 | [diff] [blame] | 537 | clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; |
Laurent Pinchart | ae67fa2 | 2015-02-24 02:20:19 +0000 | [diff] [blame] | 538 | dmas = <&dmac1 0xcd>, <&dmac1 0xce>; |
| 539 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 540 | power-domains = <&cpg_clocks>; |
Magnus Damm | b7ed8a0 | 2014-02-12 18:53:55 +0900 | [diff] [blame] | 541 | status = "disabled"; |
| 542 | }; |
| 543 | |
| 544 | sdhi1: sd@ee140000 { |
| 545 | compatible = "renesas,sdhi-r8a7791"; |
| 546 | reg = <0 0xee140000 0 0x100>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 547 | interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; |
Magnus Damm | b7ed8a0 | 2014-02-12 18:53:55 +0900 | [diff] [blame] | 548 | clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; |
Laurent Pinchart | ae67fa2 | 2015-02-24 02:20:19 +0000 | [diff] [blame] | 549 | dmas = <&dmac1 0xc1>, <&dmac1 0xc2>; |
| 550 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 551 | power-domains = <&cpg_clocks>; |
Magnus Damm | b7ed8a0 | 2014-02-12 18:53:55 +0900 | [diff] [blame] | 552 | status = "disabled"; |
| 553 | }; |
| 554 | |
| 555 | sdhi2: sd@ee160000 { |
| 556 | compatible = "renesas,sdhi-r8a7791"; |
| 557 | reg = <0 0xee160000 0 0x100>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 558 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; |
Magnus Damm | b7ed8a0 | 2014-02-12 18:53:55 +0900 | [diff] [blame] | 559 | clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; |
Laurent Pinchart | ae67fa2 | 2015-02-24 02:20:19 +0000 | [diff] [blame] | 560 | dmas = <&dmac1 0xd3>, <&dmac1 0xd4>; |
| 561 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 562 | power-domains = <&cpg_clocks>; |
Magnus Damm | b7ed8a0 | 2014-02-12 18:53:55 +0900 | [diff] [blame] | 563 | status = "disabled"; |
| 564 | }; |
| 565 | |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 566 | scifa0: serial@e6c40000 { |
Geert Uytterhoeven | b5b52dd | 2016-01-29 10:32:05 +0100 | [diff] [blame] | 567 | compatible = "renesas,scifa-r8a7791", |
| 568 | "renesas,rcar-gen2-scifa", "renesas,scifa"; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 569 | reg = <0 0xe6c40000 0 64>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 570 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 571 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>; |
Laurent Pinchart | bb7ca19 | 2016-01-29 10:47:38 +0100 | [diff] [blame^] | 572 | clock-names = "fck"; |
Geert Uytterhoeven | 558d656 | 2015-05-20 19:46:26 +0200 | [diff] [blame] | 573 | dmas = <&dmac0 0x21>, <&dmac0 0x22>; |
| 574 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 575 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 576 | status = "disabled"; |
| 577 | }; |
| 578 | |
| 579 | scifa1: serial@e6c50000 { |
Geert Uytterhoeven | b5b52dd | 2016-01-29 10:32:05 +0100 | [diff] [blame] | 580 | compatible = "renesas,scifa-r8a7791", |
| 581 | "renesas,rcar-gen2-scifa", "renesas,scifa"; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 582 | reg = <0 0xe6c50000 0 64>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 583 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 584 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>; |
Laurent Pinchart | bb7ca19 | 2016-01-29 10:47:38 +0100 | [diff] [blame^] | 585 | clock-names = "fck"; |
Geert Uytterhoeven | 558d656 | 2015-05-20 19:46:26 +0200 | [diff] [blame] | 586 | dmas = <&dmac0 0x25>, <&dmac0 0x26>; |
| 587 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 588 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 589 | status = "disabled"; |
| 590 | }; |
| 591 | |
| 592 | scifa2: serial@e6c60000 { |
Geert Uytterhoeven | b5b52dd | 2016-01-29 10:32:05 +0100 | [diff] [blame] | 593 | compatible = "renesas,scifa-r8a7791", |
| 594 | "renesas,rcar-gen2-scifa", "renesas,scifa"; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 595 | reg = <0 0xe6c60000 0 64>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 596 | interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 597 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>; |
Laurent Pinchart | bb7ca19 | 2016-01-29 10:47:38 +0100 | [diff] [blame^] | 598 | clock-names = "fck"; |
Geert Uytterhoeven | 558d656 | 2015-05-20 19:46:26 +0200 | [diff] [blame] | 599 | dmas = <&dmac0 0x27>, <&dmac0 0x28>; |
| 600 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 601 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 602 | status = "disabled"; |
| 603 | }; |
| 604 | |
| 605 | scifa3: serial@e6c70000 { |
Geert Uytterhoeven | b5b52dd | 2016-01-29 10:32:05 +0100 | [diff] [blame] | 606 | compatible = "renesas,scifa-r8a7791", |
| 607 | "renesas,rcar-gen2-scifa", "renesas,scifa"; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 608 | reg = <0 0xe6c70000 0 64>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 609 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 610 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>; |
Laurent Pinchart | bb7ca19 | 2016-01-29 10:47:38 +0100 | [diff] [blame^] | 611 | clock-names = "fck"; |
Geert Uytterhoeven | 558d656 | 2015-05-20 19:46:26 +0200 | [diff] [blame] | 612 | dmas = <&dmac0 0x1b>, <&dmac0 0x1c>; |
| 613 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 614 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 615 | status = "disabled"; |
| 616 | }; |
| 617 | |
| 618 | scifa4: serial@e6c78000 { |
Geert Uytterhoeven | b5b52dd | 2016-01-29 10:32:05 +0100 | [diff] [blame] | 619 | compatible = "renesas,scifa-r8a7791", |
| 620 | "renesas,rcar-gen2-scifa", "renesas,scifa"; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 621 | reg = <0 0xe6c78000 0 64>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 622 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 623 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>; |
Laurent Pinchart | bb7ca19 | 2016-01-29 10:47:38 +0100 | [diff] [blame^] | 624 | clock-names = "fck"; |
Geert Uytterhoeven | 558d656 | 2015-05-20 19:46:26 +0200 | [diff] [blame] | 625 | dmas = <&dmac0 0x1f>, <&dmac0 0x20>; |
| 626 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 627 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 628 | status = "disabled"; |
| 629 | }; |
| 630 | |
| 631 | scifa5: serial@e6c80000 { |
Geert Uytterhoeven | b5b52dd | 2016-01-29 10:32:05 +0100 | [diff] [blame] | 632 | compatible = "renesas,scifa-r8a7791", |
| 633 | "renesas,rcar-gen2-scifa", "renesas,scifa"; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 634 | reg = <0 0xe6c80000 0 64>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 635 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 636 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>; |
Laurent Pinchart | bb7ca19 | 2016-01-29 10:47:38 +0100 | [diff] [blame^] | 637 | clock-names = "fck"; |
Geert Uytterhoeven | 558d656 | 2015-05-20 19:46:26 +0200 | [diff] [blame] | 638 | dmas = <&dmac0 0x23>, <&dmac0 0x24>; |
| 639 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 640 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 641 | status = "disabled"; |
| 642 | }; |
| 643 | |
| 644 | scifb0: serial@e6c20000 { |
Geert Uytterhoeven | b5b52dd | 2016-01-29 10:32:05 +0100 | [diff] [blame] | 645 | compatible = "renesas,scifb-r8a7791", |
| 646 | "renesas,rcar-gen2-scifb", "renesas,scifb"; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 647 | reg = <0 0xe6c20000 0 64>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 648 | interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 649 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>; |
Laurent Pinchart | bb7ca19 | 2016-01-29 10:47:38 +0100 | [diff] [blame^] | 650 | clock-names = "fck"; |
Geert Uytterhoeven | 558d656 | 2015-05-20 19:46:26 +0200 | [diff] [blame] | 651 | dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; |
| 652 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 653 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 654 | status = "disabled"; |
| 655 | }; |
| 656 | |
| 657 | scifb1: serial@e6c30000 { |
Geert Uytterhoeven | b5b52dd | 2016-01-29 10:32:05 +0100 | [diff] [blame] | 658 | compatible = "renesas,scifb-r8a7791", |
| 659 | "renesas,rcar-gen2-scifb", "renesas,scifb"; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 660 | reg = <0 0xe6c30000 0 64>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 661 | interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 662 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>; |
Laurent Pinchart | bb7ca19 | 2016-01-29 10:47:38 +0100 | [diff] [blame^] | 663 | clock-names = "fck"; |
Geert Uytterhoeven | 558d656 | 2015-05-20 19:46:26 +0200 | [diff] [blame] | 664 | dmas = <&dmac0 0x19>, <&dmac0 0x1a>; |
| 665 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 666 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 667 | status = "disabled"; |
| 668 | }; |
| 669 | |
| 670 | scifb2: serial@e6ce0000 { |
Geert Uytterhoeven | b5b52dd | 2016-01-29 10:32:05 +0100 | [diff] [blame] | 671 | compatible = "renesas,scifb-r8a7791", |
| 672 | "renesas,rcar-gen2-scifb", "renesas,scifb"; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 673 | reg = <0 0xe6ce0000 0 64>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 674 | interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 675 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>; |
Laurent Pinchart | bb7ca19 | 2016-01-29 10:47:38 +0100 | [diff] [blame^] | 676 | clock-names = "fck"; |
Geert Uytterhoeven | 558d656 | 2015-05-20 19:46:26 +0200 | [diff] [blame] | 677 | dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; |
| 678 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 679 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 680 | status = "disabled"; |
| 681 | }; |
| 682 | |
| 683 | scif0: serial@e6e60000 { |
Geert Uytterhoeven | b5b52dd | 2016-01-29 10:32:05 +0100 | [diff] [blame] | 684 | compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", |
| 685 | "renesas,scif"; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 686 | reg = <0 0xe6e60000 0 64>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 687 | interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 688 | clocks = <&mstp7_clks R8A7791_CLK_SCIF0>; |
Laurent Pinchart | bb7ca19 | 2016-01-29 10:47:38 +0100 | [diff] [blame^] | 689 | clock-names = "fck"; |
Geert Uytterhoeven | 558d656 | 2015-05-20 19:46:26 +0200 | [diff] [blame] | 690 | dmas = <&dmac0 0x29>, <&dmac0 0x2a>; |
| 691 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 692 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 693 | status = "disabled"; |
| 694 | }; |
| 695 | |
| 696 | scif1: serial@e6e68000 { |
Geert Uytterhoeven | b5b52dd | 2016-01-29 10:32:05 +0100 | [diff] [blame] | 697 | compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", |
| 698 | "renesas,scif"; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 699 | reg = <0 0xe6e68000 0 64>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 700 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 701 | clocks = <&mstp7_clks R8A7791_CLK_SCIF1>; |
Laurent Pinchart | bb7ca19 | 2016-01-29 10:47:38 +0100 | [diff] [blame^] | 702 | clock-names = "fck"; |
Geert Uytterhoeven | 558d656 | 2015-05-20 19:46:26 +0200 | [diff] [blame] | 703 | dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; |
| 704 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 705 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 706 | status = "disabled"; |
| 707 | }; |
| 708 | |
| 709 | scif2: serial@e6e58000 { |
Geert Uytterhoeven | b5b52dd | 2016-01-29 10:32:05 +0100 | [diff] [blame] | 710 | compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", |
| 711 | "renesas,scif"; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 712 | reg = <0 0xe6e58000 0 64>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 713 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 714 | clocks = <&mstp7_clks R8A7791_CLK_SCIF2>; |
Laurent Pinchart | bb7ca19 | 2016-01-29 10:47:38 +0100 | [diff] [blame^] | 715 | clock-names = "fck"; |
Geert Uytterhoeven | 558d656 | 2015-05-20 19:46:26 +0200 | [diff] [blame] | 716 | dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; |
| 717 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 718 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 719 | status = "disabled"; |
| 720 | }; |
| 721 | |
| 722 | scif3: serial@e6ea8000 { |
Geert Uytterhoeven | b5b52dd | 2016-01-29 10:32:05 +0100 | [diff] [blame] | 723 | compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", |
| 724 | "renesas,scif"; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 725 | reg = <0 0xe6ea8000 0 64>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 726 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 727 | clocks = <&mstp7_clks R8A7791_CLK_SCIF3>; |
Laurent Pinchart | bb7ca19 | 2016-01-29 10:47:38 +0100 | [diff] [blame^] | 728 | clock-names = "fck"; |
Geert Uytterhoeven | 558d656 | 2015-05-20 19:46:26 +0200 | [diff] [blame] | 729 | dmas = <&dmac0 0x2f>, <&dmac0 0x30>; |
| 730 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 731 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 732 | status = "disabled"; |
| 733 | }; |
| 734 | |
| 735 | scif4: serial@e6ee0000 { |
Geert Uytterhoeven | b5b52dd | 2016-01-29 10:32:05 +0100 | [diff] [blame] | 736 | compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", |
| 737 | "renesas,scif"; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 738 | reg = <0 0xe6ee0000 0 64>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 739 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 740 | clocks = <&mstp7_clks R8A7791_CLK_SCIF4>; |
Laurent Pinchart | bb7ca19 | 2016-01-29 10:47:38 +0100 | [diff] [blame^] | 741 | clock-names = "fck"; |
Geert Uytterhoeven | 558d656 | 2015-05-20 19:46:26 +0200 | [diff] [blame] | 742 | dmas = <&dmac0 0xfb>, <&dmac0 0xfc>; |
| 743 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 744 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 745 | status = "disabled"; |
| 746 | }; |
| 747 | |
| 748 | scif5: serial@e6ee8000 { |
Geert Uytterhoeven | b5b52dd | 2016-01-29 10:32:05 +0100 | [diff] [blame] | 749 | compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", |
| 750 | "renesas,scif"; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 751 | reg = <0 0xe6ee8000 0 64>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 752 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 753 | clocks = <&mstp7_clks R8A7791_CLK_SCIF5>; |
Laurent Pinchart | bb7ca19 | 2016-01-29 10:47:38 +0100 | [diff] [blame^] | 754 | clock-names = "fck"; |
Geert Uytterhoeven | 558d656 | 2015-05-20 19:46:26 +0200 | [diff] [blame] | 755 | dmas = <&dmac0 0xfd>, <&dmac0 0xfe>; |
| 756 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 757 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 758 | status = "disabled"; |
| 759 | }; |
| 760 | |
| 761 | hscif0: serial@e62c0000 { |
Geert Uytterhoeven | b5b52dd | 2016-01-29 10:32:05 +0100 | [diff] [blame] | 762 | compatible = "renesas,hscif-r8a7791", |
| 763 | "renesas,rcar-gen2-hscif", "renesas,hscif"; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 764 | reg = <0 0xe62c0000 0 96>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 765 | interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 766 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>; |
Laurent Pinchart | bb7ca19 | 2016-01-29 10:47:38 +0100 | [diff] [blame^] | 767 | clock-names = "fck"; |
Geert Uytterhoeven | 558d656 | 2015-05-20 19:46:26 +0200 | [diff] [blame] | 768 | dmas = <&dmac0 0x39>, <&dmac0 0x3a>; |
| 769 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 770 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 771 | status = "disabled"; |
| 772 | }; |
| 773 | |
| 774 | hscif1: serial@e62c8000 { |
Geert Uytterhoeven | b5b52dd | 2016-01-29 10:32:05 +0100 | [diff] [blame] | 775 | compatible = "renesas,hscif-r8a7791", |
| 776 | "renesas,rcar-gen2-hscif", "renesas,hscif"; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 777 | reg = <0 0xe62c8000 0 96>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 778 | interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 779 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>; |
Laurent Pinchart | bb7ca19 | 2016-01-29 10:47:38 +0100 | [diff] [blame^] | 780 | clock-names = "fck"; |
Geert Uytterhoeven | 558d656 | 2015-05-20 19:46:26 +0200 | [diff] [blame] | 781 | dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; |
| 782 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 783 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 784 | status = "disabled"; |
| 785 | }; |
| 786 | |
| 787 | hscif2: serial@e62d0000 { |
Geert Uytterhoeven | b5b52dd | 2016-01-29 10:32:05 +0100 | [diff] [blame] | 788 | compatible = "renesas,hscif-r8a7791", |
| 789 | "renesas,rcar-gen2-hscif", "renesas,hscif"; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 790 | reg = <0 0xe62d0000 0 96>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 791 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 792 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>; |
Laurent Pinchart | bb7ca19 | 2016-01-29 10:47:38 +0100 | [diff] [blame^] | 793 | clock-names = "fck"; |
Geert Uytterhoeven | 558d656 | 2015-05-20 19:46:26 +0200 | [diff] [blame] | 794 | dmas = <&dmac0 0x3b>, <&dmac0 0x3c>; |
| 795 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 796 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 9640cf2 | 2013-12-11 14:14:22 +0100 | [diff] [blame] | 797 | status = "disabled"; |
| 798 | }; |
| 799 | |
Sergei Shtylyov | 2e5d55c | 2014-02-20 02:27:04 +0300 | [diff] [blame] | 800 | ether: ethernet@ee700000 { |
| 801 | compatible = "renesas,ether-r8a7791"; |
| 802 | reg = <0 0xee700000 0 0x400>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 803 | interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | 2e5d55c | 2014-02-20 02:27:04 +0300 | [diff] [blame] | 804 | clocks = <&mstp8_clks R8A7791_CLK_ETHER>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 805 | power-domains = <&cpg_clocks>; |
Sergei Shtylyov | 2e5d55c | 2014-02-20 02:27:04 +0300 | [diff] [blame] | 806 | phy-mode = "rmii"; |
| 807 | #address-cells = <1>; |
| 808 | #size-cells = <0>; |
| 809 | status = "disabled"; |
| 810 | }; |
| 811 | |
Sergei Shtylyov | 46ece34 | 2015-12-03 01:23:03 +0300 | [diff] [blame] | 812 | avb: ethernet@e6800000 { |
| 813 | compatible = "renesas,etheravb-r8a7791", |
| 814 | "renesas,etheravb-rcar-gen2"; |
| 815 | reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 816 | interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | 46ece34 | 2015-12-03 01:23:03 +0300 | [diff] [blame] | 817 | clocks = <&mstp8_clks R8A7791_CLK_ETHERAVB>; |
| 818 | power-domains = <&cpg_clocks>; |
| 819 | #address-cells = <1>; |
| 820 | #size-cells = <0>; |
| 821 | status = "disabled"; |
| 822 | }; |
| 823 | |
Valentine Barshak | b8532c6 | 2014-01-14 21:05:40 +0400 | [diff] [blame] | 824 | sata0: sata@ee300000 { |
| 825 | compatible = "renesas,sata-r8a7791"; |
| 826 | reg = <0 0xee300000 0 0x2000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 827 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
Valentine Barshak | b8532c6 | 2014-01-14 21:05:40 +0400 | [diff] [blame] | 828 | clocks = <&mstp8_clks R8A7791_CLK_SATA0>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 829 | power-domains = <&cpg_clocks>; |
Valentine Barshak | b8532c6 | 2014-01-14 21:05:40 +0400 | [diff] [blame] | 830 | status = "disabled"; |
| 831 | }; |
| 832 | |
| 833 | sata1: sata@ee500000 { |
| 834 | compatible = "renesas,sata-r8a7791"; |
| 835 | reg = <0 0xee500000 0 0x2000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 836 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
Valentine Barshak | b8532c6 | 2014-01-14 21:05:40 +0400 | [diff] [blame] | 837 | clocks = <&mstp8_clks R8A7791_CLK_SATA1>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 838 | power-domains = <&cpg_clocks>; |
Valentine Barshak | b8532c6 | 2014-01-14 21:05:40 +0400 | [diff] [blame] | 839 | status = "disabled"; |
| 840 | }; |
| 841 | |
Yoshihiro Shimoda | 1c1fee7 | 2014-10-24 19:45:06 +0900 | [diff] [blame] | 842 | hsusb: usb@e6590000 { |
Simon Horman | 8cf1d45 | 2016-01-04 08:20:18 +1100 | [diff] [blame] | 843 | compatible = "renesas,usbhs-r8a7791", "renesas,rcar-gen2-usbhs"; |
Yoshihiro Shimoda | 1c1fee7 | 2014-10-24 19:45:06 +0900 | [diff] [blame] | 844 | reg = <0 0xe6590000 0 0x100>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 845 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
Yoshihiro Shimoda | 1c1fee7 | 2014-10-24 19:45:06 +0900 | [diff] [blame] | 846 | clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; |
Yoshihiro Shimoda | 7706993 | 2015-05-08 16:13:34 +0900 | [diff] [blame] | 847 | dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, |
| 848 | <&usb_dmac1 0>, <&usb_dmac1 1>; |
| 849 | dma-names = "ch0", "ch1", "ch2", "ch3"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 850 | power-domains = <&cpg_clocks>; |
| 851 | renesas,buswait = <4>; |
| 852 | phys = <&usb0 1>; |
| 853 | phy-names = "usb"; |
Yoshihiro Shimoda | 1c1fee7 | 2014-10-24 19:45:06 +0900 | [diff] [blame] | 854 | status = "disabled"; |
| 855 | }; |
| 856 | |
Sergei Shtylyov | 3b7e530 | 2014-09-27 01:08:12 +0400 | [diff] [blame] | 857 | usbphy: usb-phy@e6590100 { |
| 858 | compatible = "renesas,usb-phy-r8a7791"; |
| 859 | reg = <0 0xe6590100 0 0x100>; |
| 860 | #address-cells = <1>; |
| 861 | #size-cells = <0>; |
| 862 | clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; |
| 863 | clock-names = "usbhs"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 864 | power-domains = <&cpg_clocks>; |
Sergei Shtylyov | 3b7e530 | 2014-09-27 01:08:12 +0400 | [diff] [blame] | 865 | status = "disabled"; |
| 866 | |
| 867 | usb0: usb-channel@0 { |
| 868 | reg = <0>; |
| 869 | #phy-cells = <1>; |
| 870 | }; |
| 871 | usb2: usb-channel@2 { |
| 872 | reg = <2>; |
| 873 | #phy-cells = <1>; |
| 874 | }; |
| 875 | }; |
| 876 | |
Sergei Shtylyov | 0b8d1d5 | 2014-08-02 04:04:21 +0400 | [diff] [blame] | 877 | vin0: video@e6ef0000 { |
| 878 | compatible = "renesas,vin-r8a7791"; |
Sergei Shtylyov | 0b8d1d5 | 2014-08-02 04:04:21 +0400 | [diff] [blame] | 879 | reg = <0 0xe6ef0000 0 0x1000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 880 | interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 881 | clocks = <&mstp8_clks R8A7791_CLK_VIN0>; |
| 882 | power-domains = <&cpg_clocks>; |
Sergei Shtylyov | 0b8d1d5 | 2014-08-02 04:04:21 +0400 | [diff] [blame] | 883 | status = "disabled"; |
| 884 | }; |
| 885 | |
| 886 | vin1: video@e6ef1000 { |
| 887 | compatible = "renesas,vin-r8a7791"; |
Sergei Shtylyov | 0b8d1d5 | 2014-08-02 04:04:21 +0400 | [diff] [blame] | 888 | reg = <0 0xe6ef1000 0 0x1000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 889 | interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 890 | clocks = <&mstp8_clks R8A7791_CLK_VIN1>; |
| 891 | power-domains = <&cpg_clocks>; |
Sergei Shtylyov | 0b8d1d5 | 2014-08-02 04:04:21 +0400 | [diff] [blame] | 892 | status = "disabled"; |
| 893 | }; |
| 894 | |
| 895 | vin2: video@e6ef2000 { |
| 896 | compatible = "renesas,vin-r8a7791"; |
Sergei Shtylyov | 0b8d1d5 | 2014-08-02 04:04:21 +0400 | [diff] [blame] | 897 | reg = <0 0xe6ef2000 0 0x1000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 898 | interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 899 | clocks = <&mstp8_clks R8A7791_CLK_VIN2>; |
| 900 | power-domains = <&cpg_clocks>; |
Sergei Shtylyov | 0b8d1d5 | 2014-08-02 04:04:21 +0400 | [diff] [blame] | 901 | status = "disabled"; |
| 902 | }; |
| 903 | |
Laurent Pinchart | 8eefac2 | 2014-01-21 16:00:46 +0100 | [diff] [blame] | 904 | vsp1@fe928000 { |
| 905 | compatible = "renesas,vsp1"; |
| 906 | reg = <0 0xfe928000 0 0x8000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 907 | interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 8eefac2 | 2014-01-21 16:00:46 +0100 | [diff] [blame] | 908 | clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 909 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 8eefac2 | 2014-01-21 16:00:46 +0100 | [diff] [blame] | 910 | |
| 911 | renesas,has-lut; |
| 912 | renesas,has-sru; |
| 913 | renesas,#rpf = <5>; |
| 914 | renesas,#uds = <3>; |
| 915 | renesas,#wpf = <4>; |
| 916 | }; |
| 917 | |
| 918 | vsp1@fe930000 { |
| 919 | compatible = "renesas,vsp1"; |
| 920 | reg = <0 0xfe930000 0 0x8000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 921 | interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 8eefac2 | 2014-01-21 16:00:46 +0100 | [diff] [blame] | 922 | clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 923 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 8eefac2 | 2014-01-21 16:00:46 +0100 | [diff] [blame] | 924 | |
| 925 | renesas,has-lif; |
| 926 | renesas,has-lut; |
| 927 | renesas,#rpf = <4>; |
| 928 | renesas,#uds = <1>; |
| 929 | renesas,#wpf = <4>; |
| 930 | }; |
| 931 | |
| 932 | vsp1@fe938000 { |
| 933 | compatible = "renesas,vsp1"; |
| 934 | reg = <0 0xfe938000 0 0x8000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 935 | interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 8eefac2 | 2014-01-21 16:00:46 +0100 | [diff] [blame] | 936 | clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 937 | power-domains = <&cpg_clocks>; |
Laurent Pinchart | 8eefac2 | 2014-01-21 16:00:46 +0100 | [diff] [blame] | 938 | |
| 939 | renesas,has-lif; |
| 940 | renesas,has-lut; |
| 941 | renesas,#rpf = <4>; |
| 942 | renesas,#uds = <1>; |
| 943 | renesas,#wpf = <4>; |
| 944 | }; |
| 945 | |
| 946 | du: display@feb00000 { |
| 947 | compatible = "renesas,du-r8a7791"; |
| 948 | reg = <0 0xfeb00000 0 0x40000>, |
| 949 | <0 0xfeb90000 0 0x1c>; |
| 950 | reg-names = "du", "lvds.0"; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 951 | interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, |
| 952 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 8eefac2 | 2014-01-21 16:00:46 +0100 | [diff] [blame] | 953 | clocks = <&mstp7_clks R8A7791_CLK_DU0>, |
| 954 | <&mstp7_clks R8A7791_CLK_DU1>, |
| 955 | <&mstp7_clks R8A7791_CLK_LVDS0>; |
| 956 | clock-names = "du.0", "du.1", "lvds.0"; |
| 957 | status = "disabled"; |
| 958 | |
| 959 | ports { |
| 960 | #address-cells = <1>; |
| 961 | #size-cells = <0>; |
| 962 | |
| 963 | port@0 { |
| 964 | reg = <0>; |
| 965 | du_out_rgb: endpoint { |
| 966 | }; |
| 967 | }; |
| 968 | port@1 { |
| 969 | reg = <1>; |
| 970 | du_out_lvds0: endpoint { |
| 971 | }; |
| 972 | }; |
| 973 | }; |
| 974 | }; |
| 975 | |
Sergei Shtylyov | 3cf0188 | 2015-01-06 01:25:25 +0300 | [diff] [blame] | 976 | can0: can@e6e80000 { |
| 977 | compatible = "renesas,can-r8a7791"; |
| 978 | reg = <0 0xe6e80000 0 0x1000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 979 | interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | 3cf0188 | 2015-01-06 01:25:25 +0300 | [diff] [blame] | 980 | clocks = <&mstp9_clks R8A7791_CLK_RCAN0>, |
| 981 | <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; |
| 982 | clock-names = "clkp1", "clkp2", "can_clk"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 983 | power-domains = <&cpg_clocks>; |
Sergei Shtylyov | 3cf0188 | 2015-01-06 01:25:25 +0300 | [diff] [blame] | 984 | status = "disabled"; |
| 985 | }; |
| 986 | |
| 987 | can1: can@e6e88000 { |
| 988 | compatible = "renesas,can-r8a7791"; |
| 989 | reg = <0 0xe6e88000 0 0x1000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 990 | interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | 3cf0188 | 2015-01-06 01:25:25 +0300 | [diff] [blame] | 991 | clocks = <&mstp9_clks R8A7791_CLK_RCAN1>, |
| 992 | <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; |
| 993 | clock-names = "clkp1", "clkp2", "can_clk"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 994 | power-domains = <&cpg_clocks>; |
Sergei Shtylyov | 3cf0188 | 2015-01-06 01:25:25 +0300 | [diff] [blame] | 995 | status = "disabled"; |
| 996 | }; |
| 997 | |
Mikhail Ulyanov | 0caa366 | 2015-07-24 16:25:46 +0300 | [diff] [blame] | 998 | jpu: jpeg-codec@fe980000 { |
| 999 | compatible = "renesas,jpu-r8a7791"; |
| 1000 | reg = <0 0xfe980000 0 0x10300>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1001 | interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; |
Mikhail Ulyanov | 0caa366 | 2015-07-24 16:25:46 +0300 | [diff] [blame] | 1002 | clocks = <&mstp1_clks R8A7791_CLK_JPU>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 1003 | power-domains = <&cpg_clocks>; |
Mikhail Ulyanov | 0caa366 | 2015-07-24 16:25:46 +0300 | [diff] [blame] | 1004 | }; |
| 1005 | |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1006 | clocks { |
| 1007 | #address-cells = <2>; |
| 1008 | #size-cells = <2>; |
| 1009 | ranges; |
| 1010 | |
| 1011 | /* External root clock */ |
| 1012 | extal_clk: extal_clk { |
| 1013 | compatible = "fixed-clock"; |
| 1014 | #clock-cells = <0>; |
| 1015 | /* This value must be overriden by the board. */ |
| 1016 | clock-frequency = <0>; |
| 1017 | clock-output-names = "extal"; |
| 1018 | }; |
| 1019 | |
Kuninori Morimoto | 0d3dbde | 2014-06-11 21:44:04 -0700 | [diff] [blame] | 1020 | /* |
| 1021 | * The external audio clocks are configured as 0 Hz fixed frequency clocks by |
| 1022 | * default. Boards that provide audio clocks should override them. |
| 1023 | */ |
| 1024 | audio_clk_a: audio_clk_a { |
| 1025 | compatible = "fixed-clock"; |
| 1026 | #clock-cells = <0>; |
| 1027 | clock-frequency = <0>; |
| 1028 | clock-output-names = "audio_clk_a"; |
| 1029 | }; |
| 1030 | audio_clk_b: audio_clk_b { |
| 1031 | compatible = "fixed-clock"; |
| 1032 | #clock-cells = <0>; |
| 1033 | clock-frequency = <0>; |
| 1034 | clock-output-names = "audio_clk_b"; |
| 1035 | }; |
| 1036 | audio_clk_c: audio_clk_c { |
| 1037 | compatible = "fixed-clock"; |
| 1038 | #clock-cells = <0>; |
| 1039 | clock-frequency = <0>; |
| 1040 | clock-output-names = "audio_clk_c"; |
| 1041 | }; |
| 1042 | |
Phil Edworthy | 66c405e | 2014-06-13 10:37:19 +0100 | [diff] [blame] | 1043 | /* External PCIe clock - can be overridden by the board */ |
| 1044 | pcie_bus_clk: pcie_bus_clk { |
| 1045 | compatible = "fixed-clock"; |
| 1046 | #clock-cells = <0>; |
| 1047 | clock-frequency = <100000000>; |
| 1048 | clock-output-names = "pcie_bus"; |
| 1049 | status = "disabled"; |
| 1050 | }; |
| 1051 | |
Sergei Shtylyov | b324252 | 2015-01-06 01:24:08 +0300 | [diff] [blame] | 1052 | /* External USB clock - can be overridden by the board */ |
| 1053 | usb_extal_clk: usb_extal_clk { |
| 1054 | compatible = "fixed-clock"; |
| 1055 | #clock-cells = <0>; |
| 1056 | clock-frequency = <48000000>; |
| 1057 | clock-output-names = "usb_extal"; |
| 1058 | }; |
| 1059 | |
| 1060 | /* External CAN clock */ |
| 1061 | can_clk: can_clk { |
| 1062 | compatible = "fixed-clock"; |
| 1063 | #clock-cells = <0>; |
| 1064 | /* This value must be overridden by the board. */ |
| 1065 | clock-frequency = <0>; |
| 1066 | clock-output-names = "can_clk"; |
| 1067 | status = "disabled"; |
| 1068 | }; |
| 1069 | |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1070 | /* Special CPG clocks */ |
| 1071 | cpg_clocks: cpg_clocks@e6150000 { |
| 1072 | compatible = "renesas,r8a7791-cpg-clocks", |
| 1073 | "renesas,rcar-gen2-cpg-clocks"; |
| 1074 | reg = <0 0xe6150000 0 0x1000>; |
Sergei Shtylyov | b324252 | 2015-01-06 01:24:08 +0300 | [diff] [blame] | 1075 | clocks = <&extal_clk &usb_extal_clk>; |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1076 | #clock-cells = <1>; |
| 1077 | clock-output-names = "main", "pll0", "pll1", "pll3", |
Sergei Shtylyov | b324252 | 2015-01-06 01:24:08 +0300 | [diff] [blame] | 1078 | "lb", "qspi", "sdh", "sd0", "z", |
Sergei Shtylyov | ae65a8a | 2014-12-30 23:20:34 +0300 | [diff] [blame] | 1079 | "rcan", "adsp"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 1080 | #power-domain-cells = <0>; |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1081 | }; |
| 1082 | |
| 1083 | /* Variable factor clocks */ |
Simon Horman | 2ea0d4e | 2015-01-29 10:41:24 +0900 | [diff] [blame] | 1084 | sd2_clk: sd2_clk@e6150078 { |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1085 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; |
| 1086 | reg = <0 0xe6150078 0 4>; |
| 1087 | clocks = <&pll1_div2_clk>; |
| 1088 | #clock-cells = <0>; |
Simon Horman | 2ea0d4e | 2015-01-29 10:41:24 +0900 | [diff] [blame] | 1089 | clock-output-names = "sd2"; |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1090 | }; |
Simon Horman | 2ea0d4e | 2015-01-29 10:41:24 +0900 | [diff] [blame] | 1091 | sd3_clk: sd3_clk@e615026c { |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1092 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; |
Shinobu Uehara | c9b2277 | 2014-07-21 22:04:29 -0700 | [diff] [blame] | 1093 | reg = <0 0xe615026c 0 4>; |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1094 | clocks = <&pll1_div2_clk>; |
| 1095 | #clock-cells = <0>; |
Simon Horman | 2ea0d4e | 2015-01-29 10:41:24 +0900 | [diff] [blame] | 1096 | clock-output-names = "sd3"; |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1097 | }; |
| 1098 | mmc0_clk: mmc0_clk@e6150240 { |
| 1099 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; |
| 1100 | reg = <0 0xe6150240 0 4>; |
| 1101 | clocks = <&pll1_div2_clk>; |
| 1102 | #clock-cells = <0>; |
| 1103 | clock-output-names = "mmc0"; |
| 1104 | }; |
| 1105 | ssp_clk: ssp_clk@e6150248 { |
| 1106 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; |
| 1107 | reg = <0 0xe6150248 0 4>; |
| 1108 | clocks = <&pll1_div2_clk>; |
| 1109 | #clock-cells = <0>; |
| 1110 | clock-output-names = "ssp"; |
| 1111 | }; |
| 1112 | ssprs_clk: ssprs_clk@e615024c { |
| 1113 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; |
| 1114 | reg = <0 0xe615024c 0 4>; |
| 1115 | clocks = <&pll1_div2_clk>; |
| 1116 | #clock-cells = <0>; |
| 1117 | clock-output-names = "ssprs"; |
| 1118 | }; |
| 1119 | |
| 1120 | /* Fixed factor clocks */ |
| 1121 | pll1_div2_clk: pll1_div2_clk { |
| 1122 | compatible = "fixed-factor-clock"; |
| 1123 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; |
| 1124 | #clock-cells = <0>; |
| 1125 | clock-div = <2>; |
| 1126 | clock-mult = <1>; |
| 1127 | clock-output-names = "pll1_div2"; |
| 1128 | }; |
| 1129 | zg_clk: zg_clk { |
| 1130 | compatible = "fixed-factor-clock"; |
| 1131 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; |
| 1132 | #clock-cells = <0>; |
| 1133 | clock-div = <3>; |
| 1134 | clock-mult = <1>; |
| 1135 | clock-output-names = "zg"; |
| 1136 | }; |
| 1137 | zx_clk: zx_clk { |
| 1138 | compatible = "fixed-factor-clock"; |
| 1139 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; |
| 1140 | #clock-cells = <0>; |
| 1141 | clock-div = <3>; |
| 1142 | clock-mult = <1>; |
| 1143 | clock-output-names = "zx"; |
| 1144 | }; |
| 1145 | zs_clk: zs_clk { |
| 1146 | compatible = "fixed-factor-clock"; |
| 1147 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; |
| 1148 | #clock-cells = <0>; |
| 1149 | clock-div = <6>; |
| 1150 | clock-mult = <1>; |
| 1151 | clock-output-names = "zs"; |
| 1152 | }; |
| 1153 | hp_clk: hp_clk { |
| 1154 | compatible = "fixed-factor-clock"; |
| 1155 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; |
| 1156 | #clock-cells = <0>; |
| 1157 | clock-div = <12>; |
| 1158 | clock-mult = <1>; |
| 1159 | clock-output-names = "hp"; |
| 1160 | }; |
| 1161 | i_clk: i_clk { |
| 1162 | compatible = "fixed-factor-clock"; |
| 1163 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; |
| 1164 | #clock-cells = <0>; |
| 1165 | clock-div = <2>; |
| 1166 | clock-mult = <1>; |
| 1167 | clock-output-names = "i"; |
| 1168 | }; |
| 1169 | b_clk: b_clk { |
| 1170 | compatible = "fixed-factor-clock"; |
| 1171 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; |
| 1172 | #clock-cells = <0>; |
| 1173 | clock-div = <12>; |
| 1174 | clock-mult = <1>; |
| 1175 | clock-output-names = "b"; |
| 1176 | }; |
| 1177 | p_clk: p_clk { |
| 1178 | compatible = "fixed-factor-clock"; |
| 1179 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; |
| 1180 | #clock-cells = <0>; |
| 1181 | clock-div = <24>; |
| 1182 | clock-mult = <1>; |
| 1183 | clock-output-names = "p"; |
| 1184 | }; |
| 1185 | cl_clk: cl_clk { |
| 1186 | compatible = "fixed-factor-clock"; |
| 1187 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; |
| 1188 | #clock-cells = <0>; |
| 1189 | clock-div = <48>; |
| 1190 | clock-mult = <1>; |
| 1191 | clock-output-names = "cl"; |
| 1192 | }; |
| 1193 | m2_clk: m2_clk { |
| 1194 | compatible = "fixed-factor-clock"; |
| 1195 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; |
| 1196 | #clock-cells = <0>; |
| 1197 | clock-div = <8>; |
| 1198 | clock-mult = <1>; |
| 1199 | clock-output-names = "m2"; |
| 1200 | }; |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1201 | rclk_clk: rclk_clk { |
| 1202 | compatible = "fixed-factor-clock"; |
| 1203 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; |
| 1204 | #clock-cells = <0>; |
| 1205 | clock-div = <(48 * 1024)>; |
| 1206 | clock-mult = <1>; |
| 1207 | clock-output-names = "rclk"; |
| 1208 | }; |
| 1209 | oscclk_clk: oscclk_clk { |
| 1210 | compatible = "fixed-factor-clock"; |
| 1211 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; |
| 1212 | #clock-cells = <0>; |
| 1213 | clock-div = <(12 * 1024)>; |
| 1214 | clock-mult = <1>; |
| 1215 | clock-output-names = "oscclk"; |
| 1216 | }; |
| 1217 | zb3_clk: zb3_clk { |
| 1218 | compatible = "fixed-factor-clock"; |
| 1219 | clocks = <&cpg_clocks R8A7791_CLK_PLL3>; |
| 1220 | #clock-cells = <0>; |
| 1221 | clock-div = <4>; |
| 1222 | clock-mult = <1>; |
| 1223 | clock-output-names = "zb3"; |
| 1224 | }; |
| 1225 | zb3d2_clk: zb3d2_clk { |
| 1226 | compatible = "fixed-factor-clock"; |
| 1227 | clocks = <&cpg_clocks R8A7791_CLK_PLL3>; |
| 1228 | #clock-cells = <0>; |
| 1229 | clock-div = <8>; |
| 1230 | clock-mult = <1>; |
| 1231 | clock-output-names = "zb3d2"; |
| 1232 | }; |
| 1233 | ddr_clk: ddr_clk { |
| 1234 | compatible = "fixed-factor-clock"; |
| 1235 | clocks = <&cpg_clocks R8A7791_CLK_PLL3>; |
| 1236 | #clock-cells = <0>; |
| 1237 | clock-div = <8>; |
| 1238 | clock-mult = <1>; |
| 1239 | clock-output-names = "ddr"; |
| 1240 | }; |
| 1241 | mp_clk: mp_clk { |
| 1242 | compatible = "fixed-factor-clock"; |
| 1243 | clocks = <&pll1_div2_clk>; |
| 1244 | #clock-cells = <0>; |
| 1245 | clock-div = <15>; |
| 1246 | clock-mult = <1>; |
| 1247 | clock-output-names = "mp"; |
| 1248 | }; |
| 1249 | cp_clk: cp_clk { |
| 1250 | compatible = "fixed-factor-clock"; |
| 1251 | clocks = <&extal_clk>; |
| 1252 | #clock-cells = <0>; |
| 1253 | clock-div = <2>; |
| 1254 | clock-mult = <1>; |
| 1255 | clock-output-names = "cp"; |
| 1256 | }; |
| 1257 | |
| 1258 | /* Gate clocks */ |
Laurent Pinchart | cded80f | 2013-12-19 16:51:02 +0100 | [diff] [blame] | 1259 | mstp0_clks: mstp0_clks@e6150130 { |
| 1260 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1261 | reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; |
| 1262 | clocks = <&mp_clk>; |
| 1263 | #clock-cells = <1>; |
Ben Dooks | cb0bf85 | 2014-11-10 19:49:38 +0100 | [diff] [blame] | 1264 | clock-indices = <R8A7791_CLK_MSIOF0>; |
Laurent Pinchart | cded80f | 2013-12-19 16:51:02 +0100 | [diff] [blame] | 1265 | clock-output-names = "msiof0"; |
| 1266 | }; |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1267 | mstp1_clks: mstp1_clks@e6150134 { |
| 1268 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1269 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; |
Yoshifumi Hosoya | 74d89d2 | 2014-10-14 16:01:43 +0900 | [diff] [blame] | 1270 | clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>, |
| 1271 | <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, |
| 1272 | <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>, |
| 1273 | <&zs_clk>; |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1274 | #clock-cells = <1>; |
Ben Dooks | cb0bf85 | 2014-11-10 19:49:38 +0100 | [diff] [blame] | 1275 | clock-indices = < |
Yoshifumi Hosoya | 74d89d2 | 2014-10-14 16:01:43 +0900 | [diff] [blame] | 1276 | R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU |
| 1277 | R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG |
| 1278 | R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0 |
| 1279 | R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0 |
| 1280 | R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0 |
| 1281 | R8A7791_CLK_VSP1_S |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1282 | >; |
| 1283 | clock-output-names = |
Yoshifumi Hosoya | 74d89d2 | 2014-10-14 16:01:43 +0900 | [diff] [blame] | 1284 | "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg", |
| 1285 | "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0", |
| 1286 | "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy"; |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1287 | }; |
| 1288 | mstp2_clks: mstp2_clks@e6150138 { |
| 1289 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1290 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; |
| 1291 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, |
Geert Uytterhoeven | 4e074bc | 2014-06-02 15:42:07 +0200 | [diff] [blame] | 1292 | <&mp_clk>, <&mp_clk>, <&mp_clk>, |
| 1293 | <&zs_clk>, <&zs_clk>; |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1294 | #clock-cells = <1>; |
Ben Dooks | cb0bf85 | 2014-11-10 19:49:38 +0100 | [diff] [blame] | 1295 | clock-indices = < |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1296 | R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 |
Laurent Pinchart | cded80f | 2013-12-19 16:51:02 +0100 | [diff] [blame] | 1297 | R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 |
| 1298 | R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 |
Geert Uytterhoeven | 4e074bc | 2014-06-02 15:42:07 +0200 | [diff] [blame] | 1299 | R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0 |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1300 | >; |
| 1301 | clock-output-names = |
Geert Uytterhoeven | 0c002ef | 2014-02-20 15:49:29 +0100 | [diff] [blame] | 1302 | "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", |
Geert Uytterhoeven | 4e074bc | 2014-06-02 15:42:07 +0200 | [diff] [blame] | 1303 | "scifb1", "msiof1", "scifb2", |
| 1304 | "sys-dmac1", "sys-dmac0"; |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1305 | }; |
| 1306 | mstp3_clks: mstp3_clks@e615013c { |
| 1307 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1308 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; |
Simon Horman | 2ea0d4e | 2015-01-29 10:41:24 +0900 | [diff] [blame] | 1309 | clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>, |
Yoshihiro Shimoda | b9473d9 | 2014-11-17 18:25:25 +0900 | [diff] [blame] | 1310 | <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, |
| 1311 | <&hp_clk>, <&hp_clk>; |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1312 | #clock-cells = <1>; |
Ben Dooks | cb0bf85 | 2014-11-10 19:49:38 +0100 | [diff] [blame] | 1313 | clock-indices = < |
Wolfram Sang | c08691b | 2014-03-10 12:26:57 +0100 | [diff] [blame] | 1314 | R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 |
Phil Edworthy | 4bfb376 | 2014-06-13 10:37:18 +0100 | [diff] [blame] | 1315 | R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1 |
| 1316 | R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 |
Yoshihiro Shimoda | b9473d9 | 2014-11-17 18:25:25 +0900 | [diff] [blame] | 1317 | R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1 |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1318 | >; |
| 1319 | clock-output-names = |
Wolfram Sang | c08691b | 2014-03-10 12:26:57 +0100 | [diff] [blame] | 1320 | "tpu0", "sdhi2", "sdhi1", "sdhi0", |
Yoshihiro Shimoda | b9473d9 | 2014-11-17 18:25:25 +0900 | [diff] [blame] | 1321 | "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1", |
| 1322 | "usbdmac0", "usbdmac1"; |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1323 | }; |
Geert Uytterhoeven | 62d386c | 2015-03-18 19:56:00 +0100 | [diff] [blame] | 1324 | mstp4_clks: mstp4_clks@e6150140 { |
| 1325 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1326 | reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; |
| 1327 | clocks = <&cp_clk>; |
| 1328 | #clock-cells = <1>; |
| 1329 | clock-indices = <R8A7791_CLK_IRQC>; |
| 1330 | clock-output-names = "irqc"; |
| 1331 | }; |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1332 | mstp5_clks: mstp5_clks@e6150144 { |
| 1333 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1334 | reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; |
Sergei Shtylyov | ae65a8a | 2014-12-30 23:20:34 +0300 | [diff] [blame] | 1335 | clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>, |
| 1336 | <&extal_clk>, <&p_clk>; |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1337 | #clock-cells = <1>; |
Ben Dooks | cb0bf85 | 2014-11-10 19:49:38 +0100 | [diff] [blame] | 1338 | clock-indices = < |
| 1339 | R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1 |
Sergei Shtylyov | ae65a8a | 2014-12-30 23:20:34 +0300 | [diff] [blame] | 1340 | R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL |
| 1341 | R8A7791_CLK_PWM |
Ben Dooks | cb0bf85 | 2014-11-10 19:49:38 +0100 | [diff] [blame] | 1342 | >; |
Sergei Shtylyov | ae65a8a | 2014-12-30 23:20:34 +0300 | [diff] [blame] | 1343 | clock-output-names = "audmac0", "audmac1", "adsp_mod", |
| 1344 | "thermal", "pwm"; |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1345 | }; |
| 1346 | mstp7_clks: mstp7_clks@e615014c { |
| 1347 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1348 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; |
Kazuya Mizuguchi | 118e4e6 | 2015-02-19 10:43:10 -0500 | [diff] [blame] | 1349 | clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1350 | <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, |
| 1351 | <&zx_clk>, <&zx_clk>, <&zx_clk>; |
| 1352 | #clock-cells = <1>; |
Ben Dooks | cb0bf85 | 2014-11-10 19:49:38 +0100 | [diff] [blame] | 1353 | clock-indices = < |
Magnus Damm | 6225b99 | 2014-04-07 15:04:21 +0900 | [diff] [blame] | 1354 | R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1355 | R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 |
| 1356 | R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 |
| 1357 | R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0 |
| 1358 | R8A7791_CLK_LVDS0 |
| 1359 | >; |
| 1360 | clock-output-names = |
Magnus Damm | 6225b99 | 2014-04-07 15:04:21 +0900 | [diff] [blame] | 1361 | "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1362 | "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0"; |
| 1363 | }; |
| 1364 | mstp8_clks: mstp8_clks@e6150990 { |
| 1365 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1366 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; |
Ryo Kataoka | 75a499a | 2015-02-19 22:29:06 +0900 | [diff] [blame] | 1367 | clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>, |
Sergei Shtylyov | eaa870b | 2015-12-03 01:21:49 +0300 | [diff] [blame] | 1368 | <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>, |
| 1369 | <&zs_clk>; |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1370 | #clock-cells = <1>; |
Ben Dooks | cb0bf85 | 2014-11-10 19:49:38 +0100 | [diff] [blame] | 1371 | clock-indices = < |
Andrey Gusakov | 7408d30 | 2014-12-18 23:43:03 +0300 | [diff] [blame] | 1372 | R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB |
Laurent Pinchart | 09c9834 | 2014-01-07 09:22:54 +0100 | [diff] [blame] | 1373 | R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0 |
Sergei Shtylyov | eaa870b | 2015-12-03 01:21:49 +0300 | [diff] [blame] | 1374 | R8A7791_CLK_ETHERAVB R8A7791_CLK_ETHER |
| 1375 | R8A7791_CLK_SATA1 R8A7791_CLK_SATA0 |
Laurent Pinchart | 09c9834 | 2014-01-07 09:22:54 +0100 | [diff] [blame] | 1376 | >; |
Laurent Pinchart | 65f05c3 | 2014-01-07 09:22:56 +0100 | [diff] [blame] | 1377 | clock-output-names = |
Sergei Shtylyov | eaa870b | 2015-12-03 01:21:49 +0300 | [diff] [blame] | 1378 | "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0", |
| 1379 | "etheravb", "ether", "sata1", "sata0"; |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1380 | }; |
| 1381 | mstp9_clks: mstp9_clks@e6150994 { |
| 1382 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1383 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; |
Geert Uytterhoeven | 4faf9c5 | 2014-04-23 10:25:28 +0200 | [diff] [blame] | 1384 | clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, |
| 1385 | <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, |
| 1386 | <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>, |
Laurent Pinchart | 11b48db | 2014-04-01 13:02:18 +0200 | [diff] [blame] | 1387 | <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, |
| 1388 | <&hp_clk>, <&hp_clk>; |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1389 | #clock-cells = <1>; |
Ben Dooks | cb0bf85 | 2014-11-10 19:49:38 +0100 | [diff] [blame] | 1390 | clock-indices = < |
Geert Uytterhoeven | 4faf9c5 | 2014-04-23 10:25:28 +0200 | [diff] [blame] | 1391 | R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4 |
| 1392 | R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0 |
Wolfram Sang | c08691b | 2014-03-10 12:26:57 +0100 | [diff] [blame] | 1393 | R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 |
| 1394 | R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2 |
| 1395 | R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1396 | >; |
| 1397 | clock-output-names = |
Geert Uytterhoeven | 4faf9c5 | 2014-04-23 10:25:28 +0200 | [diff] [blame] | 1398 | "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", |
| 1399 | "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2", |
| 1400 | "i2c1", "i2c0"; |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1401 | }; |
Kuninori Morimoto | ee91415 | 2014-06-11 21:44:16 -0700 | [diff] [blame] | 1402 | mstp10_clks: mstp10_clks@e6150998 { |
| 1403 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1404 | reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; |
| 1405 | clocks = <&p_clk>, |
| 1406 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, |
| 1407 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, |
| 1408 | <&p_clk>, |
| 1409 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, |
| 1410 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, |
| 1411 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, |
| 1412 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, |
| 1413 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, |
Kuninori Morimoto | 8840170 | 2015-07-21 00:27:03 +0000 | [diff] [blame] | 1414 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, |
Kuninori Morimoto | ee91415 | 2014-06-11 21:44:16 -0700 | [diff] [blame] | 1415 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>; |
| 1416 | |
| 1417 | #clock-cells = <1>; |
| 1418 | clock-indices = < |
| 1419 | R8A7791_CLK_SSI_ALL |
| 1420 | R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5 |
| 1421 | R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0 |
| 1422 | R8A7791_CLK_SCU_ALL |
| 1423 | R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0 |
Kuninori Morimoto | 8840170 | 2015-07-21 00:27:03 +0000 | [diff] [blame] | 1424 | R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0 |
Kuninori Morimoto | ee91415 | 2014-06-11 21:44:16 -0700 | [diff] [blame] | 1425 | R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5 |
| 1426 | R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0 |
| 1427 | >; |
| 1428 | clock-output-names = |
| 1429 | "ssi-all", |
| 1430 | "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", |
| 1431 | "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", |
| 1432 | "scu-all", |
| 1433 | "scu-dvc1", "scu-dvc0", |
Kuninori Morimoto | 8840170 | 2015-07-21 00:27:03 +0000 | [diff] [blame] | 1434 | "scu-ctu1-mix1", "scu-ctu0-mix0", |
Kuninori Morimoto | ee91415 | 2014-06-11 21:44:16 -0700 | [diff] [blame] | 1435 | "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", |
| 1436 | "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; |
| 1437 | }; |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1438 | mstp11_clks: mstp11_clks@e615099c { |
| 1439 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1440 | reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; |
| 1441 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; |
| 1442 | #clock-cells = <1>; |
Ben Dooks | cb0bf85 | 2014-11-10 19:49:38 +0100 | [diff] [blame] | 1443 | clock-indices = < |
Laurent Pinchart | 59e7989 | 2013-12-11 15:05:16 +0100 | [diff] [blame] | 1444 | R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5 |
| 1445 | >; |
| 1446 | clock-output-names = "scifa3", "scifa4", "scifa5"; |
| 1447 | }; |
| 1448 | }; |
Geert Uytterhoeven | 4d5b59c | 2014-02-04 16:24:03 +0100 | [diff] [blame] | 1449 | |
Geert Uytterhoeven | 6f3e4ee | 2014-02-25 11:30:14 +0100 | [diff] [blame] | 1450 | qspi: spi@e6b10000 { |
Geert Uytterhoeven | 4d5b59c | 2014-02-04 16:24:03 +0100 | [diff] [blame] | 1451 | compatible = "renesas,qspi-r8a7791", "renesas,qspi"; |
| 1452 | reg = <0 0xe6b10000 0 0x2c>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1453 | interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 4d5b59c | 2014-02-04 16:24:03 +0100 | [diff] [blame] | 1454 | clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; |
Geert Uytterhoeven | 591f2fa | 2014-08-06 14:59:06 +0200 | [diff] [blame] | 1455 | dmas = <&dmac0 0x17>, <&dmac0 0x18>; |
| 1456 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 1457 | power-domains = <&cpg_clocks>; |
Geert Uytterhoeven | 4d5b59c | 2014-02-04 16:24:03 +0100 | [diff] [blame] | 1458 | num-cs = <1>; |
| 1459 | #address-cells = <1>; |
| 1460 | #size-cells = <0>; |
| 1461 | status = "disabled"; |
| 1462 | }; |
Geert Uytterhoeven | 7713d3a | 2014-02-25 11:30:16 +0100 | [diff] [blame] | 1463 | |
| 1464 | msiof0: spi@e6e20000 { |
| 1465 | compatible = "renesas,msiof-r8a7791"; |
Ryo Kataoka | cb6d08a | 2015-04-05 01:55:12 +0900 | [diff] [blame] | 1466 | reg = <0 0xe6e20000 0 0x0064>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1467 | interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 7713d3a | 2014-02-25 11:30:16 +0100 | [diff] [blame] | 1468 | clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; |
Geert Uytterhoeven | a5ce27f | 2014-08-06 14:59:07 +0200 | [diff] [blame] | 1469 | dmas = <&dmac0 0x51>, <&dmac0 0x52>; |
| 1470 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 1471 | power-domains = <&cpg_clocks>; |
Geert Uytterhoeven | 7713d3a | 2014-02-25 11:30:16 +0100 | [diff] [blame] | 1472 | #address-cells = <1>; |
| 1473 | #size-cells = <0>; |
| 1474 | status = "disabled"; |
| 1475 | }; |
| 1476 | |
| 1477 | msiof1: spi@e6e10000 { |
| 1478 | compatible = "renesas,msiof-r8a7791"; |
Ryo Kataoka | cb6d08a | 2015-04-05 01:55:12 +0900 | [diff] [blame] | 1479 | reg = <0 0xe6e10000 0 0x0064>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1480 | interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 7713d3a | 2014-02-25 11:30:16 +0100 | [diff] [blame] | 1481 | clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; |
Geert Uytterhoeven | a5ce27f | 2014-08-06 14:59:07 +0200 | [diff] [blame] | 1482 | dmas = <&dmac0 0x55>, <&dmac0 0x56>; |
| 1483 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 1484 | power-domains = <&cpg_clocks>; |
Geert Uytterhoeven | 7713d3a | 2014-02-25 11:30:16 +0100 | [diff] [blame] | 1485 | #address-cells = <1>; |
| 1486 | #size-cells = <0>; |
| 1487 | status = "disabled"; |
| 1488 | }; |
| 1489 | |
| 1490 | msiof2: spi@e6e00000 { |
| 1491 | compatible = "renesas,msiof-r8a7791"; |
Ryo Kataoka | cb6d08a | 2015-04-05 01:55:12 +0900 | [diff] [blame] | 1492 | reg = <0 0xe6e00000 0 0x0064>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1493 | interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 7713d3a | 2014-02-25 11:30:16 +0100 | [diff] [blame] | 1494 | clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; |
Geert Uytterhoeven | a5ce27f | 2014-08-06 14:59:07 +0200 | [diff] [blame] | 1495 | dmas = <&dmac0 0x41>, <&dmac0 0x42>; |
| 1496 | dma-names = "tx", "rx"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 1497 | power-domains = <&cpg_clocks>; |
Geert Uytterhoeven | 7713d3a | 2014-02-25 11:30:16 +0100 | [diff] [blame] | 1498 | #address-cells = <1>; |
| 1499 | #size-cells = <0>; |
| 1500 | status = "disabled"; |
| 1501 | }; |
Phil Edworthy | 811cdfa | 2014-06-13 10:37:20 +0100 | [diff] [blame] | 1502 | |
Yoshihiro Shimoda | c196931 | 2014-10-24 19:43:02 +0900 | [diff] [blame] | 1503 | xhci: usb@ee000000 { |
| 1504 | compatible = "renesas,xhci-r8a7791"; |
| 1505 | reg = <0 0xee000000 0 0xc00>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1506 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
Yoshihiro Shimoda | c196931 | 2014-10-24 19:43:02 +0900 | [diff] [blame] | 1507 | clocks = <&mstp3_clks R8A7791_CLK_SSUSB>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 1508 | power-domains = <&cpg_clocks>; |
Yoshihiro Shimoda | c196931 | 2014-10-24 19:43:02 +0900 | [diff] [blame] | 1509 | phys = <&usb2 1>; |
| 1510 | phy-names = "usb"; |
| 1511 | status = "disabled"; |
| 1512 | }; |
| 1513 | |
Sergei Shtylyov | aace080 | 2014-06-24 22:10:05 +0400 | [diff] [blame] | 1514 | pci0: pci@ee090000 { |
| 1515 | compatible = "renesas,pci-r8a7791"; |
| 1516 | device_type = "pci"; |
Sergei Shtylyov | aace080 | 2014-06-24 22:10:05 +0400 | [diff] [blame] | 1517 | reg = <0 0xee090000 0 0xc00>, |
| 1518 | <0 0xee080000 0 0x1100>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1519 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 1520 | clocks = <&mstp7_clks R8A7791_CLK_EHCI>; |
| 1521 | power-domains = <&cpg_clocks>; |
Sergei Shtylyov | aace080 | 2014-06-24 22:10:05 +0400 | [diff] [blame] | 1522 | status = "disabled"; |
| 1523 | |
| 1524 | bus-range = <0 0>; |
| 1525 | #address-cells = <3>; |
| 1526 | #size-cells = <2>; |
| 1527 | #interrupt-cells = <1>; |
| 1528 | ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; |
| 1529 | interrupt-map-mask = <0xff00 0 0 0x7>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1530 | interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH |
| 1531 | 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH |
| 1532 | 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | e1bce12 | 2014-09-29 22:23:11 +0400 | [diff] [blame] | 1533 | |
| 1534 | usb@0,1 { |
| 1535 | reg = <0x800 0 0 0 0>; |
| 1536 | device_type = "pci"; |
| 1537 | phys = <&usb0 0>; |
| 1538 | phy-names = "usb"; |
| 1539 | }; |
| 1540 | |
| 1541 | usb@0,2 { |
| 1542 | reg = <0x1000 0 0 0 0>; |
| 1543 | device_type = "pci"; |
| 1544 | phys = <&usb0 0>; |
| 1545 | phy-names = "usb"; |
| 1546 | }; |
Sergei Shtylyov | aace080 | 2014-06-24 22:10:05 +0400 | [diff] [blame] | 1547 | }; |
| 1548 | |
| 1549 | pci1: pci@ee0d0000 { |
| 1550 | compatible = "renesas,pci-r8a7791"; |
| 1551 | device_type = "pci"; |
Sergei Shtylyov | aace080 | 2014-06-24 22:10:05 +0400 | [diff] [blame] | 1552 | reg = <0 0xee0d0000 0 0xc00>, |
| 1553 | <0 0xee0c0000 0 0x1100>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1554 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 1555 | clocks = <&mstp7_clks R8A7791_CLK_EHCI>; |
| 1556 | power-domains = <&cpg_clocks>; |
Sergei Shtylyov | aace080 | 2014-06-24 22:10:05 +0400 | [diff] [blame] | 1557 | status = "disabled"; |
| 1558 | |
| 1559 | bus-range = <1 1>; |
| 1560 | #address-cells = <3>; |
| 1561 | #size-cells = <2>; |
| 1562 | #interrupt-cells = <1>; |
| 1563 | ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; |
| 1564 | interrupt-map-mask = <0xff00 0 0 0x7>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1565 | interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH |
| 1566 | 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH |
| 1567 | 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | e1bce12 | 2014-09-29 22:23:11 +0400 | [diff] [blame] | 1568 | |
| 1569 | usb@0,1 { |
| 1570 | reg = <0x800 0 0 0 0>; |
| 1571 | device_type = "pci"; |
| 1572 | phys = <&usb2 0>; |
| 1573 | phy-names = "usb"; |
| 1574 | }; |
| 1575 | |
| 1576 | usb@0,2 { |
| 1577 | reg = <0x1000 0 0 0 0>; |
| 1578 | device_type = "pci"; |
| 1579 | phys = <&usb2 0>; |
| 1580 | phy-names = "usb"; |
| 1581 | }; |
Sergei Shtylyov | aace080 | 2014-06-24 22:10:05 +0400 | [diff] [blame] | 1582 | }; |
| 1583 | |
Phil Edworthy | 811cdfa | 2014-06-13 10:37:20 +0100 | [diff] [blame] | 1584 | pciec: pcie@fe000000 { |
| 1585 | compatible = "renesas,pcie-r8a7791"; |
| 1586 | reg = <0 0xfe000000 0 0x80000>; |
| 1587 | #address-cells = <3>; |
| 1588 | #size-cells = <2>; |
| 1589 | bus-range = <0x00 0xff>; |
| 1590 | device_type = "pci"; |
| 1591 | ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 |
| 1592 | 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 |
| 1593 | 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 |
| 1594 | 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; |
| 1595 | /* Map all possible DDR as inbound ranges */ |
| 1596 | dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 |
| 1597 | 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1598 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| 1599 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 1600 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; |
Phil Edworthy | 811cdfa | 2014-06-13 10:37:20 +0100 | [diff] [blame] | 1601 | #interrupt-cells = <1>; |
| 1602 | interrupt-map-mask = <0 0 0 0>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1603 | interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
Phil Edworthy | 811cdfa | 2014-06-13 10:37:20 +0100 | [diff] [blame] | 1604 | clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>; |
| 1605 | clock-names = "pcie", "pcie_bus"; |
Geert Uytterhoeven | 797a062 | 2015-08-04 14:28:11 +0200 | [diff] [blame] | 1606 | power-domains = <&cpg_clocks>; |
Phil Edworthy | 811cdfa | 2014-06-13 10:37:20 +0100 | [diff] [blame] | 1607 | status = "disabled"; |
| 1608 | }; |
Kuninori Morimoto | 09abd1f | 2014-06-11 21:44:26 -0700 | [diff] [blame] | 1609 | |
Laurent Pinchart | f195185 | 2015-01-27 11:13:24 +0200 | [diff] [blame] | 1610 | ipmmu_sy0: mmu@e6280000 { |
Magnus Damm | 3c8ab0c | 2015-11-17 13:31:05 +0900 | [diff] [blame] | 1611 | compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; |
Laurent Pinchart | f195185 | 2015-01-27 11:13:24 +0200 | [diff] [blame] | 1612 | reg = <0 0xe6280000 0 0x1000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1613 | interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, |
| 1614 | <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f195185 | 2015-01-27 11:13:24 +0200 | [diff] [blame] | 1615 | #iommu-cells = <1>; |
| 1616 | status = "disabled"; |
| 1617 | }; |
| 1618 | |
| 1619 | ipmmu_sy1: mmu@e6290000 { |
Magnus Damm | 3c8ab0c | 2015-11-17 13:31:05 +0900 | [diff] [blame] | 1620 | compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; |
Laurent Pinchart | f195185 | 2015-01-27 11:13:24 +0200 | [diff] [blame] | 1621 | reg = <0 0xe6290000 0 0x1000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1622 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f195185 | 2015-01-27 11:13:24 +0200 | [diff] [blame] | 1623 | #iommu-cells = <1>; |
| 1624 | status = "disabled"; |
| 1625 | }; |
| 1626 | |
| 1627 | ipmmu_ds: mmu@e6740000 { |
Magnus Damm | 3c8ab0c | 2015-11-17 13:31:05 +0900 | [diff] [blame] | 1628 | compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; |
Laurent Pinchart | f195185 | 2015-01-27 11:13:24 +0200 | [diff] [blame] | 1629 | reg = <0 0xe6740000 0 0x1000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1630 | interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, |
| 1631 | <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f195185 | 2015-01-27 11:13:24 +0200 | [diff] [blame] | 1632 | #iommu-cells = <1>; |
| 1633 | status = "disabled"; |
| 1634 | }; |
| 1635 | |
| 1636 | ipmmu_mp: mmu@ec680000 { |
Magnus Damm | 3c8ab0c | 2015-11-17 13:31:05 +0900 | [diff] [blame] | 1637 | compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; |
Laurent Pinchart | f195185 | 2015-01-27 11:13:24 +0200 | [diff] [blame] | 1638 | reg = <0 0xec680000 0 0x1000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1639 | interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f195185 | 2015-01-27 11:13:24 +0200 | [diff] [blame] | 1640 | #iommu-cells = <1>; |
| 1641 | status = "disabled"; |
| 1642 | }; |
| 1643 | |
| 1644 | ipmmu_mx: mmu@fe951000 { |
Magnus Damm | 3c8ab0c | 2015-11-17 13:31:05 +0900 | [diff] [blame] | 1645 | compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; |
Laurent Pinchart | f195185 | 2015-01-27 11:13:24 +0200 | [diff] [blame] | 1646 | reg = <0 0xfe951000 0 0x1000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1647 | interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, |
| 1648 | <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f195185 | 2015-01-27 11:13:24 +0200 | [diff] [blame] | 1649 | #iommu-cells = <1>; |
| 1650 | status = "disabled"; |
| 1651 | }; |
| 1652 | |
| 1653 | ipmmu_rt: mmu@ffc80000 { |
Magnus Damm | 3c8ab0c | 2015-11-17 13:31:05 +0900 | [diff] [blame] | 1654 | compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; |
Laurent Pinchart | f195185 | 2015-01-27 11:13:24 +0200 | [diff] [blame] | 1655 | reg = <0 0xffc80000 0 0x1000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1656 | interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f195185 | 2015-01-27 11:13:24 +0200 | [diff] [blame] | 1657 | #iommu-cells = <1>; |
| 1658 | status = "disabled"; |
| 1659 | }; |
| 1660 | |
| 1661 | ipmmu_gp: mmu@e62a0000 { |
Magnus Damm | 3c8ab0c | 2015-11-17 13:31:05 +0900 | [diff] [blame] | 1662 | compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; |
Laurent Pinchart | f195185 | 2015-01-27 11:13:24 +0200 | [diff] [blame] | 1663 | reg = <0 0xe62a0000 0 0x1000>; |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1664 | interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, |
| 1665 | <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f195185 | 2015-01-27 11:13:24 +0200 | [diff] [blame] | 1666 | #iommu-cells = <1>; |
| 1667 | status = "disabled"; |
| 1668 | }; |
| 1669 | |
Geert Uytterhoeven | 6c63e07 | 2015-04-27 14:55:29 +0200 | [diff] [blame] | 1670 | rcar_sound: sound@ec500000 { |
Kuninori Morimoto | d2b541c | 2014-12-17 06:12:02 +0000 | [diff] [blame] | 1671 | /* |
| 1672 | * #sound-dai-cells is required |
| 1673 | * |
| 1674 | * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; |
| 1675 | * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; |
| 1676 | */ |
Geert Uytterhoeven | f49cd2b | 2015-01-06 21:01:53 +0100 | [diff] [blame] | 1677 | compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2"; |
Kuninori Morimoto | 09abd1f | 2014-06-11 21:44:26 -0700 | [diff] [blame] | 1678 | reg = <0 0xec500000 0 0x1000>, /* SCU */ |
| 1679 | <0 0xec5a0000 0 0x100>, /* ADG */ |
| 1680 | <0 0xec540000 0 0x1000>, /* SSIU */ |
Kuninori Morimoto | 8c3f903 | 2015-08-24 08:28:17 +0000 | [diff] [blame] | 1681 | <0 0xec541000 0 0x280>, /* SSI */ |
Kuninori Morimoto | d73a501 | 2015-03-10 01:39:55 +0000 | [diff] [blame] | 1682 | <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ |
| 1683 | reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; |
Kuninori Morimoto | d88a6a2 | 2015-03-10 01:39:18 +0000 | [diff] [blame] | 1684 | |
Kuninori Morimoto | 09abd1f | 2014-06-11 21:44:26 -0700 | [diff] [blame] | 1685 | clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>, |
| 1686 | <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>, |
| 1687 | <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>, |
| 1688 | <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>, |
| 1689 | <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>, |
| 1690 | <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>, |
| 1691 | <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>, |
| 1692 | <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>, |
| 1693 | <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>, |
| 1694 | <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>, |
| 1695 | <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>, |
Kuninori Morimoto | 8840170 | 2015-07-21 00:27:03 +0000 | [diff] [blame] | 1696 | <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, |
Kuninori Morimoto | 7fd6e11 | 2015-07-21 00:27:24 +0000 | [diff] [blame] | 1697 | <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, |
Kuninori Morimoto | 150c8ad | 2014-06-25 17:52:33 -0700 | [diff] [blame] | 1698 | <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>, |
Kuninori Morimoto | 09abd1f | 2014-06-11 21:44:26 -0700 | [diff] [blame] | 1699 | <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; |
| 1700 | clock-names = "ssi-all", |
| 1701 | "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", |
| 1702 | "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", |
| 1703 | "src.9", "src.8", "src.7", "src.6", "src.5", |
| 1704 | "src.4", "src.3", "src.2", "src.1", "src.0", |
Kuninori Morimoto | 8840170 | 2015-07-21 00:27:03 +0000 | [diff] [blame] | 1705 | "ctu.0", "ctu.1", |
Kuninori Morimoto | 7fd6e11 | 2015-07-21 00:27:24 +0000 | [diff] [blame] | 1706 | "mix.0", "mix.1", |
Kuninori Morimoto | 150c8ad | 2014-06-25 17:52:33 -0700 | [diff] [blame] | 1707 | "dvc.0", "dvc.1", |
Kuninori Morimoto | 09abd1f | 2014-06-11 21:44:26 -0700 | [diff] [blame] | 1708 | "clk_a", "clk_b", "clk_c", "clk_i"; |
Geert Uytterhoeven | 56e86dd | 2015-08-20 01:25:20 +0000 | [diff] [blame] | 1709 | power-domains = <&cpg_clocks>; |
Kuninori Morimoto | 09abd1f | 2014-06-11 21:44:26 -0700 | [diff] [blame] | 1710 | |
| 1711 | status = "disabled"; |
| 1712 | |
Kuninori Morimoto | 150c8ad | 2014-06-25 17:52:33 -0700 | [diff] [blame] | 1713 | rcar_sound,dvc { |
Kuninori Morimoto | 6357333 | 2015-03-10 01:40:27 +0000 | [diff] [blame] | 1714 | dvc0: dvc@0 { |
| 1715 | dmas = <&audma0 0xbc>; |
| 1716 | dma-names = "tx"; |
| 1717 | }; |
| 1718 | dvc1: dvc@1 { |
| 1719 | dmas = <&audma0 0xbe>; |
| 1720 | dma-names = "tx"; |
| 1721 | }; |
Kuninori Morimoto | 150c8ad | 2014-06-25 17:52:33 -0700 | [diff] [blame] | 1722 | }; |
| 1723 | |
Kuninori Morimoto | 7fd6e11 | 2015-07-21 00:27:24 +0000 | [diff] [blame] | 1724 | rcar_sound,mix { |
| 1725 | mix0: mix@0 { }; |
| 1726 | mix1: mix@1 { }; |
| 1727 | }; |
| 1728 | |
Kuninori Morimoto | 8840170 | 2015-07-21 00:27:03 +0000 | [diff] [blame] | 1729 | rcar_sound,ctu { |
| 1730 | ctu00: ctu@0 { }; |
| 1731 | ctu01: ctu@1 { }; |
| 1732 | ctu02: ctu@2 { }; |
| 1733 | ctu03: ctu@3 { }; |
| 1734 | ctu10: ctu@4 { }; |
| 1735 | ctu11: ctu@5 { }; |
| 1736 | ctu12: ctu@6 { }; |
| 1737 | ctu13: ctu@7 { }; |
| 1738 | }; |
| 1739 | |
Kuninori Morimoto | 09abd1f | 2014-06-11 21:44:26 -0700 | [diff] [blame] | 1740 | rcar_sound,src { |
Kuninori Morimoto | 6357333 | 2015-03-10 01:40:27 +0000 | [diff] [blame] | 1741 | src0: src@0 { |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1742 | interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 6357333 | 2015-03-10 01:40:27 +0000 | [diff] [blame] | 1743 | dmas = <&audma0 0x85>, <&audma1 0x9a>; |
| 1744 | dma-names = "rx", "tx"; |
| 1745 | }; |
| 1746 | src1: src@1 { |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1747 | interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 6357333 | 2015-03-10 01:40:27 +0000 | [diff] [blame] | 1748 | dmas = <&audma0 0x87>, <&audma1 0x9c>; |
| 1749 | dma-names = "rx", "tx"; |
| 1750 | }; |
| 1751 | src2: src@2 { |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1752 | interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 6357333 | 2015-03-10 01:40:27 +0000 | [diff] [blame] | 1753 | dmas = <&audma0 0x89>, <&audma1 0x9e>; |
| 1754 | dma-names = "rx", "tx"; |
| 1755 | }; |
| 1756 | src3: src@3 { |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1757 | interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 6357333 | 2015-03-10 01:40:27 +0000 | [diff] [blame] | 1758 | dmas = <&audma0 0x8b>, <&audma1 0xa0>; |
| 1759 | dma-names = "rx", "tx"; |
| 1760 | }; |
| 1761 | src4: src@4 { |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1762 | interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 6357333 | 2015-03-10 01:40:27 +0000 | [diff] [blame] | 1763 | dmas = <&audma0 0x8d>, <&audma1 0xb0>; |
| 1764 | dma-names = "rx", "tx"; |
| 1765 | }; |
| 1766 | src5: src@5 { |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1767 | interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 6357333 | 2015-03-10 01:40:27 +0000 | [diff] [blame] | 1768 | dmas = <&audma0 0x8f>, <&audma1 0xb2>; |
| 1769 | dma-names = "rx", "tx"; |
| 1770 | }; |
| 1771 | src6: src@6 { |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1772 | interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 6357333 | 2015-03-10 01:40:27 +0000 | [diff] [blame] | 1773 | dmas = <&audma0 0x91>, <&audma1 0xb4>; |
| 1774 | dma-names = "rx", "tx"; |
| 1775 | }; |
| 1776 | src7: src@7 { |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1777 | interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 6357333 | 2015-03-10 01:40:27 +0000 | [diff] [blame] | 1778 | dmas = <&audma0 0x93>, <&audma1 0xb6>; |
| 1779 | dma-names = "rx", "tx"; |
| 1780 | }; |
| 1781 | src8: src@8 { |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1782 | interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 6357333 | 2015-03-10 01:40:27 +0000 | [diff] [blame] | 1783 | dmas = <&audma0 0x95>, <&audma1 0xb8>; |
| 1784 | dma-names = "rx", "tx"; |
| 1785 | }; |
| 1786 | src9: src@9 { |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1787 | interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 6357333 | 2015-03-10 01:40:27 +0000 | [diff] [blame] | 1788 | dmas = <&audma0 0x97>, <&audma1 0xba>; |
| 1789 | dma-names = "rx", "tx"; |
| 1790 | }; |
Kuninori Morimoto | 09abd1f | 2014-06-11 21:44:26 -0700 | [diff] [blame] | 1791 | }; |
| 1792 | |
| 1793 | rcar_sound,ssi { |
Kuninori Morimoto | 6357333 | 2015-03-10 01:40:27 +0000 | [diff] [blame] | 1794 | ssi0: ssi@0 { |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1795 | interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 6357333 | 2015-03-10 01:40:27 +0000 | [diff] [blame] | 1796 | dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; |
| 1797 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1798 | }; |
| 1799 | ssi1: ssi@1 { |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1800 | interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 6357333 | 2015-03-10 01:40:27 +0000 | [diff] [blame] | 1801 | dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; |
| 1802 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1803 | }; |
| 1804 | ssi2: ssi@2 { |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1805 | interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 6357333 | 2015-03-10 01:40:27 +0000 | [diff] [blame] | 1806 | dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; |
| 1807 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1808 | }; |
| 1809 | ssi3: ssi@3 { |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1810 | interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 6357333 | 2015-03-10 01:40:27 +0000 | [diff] [blame] | 1811 | dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; |
| 1812 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1813 | }; |
| 1814 | ssi4: ssi@4 { |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1815 | interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 6357333 | 2015-03-10 01:40:27 +0000 | [diff] [blame] | 1816 | dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; |
| 1817 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1818 | }; |
| 1819 | ssi5: ssi@5 { |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1820 | interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 6357333 | 2015-03-10 01:40:27 +0000 | [diff] [blame] | 1821 | dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; |
| 1822 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1823 | }; |
| 1824 | ssi6: ssi@6 { |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1825 | interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 6357333 | 2015-03-10 01:40:27 +0000 | [diff] [blame] | 1826 | dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; |
| 1827 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1828 | }; |
| 1829 | ssi7: ssi@7 { |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1830 | interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 6357333 | 2015-03-10 01:40:27 +0000 | [diff] [blame] | 1831 | dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; |
| 1832 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1833 | }; |
| 1834 | ssi8: ssi@8 { |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1835 | interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 6357333 | 2015-03-10 01:40:27 +0000 | [diff] [blame] | 1836 | dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; |
| 1837 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1838 | }; |
| 1839 | ssi9: ssi@9 { |
Simon Horman | 386a929 | 2016-01-15 11:44:16 +0900 | [diff] [blame] | 1840 | interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; |
Kuninori Morimoto | 6357333 | 2015-03-10 01:40:27 +0000 | [diff] [blame] | 1841 | dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; |
| 1842 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1843 | }; |
Kuninori Morimoto | 09abd1f | 2014-06-11 21:44:26 -0700 | [diff] [blame] | 1844 | }; |
| 1845 | }; |
Hisashi Nakamura | 0d0771ab | 2013-09-04 12:45:57 +0900 | [diff] [blame] | 1846 | }; |