Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 1 | /* |
Thadeu Lima de Souza Cascardo | 6c504d4 | 2010-01-17 11:23:14 +0000 | [diff] [blame] | 2 | * Low level TLB miss handlers for Book3E |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2008-2009 |
| 5 | * Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License |
| 9 | * as published by the Free Software Foundation; either version |
| 10 | * 2 of the License, or (at your option) any later version. |
| 11 | */ |
| 12 | |
| 13 | #include <asm/processor.h> |
| 14 | #include <asm/reg.h> |
| 15 | #include <asm/page.h> |
| 16 | #include <asm/mmu.h> |
| 17 | #include <asm/ppc_asm.h> |
| 18 | #include <asm/asm-offsets.h> |
| 19 | #include <asm/cputable.h> |
| 20 | #include <asm/pgtable.h> |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 21 | #include <asm/exception-64e.h> |
| 22 | #include <asm/ppc-opcode.h> |
Mihai Caraman | fecff0f | 2012-08-06 03:27:05 +0000 | [diff] [blame] | 23 | #include <asm/kvm_asm.h> |
| 24 | #include <asm/kvm_booke_hv_asm.h> |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 25 | |
| 26 | #ifdef CONFIG_PPC_64K_PAGES |
| 27 | #define VPTE_PMD_SHIFT (PTE_INDEX_SIZE+1) |
| 28 | #else |
| 29 | #define VPTE_PMD_SHIFT (PTE_INDEX_SIZE) |
| 30 | #endif |
| 31 | #define VPTE_PUD_SHIFT (VPTE_PMD_SHIFT + PMD_INDEX_SIZE) |
| 32 | #define VPTE_PGD_SHIFT (VPTE_PUD_SHIFT + PUD_INDEX_SIZE) |
| 33 | #define VPTE_INDEX_SIZE (VPTE_PGD_SHIFT + PGD_INDEX_SIZE) |
| 34 | |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 35 | /********************************************************************** |
| 36 | * * |
| 37 | * TLB miss handling for Book3E with a bolted linear mapping * |
| 38 | * No virtual page table, no nested TLB misses * |
| 39 | * * |
| 40 | **********************************************************************/ |
| 41 | |
Scott Wood | a3dc620 | 2014-03-10 17:29:38 -0500 | [diff] [blame] | 42 | /* |
| 43 | * Note that, unlike non-bolted handlers, TLB_EXFRAME is not |
| 44 | * modified by the TLB miss handlers themselves, since the TLB miss |
| 45 | * handler code will not itself cause a recursive TLB miss. |
| 46 | * |
| 47 | * TLB_EXFRAME will be modified when crit/mc/debug exceptions are |
| 48 | * entered/exited. |
| 49 | */ |
Mihai Caraman | fecff0f | 2012-08-06 03:27:05 +0000 | [diff] [blame] | 50 | .macro tlb_prolog_bolted intnum addr |
Scott Wood | a3dc620 | 2014-03-10 17:29:38 -0500 | [diff] [blame] | 51 | mtspr SPRN_SPRG_GEN_SCRATCH,r12 |
| 52 | mfspr r12,SPRN_SPRG_TLB_EXFRAME |
| 53 | std r13,EX_TLB_R13(r12) |
| 54 | std r10,EX_TLB_R10(r12) |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 55 | mfspr r13,SPRN_SPRG_PACA |
Scott Wood | a3dc620 | 2014-03-10 17:29:38 -0500 | [diff] [blame] | 56 | |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 57 | mfcr r10 |
Scott Wood | a3dc620 | 2014-03-10 17:29:38 -0500 | [diff] [blame] | 58 | std r11,EX_TLB_R11(r12) |
Mihai Caraman | fecff0f | 2012-08-06 03:27:05 +0000 | [diff] [blame] | 59 | #ifdef CONFIG_KVM_BOOKE_HV |
| 60 | BEGIN_FTR_SECTION |
| 61 | mfspr r11, SPRN_SRR1 |
| 62 | END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) |
| 63 | #endif |
| 64 | DO_KVM \intnum, SPRN_SRR1 |
Scott Wood | a3dc620 | 2014-03-10 17:29:38 -0500 | [diff] [blame] | 65 | std r16,EX_TLB_R16(r12) |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 66 | mfspr r16,\addr /* get faulting address */ |
Scott Wood | a3dc620 | 2014-03-10 17:29:38 -0500 | [diff] [blame] | 67 | std r14,EX_TLB_R14(r12) |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 68 | ld r14,PACAPGD(r13) |
Scott Wood | a3dc620 | 2014-03-10 17:29:38 -0500 | [diff] [blame] | 69 | std r15,EX_TLB_R15(r12) |
| 70 | std r10,EX_TLB_CR(r12) |
| 71 | TLB_MISS_PROLOG_STATS |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 72 | .endm |
| 73 | |
| 74 | .macro tlb_epilog_bolted |
Scott Wood | a3dc620 | 2014-03-10 17:29:38 -0500 | [diff] [blame] | 75 | ld r14,EX_TLB_CR(r12) |
| 76 | ld r10,EX_TLB_R10(r12) |
| 77 | ld r11,EX_TLB_R11(r12) |
| 78 | ld r13,EX_TLB_R13(r12) |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 79 | mtcr r14 |
Scott Wood | a3dc620 | 2014-03-10 17:29:38 -0500 | [diff] [blame] | 80 | ld r14,EX_TLB_R14(r12) |
| 81 | ld r15,EX_TLB_R15(r12) |
| 82 | TLB_MISS_RESTORE_STATS |
| 83 | ld r16,EX_TLB_R16(r12) |
| 84 | mfspr r12,SPRN_SPRG_GEN_SCRATCH |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 85 | .endm |
| 86 | |
| 87 | /* Data TLB miss */ |
| 88 | START_EXCEPTION(data_tlb_miss_bolted) |
Mihai Caraman | fecff0f | 2012-08-06 03:27:05 +0000 | [diff] [blame] | 89 | tlb_prolog_bolted BOOKE_INTERRUPT_DTLB_MISS SPRN_DEAR |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 90 | |
| 91 | /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */ |
| 92 | |
| 93 | /* We do the user/kernel test for the PID here along with the RW test |
| 94 | */ |
| 95 | /* We pre-test some combination of permissions to avoid double |
| 96 | * faults: |
| 97 | * |
| 98 | * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE |
| 99 | * ESR_ST is 0x00800000 |
| 100 | * _PAGE_BAP_SW is 0x00000010 |
| 101 | * So the shift is >> 19. This tests for supervisor writeability. |
| 102 | * If the page happens to be supervisor writeable and not user |
| 103 | * writeable, we will take a new fault later, but that should be |
| 104 | * a rare enough case. |
| 105 | * |
| 106 | * We also move ESR_ST in _PAGE_DIRTY position |
| 107 | * _PAGE_DIRTY is 0x00001000 so the shift is >> 11 |
| 108 | * |
| 109 | * MAS1 is preset for all we need except for TID that needs to |
| 110 | * be cleared for kernel translations |
| 111 | */ |
| 112 | |
| 113 | mfspr r11,SPRN_ESR |
| 114 | |
| 115 | srdi r15,r16,60 /* get region */ |
| 116 | rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4 |
Becky Bruce | 27609a4 | 2011-10-10 10:50:41 +0000 | [diff] [blame] | 117 | bne- dtlb_miss_fault_bolted /* Bail if fault addr is invalid */ |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 118 | |
| 119 | rlwinm r10,r11,32-19,27,27 |
| 120 | rlwimi r10,r11,32-16,19,19 |
Becky Bruce | 27609a4 | 2011-10-10 10:50:41 +0000 | [diff] [blame] | 121 | cmpwi r15,0 /* user vs kernel check */ |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 122 | ori r10,r10,_PAGE_PRESENT |
| 123 | oris r11,r10,_PAGE_ACCESSED@h |
| 124 | |
| 125 | TLB_MISS_STATS_SAVE_INFO_BOLTED |
| 126 | bne tlb_miss_kernel_bolted |
| 127 | |
| 128 | tlb_miss_common_bolted: |
| 129 | /* |
| 130 | * This is the guts of the TLB miss handler for bolted-linear. |
| 131 | * We are entered with: |
| 132 | * |
| 133 | * r16 = faulting address |
| 134 | * r15 = crap (free to use) |
| 135 | * r14 = page table base |
| 136 | * r13 = PACA |
| 137 | * r11 = PTE permission mask |
| 138 | * r10 = crap (free to use) |
| 139 | */ |
| 140 | rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3 |
| 141 | cmpldi cr0,r14,0 |
| 142 | clrrdi r15,r15,3 |
Becky Bruce | 27609a4 | 2011-10-10 10:50:41 +0000 | [diff] [blame] | 143 | beq tlb_miss_fault_bolted /* No PGDIR, bail */ |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 144 | |
| 145 | BEGIN_MMU_FTR_SECTION |
| 146 | /* Set the TLB reservation and search for existing entry. Then load |
| 147 | * the entry. |
| 148 | */ |
Michael Neuling | 962cffb | 2012-06-25 13:33:25 +0000 | [diff] [blame] | 149 | PPC_TLBSRX_DOT(0,R16) |
Becky Bruce | 27609a4 | 2011-10-10 10:50:41 +0000 | [diff] [blame] | 150 | ldx r14,r14,r15 /* grab pgd entry */ |
Scott Wood | 1149e8a | 2012-06-12 17:02:32 -0500 | [diff] [blame] | 151 | beq tlb_miss_done_bolted /* tlb exists already, bail */ |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 152 | MMU_FTR_SECTION_ELSE |
Becky Bruce | 27609a4 | 2011-10-10 10:50:41 +0000 | [diff] [blame] | 153 | ldx r14,r14,r15 /* grab pgd entry */ |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 154 | ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV) |
| 155 | |
| 156 | #ifndef CONFIG_PPC_64K_PAGES |
| 157 | rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3 |
| 158 | clrrdi r15,r15,3 |
Becky Bruce | d1b9b12 | 2011-10-10 10:50:42 +0000 | [diff] [blame] | 159 | cmpdi cr0,r14,0 |
| 160 | bge tlb_miss_fault_bolted /* Bad pgd entry or hugepage; bail */ |
Becky Bruce | 27609a4 | 2011-10-10 10:50:41 +0000 | [diff] [blame] | 161 | ldx r14,r14,r15 /* grab pud entry */ |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 162 | #endif /* CONFIG_PPC_64K_PAGES */ |
| 163 | |
| 164 | rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3 |
| 165 | clrrdi r15,r15,3 |
Becky Bruce | d1b9b12 | 2011-10-10 10:50:42 +0000 | [diff] [blame] | 166 | cmpdi cr0,r14,0 |
| 167 | bge tlb_miss_fault_bolted |
Becky Bruce | 27609a4 | 2011-10-10 10:50:41 +0000 | [diff] [blame] | 168 | ldx r14,r14,r15 /* Grab pmd entry */ |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 169 | |
| 170 | rldicl r15,r16,64-PAGE_SHIFT+3,64-PTE_INDEX_SIZE-3 |
| 171 | clrrdi r15,r15,3 |
Becky Bruce | d1b9b12 | 2011-10-10 10:50:42 +0000 | [diff] [blame] | 172 | cmpdi cr0,r14,0 |
| 173 | bge tlb_miss_fault_bolted |
| 174 | ldx r14,r14,r15 /* Grab PTE, normal (!huge) page */ |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 175 | |
| 176 | /* Check if required permissions are met */ |
| 177 | andc. r15,r11,r14 |
| 178 | rldicr r15,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT |
| 179 | bne- tlb_miss_fault_bolted |
| 180 | |
| 181 | /* Now we build the MAS: |
| 182 | * |
| 183 | * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG |
| 184 | * MAS 1 : Almost fully setup |
| 185 | * - PID already updated by caller if necessary |
| 186 | * - TSIZE need change if !base page size, not |
| 187 | * yet implemented for now |
| 188 | * MAS 2 : Defaults not useful, need to be redone |
| 189 | * MAS 3+7 : Needs to be done |
| 190 | */ |
| 191 | clrrdi r11,r16,12 /* Clear low crap in EA */ |
| 192 | clrldi r15,r15,12 /* Clear crap at the top */ |
| 193 | rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */ |
| 194 | rlwimi r15,r14,32-8,22,25 /* Move in U bits */ |
| 195 | mtspr SPRN_MAS2,r11 |
| 196 | andi. r11,r14,_PAGE_DIRTY |
| 197 | rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */ |
| 198 | |
| 199 | /* Mask out SW and UW if !DIRTY (XXX optimize this !) */ |
| 200 | bne 1f |
| 201 | li r11,MAS3_SW|MAS3_UW |
| 202 | andc r15,r15,r11 |
| 203 | 1: |
| 204 | mtspr SPRN_MAS7_MAS3,r15 |
| 205 | tlbwe |
| 206 | |
Scott Wood | 1149e8a | 2012-06-12 17:02:32 -0500 | [diff] [blame] | 207 | tlb_miss_done_bolted: |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 208 | TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK) |
| 209 | tlb_epilog_bolted |
| 210 | rfi |
| 211 | |
| 212 | itlb_miss_kernel_bolted: |
| 213 | li r11,_PAGE_PRESENT|_PAGE_BAP_SX /* Base perm */ |
| 214 | oris r11,r11,_PAGE_ACCESSED@h |
| 215 | tlb_miss_kernel_bolted: |
| 216 | mfspr r10,SPRN_MAS1 |
| 217 | ld r14,PACA_KERNELPGD(r13) |
| 218 | cmpldi cr0,r15,8 /* Check for vmalloc region */ |
| 219 | rlwinm r10,r10,0,16,1 /* Clear TID */ |
| 220 | mtspr SPRN_MAS1,r10 |
| 221 | beq+ tlb_miss_common_bolted |
| 222 | |
| 223 | tlb_miss_fault_bolted: |
| 224 | /* We need to check if it was an instruction miss */ |
| 225 | andi. r10,r11,_PAGE_EXEC|_PAGE_BAP_SX |
| 226 | bne itlb_miss_fault_bolted |
| 227 | dtlb_miss_fault_bolted: |
| 228 | TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT) |
| 229 | tlb_epilog_bolted |
| 230 | b exc_data_storage_book3e |
| 231 | itlb_miss_fault_bolted: |
| 232 | TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT) |
| 233 | tlb_epilog_bolted |
| 234 | b exc_instruction_storage_book3e |
| 235 | |
| 236 | /* Instruction TLB miss */ |
| 237 | START_EXCEPTION(instruction_tlb_miss_bolted) |
Mihai Caraman | fecff0f | 2012-08-06 03:27:05 +0000 | [diff] [blame] | 238 | tlb_prolog_bolted BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR0 |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 239 | |
| 240 | rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4 |
| 241 | srdi r15,r16,60 /* get region */ |
| 242 | TLB_MISS_STATS_SAVE_INFO_BOLTED |
| 243 | bne- itlb_miss_fault_bolted |
| 244 | |
| 245 | li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */ |
| 246 | |
| 247 | /* We do the user/kernel test for the PID here along with the RW test |
| 248 | */ |
| 249 | |
| 250 | cmpldi cr0,r15,0 /* Check for user region */ |
| 251 | oris r11,r11,_PAGE_ACCESSED@h |
| 252 | beq tlb_miss_common_bolted |
| 253 | b itlb_miss_kernel_bolted |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 254 | |
Scott Wood | 9841c79 | 2014-01-17 18:36:38 -0600 | [diff] [blame] | 255 | #ifdef CONFIG_PPC_FSL_BOOK3E |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 256 | /* |
| 257 | * TLB miss handling for e6500 and derivatives, using hardware tablewalk. |
| 258 | * |
| 259 | * Linear mapping is bolted: no virtual page table or nested TLB misses |
| 260 | * Indirect entries in TLB1, hardware loads resulting direct entries |
| 261 | * into TLB0 |
| 262 | * No HES or NV hint on TLB1, so we need to do software round-robin |
| 263 | * No tlbsrx. so we need a spinlock, and we have to deal |
| 264 | * with MAS-damage caused by tlbsx |
| 265 | * 4K pages only |
| 266 | */ |
| 267 | |
| 268 | START_EXCEPTION(instruction_tlb_miss_e6500) |
| 269 | tlb_prolog_bolted BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR0 |
| 270 | |
| 271 | ld r11,PACA_TCD_PTR(r13) |
| 272 | srdi. r15,r16,60 /* get region */ |
| 273 | ori r16,r16,1 |
| 274 | |
| 275 | TLB_MISS_STATS_SAVE_INFO_BOLTED |
| 276 | bne tlb_miss_kernel_e6500 /* user/kernel test */ |
| 277 | |
| 278 | b tlb_miss_common_e6500 |
| 279 | |
| 280 | START_EXCEPTION(data_tlb_miss_e6500) |
| 281 | tlb_prolog_bolted BOOKE_INTERRUPT_DTLB_MISS SPRN_DEAR |
| 282 | |
| 283 | ld r11,PACA_TCD_PTR(r13) |
| 284 | srdi. r15,r16,60 /* get region */ |
| 285 | rldicr r16,r16,0,62 |
| 286 | |
| 287 | TLB_MISS_STATS_SAVE_INFO_BOLTED |
| 288 | bne tlb_miss_kernel_e6500 /* user vs kernel check */ |
| 289 | |
| 290 | /* |
| 291 | * This is the guts of the TLB miss handler for e6500 and derivatives. |
| 292 | * We are entered with: |
| 293 | * |
| 294 | * r16 = page of faulting address (low bit 0 if data, 1 if instruction) |
| 295 | * r15 = crap (free to use) |
| 296 | * r14 = page table base |
| 297 | * r13 = PACA |
| 298 | * r11 = tlb_per_core ptr |
Scott Wood | 82d86de | 2014-03-07 14:48:35 -0600 | [diff] [blame] | 299 | * r10 = cpu number |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 300 | */ |
| 301 | tlb_miss_common_e6500: |
| 302 | /* |
| 303 | * Search if we already have an indirect entry for that virtual |
| 304 | * address, and if we do, bail out. |
| 305 | * |
| 306 | * MAS6:IND should be already set based on MAS4 |
| 307 | */ |
Scott Wood | 82d86de | 2014-03-07 14:48:35 -0600 | [diff] [blame] | 308 | 1: lbarx r15,0,r11 |
| 309 | lhz r10,PACAPACAINDEX(r13) |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 310 | cmpdi r15,0 |
Scott Wood | 82d86de | 2014-03-07 14:48:35 -0600 | [diff] [blame] | 311 | cmpdi cr1,r15,1 /* set cr1.eq = 0 for non-recursive */ |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 312 | bne 2f |
Scott Wood | 82d86de | 2014-03-07 14:48:35 -0600 | [diff] [blame] | 313 | stbcx. r10,0,r11 |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 314 | bne 1b |
Scott Wood | 82d86de | 2014-03-07 14:48:35 -0600 | [diff] [blame] | 315 | 3: |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 316 | .subsection 1 |
Scott Wood | 82d86de | 2014-03-07 14:48:35 -0600 | [diff] [blame] | 317 | 2: cmpd cr1,r15,r10 /* recursive lock due to mcheck/crit/etc? */ |
| 318 | beq cr1,3b /* unlock will happen if cr1.eq = 0 */ |
| 319 | lbz r15,0(r11) |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 320 | cmpdi r15,0 |
| 321 | bne 2b |
| 322 | b 1b |
| 323 | .previous |
| 324 | |
Scott Wood | bbd08c7 | 2014-05-19 23:04:55 -0500 | [diff] [blame^] | 325 | mfspr r15,SPRN_MAS1 |
| 326 | mfspr r10,SPRN_MAS2 |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 327 | |
| 328 | tlbsx 0,r16 |
Scott Wood | bbd08c7 | 2014-05-19 23:04:55 -0500 | [diff] [blame^] | 329 | mtspr SPRN_MAS2,r10 |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 330 | mfspr r10,SPRN_MAS1 |
Scott Wood | bbd08c7 | 2014-05-19 23:04:55 -0500 | [diff] [blame^] | 331 | mtspr SPRN_MAS1,r15 |
| 332 | |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 333 | andis. r10,r10,MAS1_VALID@h |
| 334 | bne tlb_miss_done_e6500 |
| 335 | |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 336 | /* Now, we need to walk the page tables. First check if we are in |
| 337 | * range. |
| 338 | */ |
| 339 | rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4 |
| 340 | bne- tlb_miss_fault_e6500 |
| 341 | |
| 342 | rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3 |
| 343 | cmpldi cr0,r14,0 |
| 344 | clrrdi r15,r15,3 |
| 345 | beq- tlb_miss_fault_e6500 /* No PGDIR, bail */ |
| 346 | ldx r14,r14,r15 /* grab pgd entry */ |
| 347 | |
| 348 | rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3 |
| 349 | clrrdi r15,r15,3 |
| 350 | cmpdi cr0,r14,0 |
| 351 | bge tlb_miss_fault_e6500 /* Bad pgd entry or hugepage; bail */ |
| 352 | ldx r14,r14,r15 /* grab pud entry */ |
| 353 | |
| 354 | rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3 |
| 355 | clrrdi r15,r15,3 |
| 356 | cmpdi cr0,r14,0 |
| 357 | bge tlb_miss_fault_e6500 |
| 358 | ldx r14,r14,r15 /* Grab pmd entry */ |
| 359 | |
| 360 | mfspr r10,SPRN_MAS0 |
| 361 | cmpdi cr0,r14,0 |
| 362 | bge tlb_miss_fault_e6500 |
| 363 | |
| 364 | /* Now we build the MAS for a 2M indirect page: |
| 365 | * |
| 366 | * MAS 0 : ESEL needs to be filled by software round-robin |
| 367 | * MAS 1 : Fully set up |
| 368 | * - PID already updated by caller if necessary |
| 369 | * - TSIZE for now is base ind page size always |
| 370 | * - TID already cleared if necessary |
| 371 | * MAS 2 : Default not 2M-aligned, need to be redone |
| 372 | * MAS 3+7 : Needs to be done |
| 373 | */ |
| 374 | |
| 375 | ori r14,r14,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT) |
| 376 | mtspr SPRN_MAS7_MAS3,r14 |
| 377 | |
| 378 | clrrdi r15,r16,21 /* make EA 2M-aligned */ |
| 379 | mtspr SPRN_MAS2,r15 |
| 380 | |
| 381 | lbz r15,TCD_ESEL_NEXT(r11) |
| 382 | lbz r16,TCD_ESEL_MAX(r11) |
| 383 | lbz r14,TCD_ESEL_FIRST(r11) |
| 384 | rlwimi r10,r15,16,0x00ff0000 /* insert esel_next into MAS0 */ |
| 385 | addi r15,r15,1 /* increment esel_next */ |
| 386 | mtspr SPRN_MAS0,r10 |
| 387 | cmpw r15,r16 |
| 388 | iseleq r15,r14,r15 /* if next == last use first */ |
| 389 | stb r15,TCD_ESEL_NEXT(r11) |
| 390 | |
| 391 | tlbwe |
| 392 | |
| 393 | tlb_miss_done_e6500: |
| 394 | .macro tlb_unlock_e6500 |
Scott Wood | 82d86de | 2014-03-07 14:48:35 -0600 | [diff] [blame] | 395 | beq cr1,1f /* no unlock if lock was recursively grabbed */ |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 396 | li r15,0 |
| 397 | isync |
Scott Wood | 82d86de | 2014-03-07 14:48:35 -0600 | [diff] [blame] | 398 | stb r15,0(r11) |
| 399 | 1: |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 400 | .endm |
| 401 | |
| 402 | tlb_unlock_e6500 |
| 403 | TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK) |
| 404 | tlb_epilog_bolted |
| 405 | rfi |
| 406 | |
| 407 | tlb_miss_kernel_e6500: |
| 408 | mfspr r10,SPRN_MAS1 |
| 409 | ld r14,PACA_KERNELPGD(r13) |
| 410 | cmpldi cr0,r15,8 /* Check for vmalloc region */ |
| 411 | rlwinm r10,r10,0,16,1 /* Clear TID */ |
| 412 | mtspr SPRN_MAS1,r10 |
| 413 | beq+ tlb_miss_common_e6500 |
| 414 | |
| 415 | tlb_miss_fault_e6500: |
| 416 | tlb_unlock_e6500 |
| 417 | /* We need to check if it was an instruction miss */ |
| 418 | andi. r16,r16,1 |
| 419 | bne itlb_miss_fault_e6500 |
| 420 | dtlb_miss_fault_e6500: |
| 421 | TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT) |
| 422 | tlb_epilog_bolted |
| 423 | b exc_data_storage_book3e |
| 424 | itlb_miss_fault_e6500: |
| 425 | TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT) |
| 426 | tlb_epilog_bolted |
| 427 | b exc_instruction_storage_book3e |
Scott Wood | 9841c79 | 2014-01-17 18:36:38 -0600 | [diff] [blame] | 428 | #endif /* CONFIG_PPC_FSL_BOOK3E */ |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 429 | |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 430 | /********************************************************************** |
| 431 | * * |
| 432 | * TLB miss handling for Book3E with TLB reservation and HES support * |
| 433 | * * |
| 434 | **********************************************************************/ |
| 435 | |
| 436 | |
| 437 | /* Data TLB miss */ |
| 438 | START_EXCEPTION(data_tlb_miss) |
| 439 | TLB_MISS_PROLOG |
| 440 | |
| 441 | /* Now we handle the fault proper. We only save DEAR in normal |
| 442 | * fault case since that's the only interesting values here. |
| 443 | * We could probably also optimize by not saving SRR0/1 in the |
| 444 | * linear mapping case but I'll leave that for later |
| 445 | */ |
| 446 | mfspr r14,SPRN_ESR |
| 447 | mfspr r16,SPRN_DEAR /* get faulting address */ |
| 448 | srdi r15,r16,60 /* get region */ |
| 449 | cmpldi cr0,r15,0xc /* linear mapping ? */ |
| 450 | TLB_MISS_STATS_SAVE_INFO |
| 451 | beq tlb_load_linear /* yes -> go to linear map load */ |
| 452 | |
| 453 | /* The page tables are mapped virtually linear. At this point, though, |
| 454 | * we don't know whether we are trying to fault in a first level |
| 455 | * virtual address or a virtual page table address. We can get that |
| 456 | * from bit 0x1 of the region ID which we have set for a page table |
| 457 | */ |
| 458 | andi. r10,r15,0x1 |
| 459 | bne- virt_page_table_tlb_miss |
| 460 | |
| 461 | std r14,EX_TLB_ESR(r12); /* save ESR */ |
| 462 | std r16,EX_TLB_DEAR(r12); /* save DEAR */ |
| 463 | |
| 464 | /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */ |
| 465 | li r11,_PAGE_PRESENT |
| 466 | oris r11,r11,_PAGE_ACCESSED@h |
| 467 | |
| 468 | /* We do the user/kernel test for the PID here along with the RW test |
| 469 | */ |
| 470 | cmpldi cr0,r15,0 /* Check for user region */ |
| 471 | |
| 472 | /* We pre-test some combination of permissions to avoid double |
| 473 | * faults: |
| 474 | * |
| 475 | * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE |
| 476 | * ESR_ST is 0x00800000 |
| 477 | * _PAGE_BAP_SW is 0x00000010 |
| 478 | * So the shift is >> 19. This tests for supervisor writeability. |
| 479 | * If the page happens to be supervisor writeable and not user |
| 480 | * writeable, we will take a new fault later, but that should be |
| 481 | * a rare enough case. |
| 482 | * |
| 483 | * We also move ESR_ST in _PAGE_DIRTY position |
| 484 | * _PAGE_DIRTY is 0x00001000 so the shift is >> 11 |
| 485 | * |
| 486 | * MAS1 is preset for all we need except for TID that needs to |
| 487 | * be cleared for kernel translations |
| 488 | */ |
| 489 | rlwimi r11,r14,32-19,27,27 |
| 490 | rlwimi r11,r14,32-16,19,19 |
| 491 | beq normal_tlb_miss |
| 492 | /* XXX replace the RMW cycles with immediate loads + writes */ |
| 493 | 1: mfspr r10,SPRN_MAS1 |
| 494 | cmpldi cr0,r15,8 /* Check for vmalloc region */ |
| 495 | rlwinm r10,r10,0,16,1 /* Clear TID */ |
| 496 | mtspr SPRN_MAS1,r10 |
| 497 | beq+ normal_tlb_miss |
| 498 | |
| 499 | /* We got a crappy address, just fault with whatever DEAR and ESR |
| 500 | * are here |
| 501 | */ |
| 502 | TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT) |
| 503 | TLB_MISS_EPILOG_ERROR |
| 504 | b exc_data_storage_book3e |
| 505 | |
| 506 | /* Instruction TLB miss */ |
| 507 | START_EXCEPTION(instruction_tlb_miss) |
| 508 | TLB_MISS_PROLOG |
| 509 | |
| 510 | /* If we take a recursive fault, the second level handler may need |
| 511 | * to know whether we are handling a data or instruction fault in |
| 512 | * order to get to the right store fault handler. We provide that |
| 513 | * info by writing a crazy value in ESR in our exception frame |
| 514 | */ |
| 515 | li r14,-1 /* store to exception frame is done later */ |
| 516 | |
| 517 | /* Now we handle the fault proper. We only save DEAR in the non |
| 518 | * linear mapping case since we know the linear mapping case will |
| 519 | * not re-enter. We could indeed optimize and also not save SRR0/1 |
| 520 | * in the linear mapping case but I'll leave that for later |
| 521 | * |
| 522 | * Faulting address is SRR0 which is already in r16 |
| 523 | */ |
| 524 | srdi r15,r16,60 /* get region */ |
| 525 | cmpldi cr0,r15,0xc /* linear mapping ? */ |
| 526 | TLB_MISS_STATS_SAVE_INFO |
| 527 | beq tlb_load_linear /* yes -> go to linear map load */ |
| 528 | |
| 529 | /* We do the user/kernel test for the PID here along with the RW test |
| 530 | */ |
Benjamin Herrenschmidt | ea3cc33 | 2009-08-18 19:00:34 +0000 | [diff] [blame] | 531 | li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */ |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 532 | oris r11,r11,_PAGE_ACCESSED@h |
| 533 | |
| 534 | cmpldi cr0,r15,0 /* Check for user region */ |
| 535 | std r14,EX_TLB_ESR(r12) /* write crazy -1 to frame */ |
| 536 | beq normal_tlb_miss |
Kumar Gala | 82ae5ea | 2010-11-17 07:20:32 +0000 | [diff] [blame] | 537 | |
| 538 | li r11,_PAGE_PRESENT|_PAGE_BAP_SX /* Base perm */ |
| 539 | oris r11,r11,_PAGE_ACCESSED@h |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 540 | /* XXX replace the RMW cycles with immediate loads + writes */ |
Kumar Gala | 82ae5ea | 2010-11-17 07:20:32 +0000 | [diff] [blame] | 541 | mfspr r10,SPRN_MAS1 |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 542 | cmpldi cr0,r15,8 /* Check for vmalloc region */ |
| 543 | rlwinm r10,r10,0,16,1 /* Clear TID */ |
| 544 | mtspr SPRN_MAS1,r10 |
| 545 | beq+ normal_tlb_miss |
| 546 | |
| 547 | /* We got a crappy address, just fault */ |
| 548 | TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT) |
| 549 | TLB_MISS_EPILOG_ERROR |
| 550 | b exc_instruction_storage_book3e |
| 551 | |
| 552 | /* |
| 553 | * This is the guts of the first-level TLB miss handler for direct |
| 554 | * misses. We are entered with: |
| 555 | * |
| 556 | * r16 = faulting address |
| 557 | * r15 = region ID |
| 558 | * r14 = crap (free to use) |
| 559 | * r13 = PACA |
| 560 | * r12 = TLB exception frame in PACA |
| 561 | * r11 = PTE permission mask |
| 562 | * r10 = crap (free to use) |
| 563 | */ |
| 564 | normal_tlb_miss: |
| 565 | /* So we first construct the page table address. We do that by |
| 566 | * shifting the bottom of the address (not the region ID) by |
| 567 | * PAGE_SHIFT-3, clearing the bottom 3 bits (get a PTE ptr) and |
| 568 | * or'ing the fourth high bit. |
| 569 | * |
| 570 | * NOTE: For 64K pages, we do things slightly differently in |
| 571 | * order to handle the weird page table format used by linux |
| 572 | */ |
| 573 | ori r10,r15,0x1 |
| 574 | #ifdef CONFIG_PPC_64K_PAGES |
| 575 | /* For the top bits, 16 bytes per PTE */ |
| 576 | rldicl r14,r16,64-(PAGE_SHIFT-4),PAGE_SHIFT-4+4 |
| 577 | /* Now create the bottom bits as 0 in position 0x8000 and |
| 578 | * the rest calculated for 8 bytes per PTE |
| 579 | */ |
| 580 | rldicl r15,r16,64-(PAGE_SHIFT-3),64-15 |
| 581 | /* Insert the bottom bits in */ |
| 582 | rlwimi r14,r15,0,16,31 |
| 583 | #else |
| 584 | rldicl r14,r16,64-(PAGE_SHIFT-3),PAGE_SHIFT-3+4 |
| 585 | #endif |
| 586 | sldi r15,r10,60 |
| 587 | clrrdi r14,r14,3 |
| 588 | or r10,r15,r14 |
| 589 | |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 590 | BEGIN_MMU_FTR_SECTION |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 591 | /* Set the TLB reservation and search for existing entry. Then load |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 592 | * the entry. |
| 593 | */ |
Michael Neuling | 962cffb | 2012-06-25 13:33:25 +0000 | [diff] [blame] | 594 | PPC_TLBSRX_DOT(0,R16) |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 595 | ld r14,0(r10) |
| 596 | beq normal_tlb_miss_done |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 597 | MMU_FTR_SECTION_ELSE |
| 598 | ld r14,0(r10) |
| 599 | ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV) |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 600 | |
| 601 | finish_normal_tlb_miss: |
| 602 | /* Check if required permissions are met */ |
| 603 | andc. r15,r11,r14 |
| 604 | bne- normal_tlb_miss_access_fault |
| 605 | |
| 606 | /* Now we build the MAS: |
| 607 | * |
| 608 | * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG |
| 609 | * MAS 1 : Almost fully setup |
| 610 | * - PID already updated by caller if necessary |
| 611 | * - TSIZE need change if !base page size, not |
| 612 | * yet implemented for now |
| 613 | * MAS 2 : Defaults not useful, need to be redone |
| 614 | * MAS 3+7 : Needs to be done |
| 615 | * |
| 616 | * TODO: mix up code below for better scheduling |
| 617 | */ |
| 618 | clrrdi r11,r16,12 /* Clear low crap in EA */ |
| 619 | rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */ |
| 620 | mtspr SPRN_MAS2,r11 |
| 621 | |
| 622 | /* Check page size, if not standard, update MAS1 */ |
| 623 | rldicl r11,r14,64-8,64-8 |
| 624 | #ifdef CONFIG_PPC_64K_PAGES |
| 625 | cmpldi cr0,r11,BOOK3E_PAGESZ_64K |
| 626 | #else |
| 627 | cmpldi cr0,r11,BOOK3E_PAGESZ_4K |
| 628 | #endif |
| 629 | beq- 1f |
| 630 | mfspr r11,SPRN_MAS1 |
| 631 | rlwimi r11,r14,31,21,24 |
| 632 | rlwinm r11,r11,0,21,19 |
| 633 | mtspr SPRN_MAS1,r11 |
| 634 | 1: |
| 635 | /* Move RPN in position */ |
| 636 | rldicr r11,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT |
| 637 | clrldi r15,r11,12 /* Clear crap at the top */ |
| 638 | rlwimi r15,r14,32-8,22,25 /* Move in U bits */ |
| 639 | rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */ |
| 640 | |
| 641 | /* Mask out SW and UW if !DIRTY (XXX optimize this !) */ |
| 642 | andi. r11,r14,_PAGE_DIRTY |
| 643 | bne 1f |
| 644 | li r11,MAS3_SW|MAS3_UW |
| 645 | andc r15,r15,r11 |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 646 | 1: |
| 647 | BEGIN_MMU_FTR_SECTION |
| 648 | srdi r16,r15,32 |
| 649 | mtspr SPRN_MAS3,r15 |
| 650 | mtspr SPRN_MAS7,r16 |
| 651 | MMU_FTR_SECTION_ELSE |
| 652 | mtspr SPRN_MAS7_MAS3,r15 |
| 653 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS) |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 654 | |
| 655 | tlbwe |
| 656 | |
| 657 | normal_tlb_miss_done: |
| 658 | /* We don't bother with restoring DEAR or ESR since we know we are |
| 659 | * level 0 and just going back to userland. They are only needed |
| 660 | * if you are going to take an access fault |
| 661 | */ |
| 662 | TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK) |
| 663 | TLB_MISS_EPILOG_SUCCESS |
| 664 | rfi |
| 665 | |
| 666 | normal_tlb_miss_access_fault: |
| 667 | /* We need to check if it was an instruction miss */ |
Benjamin Herrenschmidt | ea3cc33 | 2009-08-18 19:00:34 +0000 | [diff] [blame] | 668 | andi. r10,r11,_PAGE_EXEC |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 669 | bne 1f |
| 670 | ld r14,EX_TLB_DEAR(r12) |
| 671 | ld r15,EX_TLB_ESR(r12) |
| 672 | mtspr SPRN_DEAR,r14 |
| 673 | mtspr SPRN_ESR,r15 |
| 674 | TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT) |
| 675 | TLB_MISS_EPILOG_ERROR |
| 676 | b exc_data_storage_book3e |
| 677 | 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT) |
| 678 | TLB_MISS_EPILOG_ERROR |
| 679 | b exc_instruction_storage_book3e |
| 680 | |
| 681 | |
| 682 | /* |
| 683 | * This is the guts of the second-level TLB miss handler for direct |
| 684 | * misses. We are entered with: |
| 685 | * |
| 686 | * r16 = virtual page table faulting address |
| 687 | * r15 = region (top 4 bits of address) |
| 688 | * r14 = crap (free to use) |
| 689 | * r13 = PACA |
| 690 | * r12 = TLB exception frame in PACA |
| 691 | * r11 = crap (free to use) |
| 692 | * r10 = crap (free to use) |
| 693 | * |
| 694 | * Note that this should only ever be called as a second level handler |
| 695 | * with the current scheme when using SW load. |
| 696 | * That means we can always get the original fault DEAR at |
| 697 | * EX_TLB_DEAR-EX_TLB_SIZE(r12) |
| 698 | * |
| 699 | * It can be re-entered by the linear mapping miss handler. However, to |
| 700 | * avoid too much complication, it will restart the whole fault at level |
| 701 | * 0 so we don't care too much about clobbers |
| 702 | * |
| 703 | * XXX That code was written back when we couldn't clobber r14. We can now, |
| 704 | * so we could probably optimize things a bit |
| 705 | */ |
| 706 | virt_page_table_tlb_miss: |
| 707 | /* Are we hitting a kernel page table ? */ |
| 708 | andi. r10,r15,0x8 |
| 709 | |
| 710 | /* The cool thing now is that r10 contains 0 for user and 8 for kernel, |
| 711 | * and we happen to have the swapper_pg_dir at offset 8 from the user |
| 712 | * pgdir in the PACA :-). |
| 713 | */ |
| 714 | add r11,r10,r13 |
| 715 | |
| 716 | /* If kernel, we need to clear MAS1 TID */ |
| 717 | beq 1f |
| 718 | /* XXX replace the RMW cycles with immediate loads + writes */ |
| 719 | mfspr r10,SPRN_MAS1 |
| 720 | rlwinm r10,r10,0,16,1 /* Clear TID */ |
| 721 | mtspr SPRN_MAS1,r10 |
| 722 | 1: |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 723 | BEGIN_MMU_FTR_SECTION |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 724 | /* Search if we already have a TLB entry for that virtual address, and |
| 725 | * if we do, bail out. |
| 726 | */ |
Michael Neuling | 962cffb | 2012-06-25 13:33:25 +0000 | [diff] [blame] | 727 | PPC_TLBSRX_DOT(0,R16) |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 728 | beq virt_page_table_tlb_miss_done |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 729 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV) |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 730 | |
| 731 | /* Now, we need to walk the page tables. First check if we are in |
| 732 | * range. |
| 733 | */ |
| 734 | rldicl. r10,r16,64-(VPTE_INDEX_SIZE+3),VPTE_INDEX_SIZE+3+4 |
| 735 | bne- virt_page_table_tlb_miss_fault |
| 736 | |
| 737 | /* Get the PGD pointer */ |
| 738 | ld r15,PACAPGD(r11) |
| 739 | cmpldi cr0,r15,0 |
| 740 | beq- virt_page_table_tlb_miss_fault |
| 741 | |
| 742 | /* Get to PGD entry */ |
| 743 | rldicl r11,r16,64-VPTE_PGD_SHIFT,64-PGD_INDEX_SIZE-3 |
| 744 | clrrdi r10,r11,3 |
| 745 | ldx r15,r10,r15 |
Becky Bruce | 41151e7 | 2011-06-28 09:54:48 +0000 | [diff] [blame] | 746 | cmpdi cr0,r15,0 |
| 747 | bge virt_page_table_tlb_miss_fault |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 748 | |
| 749 | #ifndef CONFIG_PPC_64K_PAGES |
| 750 | /* Get to PUD entry */ |
| 751 | rldicl r11,r16,64-VPTE_PUD_SHIFT,64-PUD_INDEX_SIZE-3 |
| 752 | clrrdi r10,r11,3 |
| 753 | ldx r15,r10,r15 |
Becky Bruce | 41151e7 | 2011-06-28 09:54:48 +0000 | [diff] [blame] | 754 | cmpdi cr0,r15,0 |
| 755 | bge virt_page_table_tlb_miss_fault |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 756 | #endif /* CONFIG_PPC_64K_PAGES */ |
| 757 | |
| 758 | /* Get to PMD entry */ |
| 759 | rldicl r11,r16,64-VPTE_PMD_SHIFT,64-PMD_INDEX_SIZE-3 |
| 760 | clrrdi r10,r11,3 |
| 761 | ldx r15,r10,r15 |
Becky Bruce | 41151e7 | 2011-06-28 09:54:48 +0000 | [diff] [blame] | 762 | cmpdi cr0,r15,0 |
| 763 | bge virt_page_table_tlb_miss_fault |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 764 | |
| 765 | /* Ok, we're all right, we can now create a kernel translation for |
| 766 | * a 4K or 64K page from r16 -> r15. |
| 767 | */ |
| 768 | /* Now we build the MAS: |
| 769 | * |
| 770 | * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG |
| 771 | * MAS 1 : Almost fully setup |
| 772 | * - PID already updated by caller if necessary |
| 773 | * - TSIZE for now is base page size always |
| 774 | * MAS 2 : Use defaults |
| 775 | * MAS 3+7 : Needs to be done |
| 776 | * |
| 777 | * So we only do MAS 2 and 3 for now... |
| 778 | */ |
| 779 | clrldi r11,r15,4 /* remove region ID from RPN */ |
| 780 | ori r10,r11,1 /* Or-in SR */ |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 781 | |
| 782 | BEGIN_MMU_FTR_SECTION |
| 783 | srdi r16,r10,32 |
| 784 | mtspr SPRN_MAS3,r10 |
| 785 | mtspr SPRN_MAS7,r16 |
| 786 | MMU_FTR_SECTION_ELSE |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 787 | mtspr SPRN_MAS7_MAS3,r10 |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 788 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS) |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 789 | |
| 790 | tlbwe |
| 791 | |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 792 | BEGIN_MMU_FTR_SECTION |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 793 | virt_page_table_tlb_miss_done: |
| 794 | |
| 795 | /* We have overriden MAS2:EPN but currently our primary TLB miss |
| 796 | * handler will always restore it so that should not be an issue, |
| 797 | * if we ever optimize the primary handler to not write MAS2 on |
| 798 | * some cases, we'll have to restore MAS2:EPN here based on the |
| 799 | * original fault's DEAR. If we do that we have to modify the |
| 800 | * ITLB miss handler to also store SRR0 in the exception frame |
| 801 | * as DEAR. |
| 802 | * |
| 803 | * However, one nasty thing we did is we cleared the reservation |
| 804 | * (well, potentially we did). We do a trick here thus if we |
| 805 | * are not a level 0 exception (we interrupted the TLB miss) we |
| 806 | * offset the return address by -4 in order to replay the tlbsrx |
| 807 | * instruction there |
| 808 | */ |
| 809 | subf r10,r13,r12 |
| 810 | cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE |
| 811 | bne- 1f |
| 812 | ld r11,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13) |
| 813 | addi r10,r11,-4 |
| 814 | std r10,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13) |
| 815 | 1: |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 816 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV) |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 817 | /* Return to caller, normal case */ |
| 818 | TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK); |
| 819 | TLB_MISS_EPILOG_SUCCESS |
| 820 | rfi |
| 821 | |
| 822 | virt_page_table_tlb_miss_fault: |
| 823 | /* If we fault here, things are a little bit tricky. We need to call |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 824 | * either data or instruction store fault, and we need to retrieve |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 825 | * the original fault address and ESR (for data). |
| 826 | * |
| 827 | * The thing is, we know that in normal circumstances, this is |
| 828 | * always called as a second level tlb miss for SW load or as a first |
| 829 | * level TLB miss for HW load, so we should be able to peek at the |
Sylvestre Ledru | f65e51d | 2011-04-04 15:04:46 -0700 | [diff] [blame] | 830 | * relevant information in the first exception frame in the PACA. |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 831 | * |
| 832 | * However, we do need to double check that, because we may just hit |
| 833 | * a stray kernel pointer or a userland attack trying to hit those |
| 834 | * areas. If that is the case, we do a data fault. (We can't get here |
| 835 | * from an instruction tlb miss anyway). |
| 836 | * |
| 837 | * Note also that when going to a fault, we must unwind the previous |
| 838 | * level as well. Since we are doing that, we don't need to clear or |
| 839 | * restore the TLB reservation neither. |
| 840 | */ |
| 841 | subf r10,r13,r12 |
| 842 | cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE |
| 843 | bne- virt_page_table_tlb_miss_whacko_fault |
| 844 | |
| 845 | /* We dig the original DEAR and ESR from slot 0 */ |
| 846 | ld r15,EX_TLB_DEAR+PACA_EXTLB(r13) |
| 847 | ld r16,EX_TLB_ESR+PACA_EXTLB(r13) |
| 848 | |
| 849 | /* We check for the "special" ESR value for instruction faults */ |
| 850 | cmpdi cr0,r16,-1 |
| 851 | beq 1f |
| 852 | mtspr SPRN_DEAR,r15 |
| 853 | mtspr SPRN_ESR,r16 |
| 854 | TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT); |
| 855 | TLB_MISS_EPILOG_ERROR |
| 856 | b exc_data_storage_book3e |
| 857 | 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT); |
| 858 | TLB_MISS_EPILOG_ERROR |
| 859 | b exc_instruction_storage_book3e |
| 860 | |
| 861 | virt_page_table_tlb_miss_whacko_fault: |
| 862 | /* The linear fault will restart everything so ESR and DEAR will |
| 863 | * not have been clobbered, let's just fault with what we have |
| 864 | */ |
| 865 | TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_FAULT); |
| 866 | TLB_MISS_EPILOG_ERROR |
| 867 | b exc_data_storage_book3e |
| 868 | |
| 869 | |
| 870 | /************************************************************** |
| 871 | * * |
| 872 | * TLB miss handling for Book3E with hw page table support * |
| 873 | * * |
| 874 | **************************************************************/ |
| 875 | |
| 876 | |
| 877 | /* Data TLB miss */ |
| 878 | START_EXCEPTION(data_tlb_miss_htw) |
| 879 | TLB_MISS_PROLOG |
| 880 | |
| 881 | /* Now we handle the fault proper. We only save DEAR in normal |
| 882 | * fault case since that's the only interesting values here. |
| 883 | * We could probably also optimize by not saving SRR0/1 in the |
| 884 | * linear mapping case but I'll leave that for later |
| 885 | */ |
| 886 | mfspr r14,SPRN_ESR |
| 887 | mfspr r16,SPRN_DEAR /* get faulting address */ |
| 888 | srdi r11,r16,60 /* get region */ |
| 889 | cmpldi cr0,r11,0xc /* linear mapping ? */ |
| 890 | TLB_MISS_STATS_SAVE_INFO |
| 891 | beq tlb_load_linear /* yes -> go to linear map load */ |
| 892 | |
| 893 | /* We do the user/kernel test for the PID here along with the RW test |
| 894 | */ |
| 895 | cmpldi cr0,r11,0 /* Check for user region */ |
| 896 | ld r15,PACAPGD(r13) /* Load user pgdir */ |
| 897 | beq htw_tlb_miss |
| 898 | |
| 899 | /* XXX replace the RMW cycles with immediate loads + writes */ |
| 900 | 1: mfspr r10,SPRN_MAS1 |
| 901 | cmpldi cr0,r11,8 /* Check for vmalloc region */ |
| 902 | rlwinm r10,r10,0,16,1 /* Clear TID */ |
| 903 | mtspr SPRN_MAS1,r10 |
| 904 | ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */ |
| 905 | beq+ htw_tlb_miss |
| 906 | |
| 907 | /* We got a crappy address, just fault with whatever DEAR and ESR |
| 908 | * are here |
| 909 | */ |
| 910 | TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT) |
| 911 | TLB_MISS_EPILOG_ERROR |
| 912 | b exc_data_storage_book3e |
| 913 | |
| 914 | /* Instruction TLB miss */ |
| 915 | START_EXCEPTION(instruction_tlb_miss_htw) |
| 916 | TLB_MISS_PROLOG |
| 917 | |
| 918 | /* If we take a recursive fault, the second level handler may need |
| 919 | * to know whether we are handling a data or instruction fault in |
| 920 | * order to get to the right store fault handler. We provide that |
| 921 | * info by keeping a crazy value for ESR in r14 |
| 922 | */ |
| 923 | li r14,-1 /* store to exception frame is done later */ |
| 924 | |
| 925 | /* Now we handle the fault proper. We only save DEAR in the non |
| 926 | * linear mapping case since we know the linear mapping case will |
| 927 | * not re-enter. We could indeed optimize and also not save SRR0/1 |
| 928 | * in the linear mapping case but I'll leave that for later |
| 929 | * |
| 930 | * Faulting address is SRR0 which is already in r16 |
| 931 | */ |
| 932 | srdi r11,r16,60 /* get region */ |
| 933 | cmpldi cr0,r11,0xc /* linear mapping ? */ |
| 934 | TLB_MISS_STATS_SAVE_INFO |
| 935 | beq tlb_load_linear /* yes -> go to linear map load */ |
| 936 | |
| 937 | /* We do the user/kernel test for the PID here along with the RW test |
| 938 | */ |
| 939 | cmpldi cr0,r11,0 /* Check for user region */ |
| 940 | ld r15,PACAPGD(r13) /* Load user pgdir */ |
| 941 | beq htw_tlb_miss |
| 942 | |
| 943 | /* XXX replace the RMW cycles with immediate loads + writes */ |
| 944 | 1: mfspr r10,SPRN_MAS1 |
| 945 | cmpldi cr0,r11,8 /* Check for vmalloc region */ |
| 946 | rlwinm r10,r10,0,16,1 /* Clear TID */ |
| 947 | mtspr SPRN_MAS1,r10 |
| 948 | ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */ |
| 949 | beq+ htw_tlb_miss |
| 950 | |
| 951 | /* We got a crappy address, just fault */ |
| 952 | TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT) |
| 953 | TLB_MISS_EPILOG_ERROR |
| 954 | b exc_instruction_storage_book3e |
| 955 | |
| 956 | |
| 957 | /* |
| 958 | * This is the guts of the second-level TLB miss handler for direct |
| 959 | * misses. We are entered with: |
| 960 | * |
| 961 | * r16 = virtual page table faulting address |
| 962 | * r15 = PGD pointer |
| 963 | * r14 = ESR |
| 964 | * r13 = PACA |
| 965 | * r12 = TLB exception frame in PACA |
| 966 | * r11 = crap (free to use) |
| 967 | * r10 = crap (free to use) |
| 968 | * |
| 969 | * It can be re-entered by the linear mapping miss handler. However, to |
| 970 | * avoid too much complication, it will save/restore things for us |
| 971 | */ |
| 972 | htw_tlb_miss: |
| 973 | /* Search if we already have a TLB entry for that virtual address, and |
| 974 | * if we do, bail out. |
| 975 | * |
| 976 | * MAS1:IND should be already set based on MAS4 |
| 977 | */ |
Michael Neuling | 962cffb | 2012-06-25 13:33:25 +0000 | [diff] [blame] | 978 | PPC_TLBSRX_DOT(0,R16) |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 979 | beq htw_tlb_miss_done |
| 980 | |
| 981 | /* Now, we need to walk the page tables. First check if we are in |
| 982 | * range. |
| 983 | */ |
| 984 | rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4 |
| 985 | bne- htw_tlb_miss_fault |
| 986 | |
| 987 | /* Get the PGD pointer */ |
| 988 | cmpldi cr0,r15,0 |
| 989 | beq- htw_tlb_miss_fault |
| 990 | |
| 991 | /* Get to PGD entry */ |
| 992 | rldicl r11,r16,64-(PGDIR_SHIFT-3),64-PGD_INDEX_SIZE-3 |
| 993 | clrrdi r10,r11,3 |
| 994 | ldx r15,r10,r15 |
Becky Bruce | 41151e7 | 2011-06-28 09:54:48 +0000 | [diff] [blame] | 995 | cmpdi cr0,r15,0 |
| 996 | bge htw_tlb_miss_fault |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 997 | |
| 998 | #ifndef CONFIG_PPC_64K_PAGES |
| 999 | /* Get to PUD entry */ |
| 1000 | rldicl r11,r16,64-(PUD_SHIFT-3),64-PUD_INDEX_SIZE-3 |
| 1001 | clrrdi r10,r11,3 |
| 1002 | ldx r15,r10,r15 |
Becky Bruce | 41151e7 | 2011-06-28 09:54:48 +0000 | [diff] [blame] | 1003 | cmpdi cr0,r15,0 |
| 1004 | bge htw_tlb_miss_fault |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 1005 | #endif /* CONFIG_PPC_64K_PAGES */ |
| 1006 | |
| 1007 | /* Get to PMD entry */ |
| 1008 | rldicl r11,r16,64-(PMD_SHIFT-3),64-PMD_INDEX_SIZE-3 |
| 1009 | clrrdi r10,r11,3 |
| 1010 | ldx r15,r10,r15 |
Becky Bruce | 41151e7 | 2011-06-28 09:54:48 +0000 | [diff] [blame] | 1011 | cmpdi cr0,r15,0 |
| 1012 | bge htw_tlb_miss_fault |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 1013 | |
| 1014 | /* Ok, we're all right, we can now create an indirect entry for |
| 1015 | * a 1M or 256M page. |
| 1016 | * |
| 1017 | * The last trick is now that because we use "half" pages for |
| 1018 | * the HTW (1M IND is 2K and 256M IND is 32K) we need to account |
| 1019 | * for an added LSB bit to the RPN. For 64K pages, there is no |
| 1020 | * problem as we already use 32K arrays (half PTE pages), but for |
| 1021 | * 4K page we need to extract a bit from the virtual address and |
| 1022 | * insert it into the "PA52" bit of the RPN. |
| 1023 | */ |
| 1024 | #ifndef CONFIG_PPC_64K_PAGES |
| 1025 | rlwimi r15,r16,32-9,20,20 |
| 1026 | #endif |
| 1027 | /* Now we build the MAS: |
| 1028 | * |
| 1029 | * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG |
| 1030 | * MAS 1 : Almost fully setup |
| 1031 | * - PID already updated by caller if necessary |
| 1032 | * - TSIZE for now is base ind page size always |
| 1033 | * MAS 2 : Use defaults |
| 1034 | * MAS 3+7 : Needs to be done |
| 1035 | */ |
| 1036 | #ifdef CONFIG_PPC_64K_PAGES |
| 1037 | ori r10,r15,(BOOK3E_PAGESZ_64K << MAS3_SPSIZE_SHIFT) |
| 1038 | #else |
| 1039 | ori r10,r15,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT) |
| 1040 | #endif |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 1041 | |
| 1042 | BEGIN_MMU_FTR_SECTION |
| 1043 | srdi r16,r10,32 |
| 1044 | mtspr SPRN_MAS3,r10 |
| 1045 | mtspr SPRN_MAS7,r16 |
| 1046 | MMU_FTR_SECTION_ELSE |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 1047 | mtspr SPRN_MAS7_MAS3,r10 |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 1048 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS) |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 1049 | |
| 1050 | tlbwe |
| 1051 | |
| 1052 | htw_tlb_miss_done: |
| 1053 | /* We don't bother with restoring DEAR or ESR since we know we are |
| 1054 | * level 0 and just going back to userland. They are only needed |
| 1055 | * if you are going to take an access fault |
| 1056 | */ |
| 1057 | TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK) |
| 1058 | TLB_MISS_EPILOG_SUCCESS |
| 1059 | rfi |
| 1060 | |
| 1061 | htw_tlb_miss_fault: |
| 1062 | /* We need to check if it was an instruction miss. We know this |
| 1063 | * though because r14 would contain -1 |
| 1064 | */ |
| 1065 | cmpdi cr0,r14,-1 |
| 1066 | beq 1f |
| 1067 | mtspr SPRN_DEAR,r16 |
| 1068 | mtspr SPRN_ESR,r14 |
| 1069 | TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT) |
| 1070 | TLB_MISS_EPILOG_ERROR |
| 1071 | b exc_data_storage_book3e |
| 1072 | 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT) |
| 1073 | TLB_MISS_EPILOG_ERROR |
| 1074 | b exc_instruction_storage_book3e |
| 1075 | |
| 1076 | /* |
| 1077 | * This is the guts of "any" level TLB miss handler for kernel linear |
| 1078 | * mapping misses. We are entered with: |
| 1079 | * |
| 1080 | * |
| 1081 | * r16 = faulting address |
| 1082 | * r15 = crap (free to use) |
| 1083 | * r14 = ESR (data) or -1 (instruction) |
| 1084 | * r13 = PACA |
| 1085 | * r12 = TLB exception frame in PACA |
| 1086 | * r11 = crap (free to use) |
| 1087 | * r10 = crap (free to use) |
| 1088 | * |
| 1089 | * In addition we know that we will not re-enter, so in theory, we could |
| 1090 | * use a simpler epilog not restoring SRR0/1 etc.. but we'll do that later. |
| 1091 | * |
| 1092 | * We also need to be careful about MAS registers here & TLB reservation, |
| 1093 | * as we know we'll have clobbered them if we interrupt the main TLB miss |
| 1094 | * handlers in which case we probably want to do a full restart at level |
| 1095 | * 0 rather than saving / restoring the MAS. |
| 1096 | * |
| 1097 | * Note: If we care about performance of that core, we can easily shuffle |
| 1098 | * a few things around |
| 1099 | */ |
| 1100 | tlb_load_linear: |
| 1101 | /* For now, we assume the linear mapping is contiguous and stops at |
| 1102 | * linear_map_top. We also assume the size is a multiple of 1G, thus |
| 1103 | * we only use 1G pages for now. That might have to be changed in a |
| 1104 | * final implementation, especially when dealing with hypervisors |
| 1105 | */ |
| 1106 | ld r11,PACATOC(r13) |
| 1107 | ld r11,linear_map_top@got(r11) |
| 1108 | ld r10,0(r11) |
Benjamin Krill | 60b9622 | 2014-02-27 15:49:21 +0100 | [diff] [blame] | 1109 | tovirt(10,10) |
| 1110 | cmpld cr0,r16,r10 |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 1111 | bge tlb_load_linear_fault |
| 1112 | |
| 1113 | /* MAS1 need whole new setup. */ |
| 1114 | li r15,(BOOK3E_PAGESZ_1GB<<MAS1_TSIZE_SHIFT) |
| 1115 | oris r15,r15,MAS1_VALID@h /* MAS1 needs V and TSIZE */ |
| 1116 | mtspr SPRN_MAS1,r15 |
| 1117 | |
| 1118 | /* Already somebody there ? */ |
Michael Neuling | 962cffb | 2012-06-25 13:33:25 +0000 | [diff] [blame] | 1119 | PPC_TLBSRX_DOT(0,R16) |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 1120 | beq tlb_load_linear_done |
| 1121 | |
| 1122 | /* Now we build the remaining MAS. MAS0 and 2 should be fine |
| 1123 | * with their defaults, which leaves us with MAS 3 and 7. The |
| 1124 | * mapping is linear, so we just take the address, clear the |
| 1125 | * region bits, and or in the permission bits which are currently |
| 1126 | * hard wired |
| 1127 | */ |
| 1128 | clrrdi r10,r16,30 /* 1G page index */ |
| 1129 | clrldi r10,r10,4 /* clear region bits */ |
| 1130 | ori r10,r10,MAS3_SR|MAS3_SW|MAS3_SX |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 1131 | |
| 1132 | BEGIN_MMU_FTR_SECTION |
| 1133 | srdi r16,r10,32 |
| 1134 | mtspr SPRN_MAS3,r10 |
| 1135 | mtspr SPRN_MAS7,r16 |
| 1136 | MMU_FTR_SECTION_ELSE |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 1137 | mtspr SPRN_MAS7_MAS3,r10 |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 1138 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS) |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 1139 | |
| 1140 | tlbwe |
| 1141 | |
| 1142 | tlb_load_linear_done: |
| 1143 | /* We use the "error" epilog for success as we do want to |
| 1144 | * restore to the initial faulting context, whatever it was. |
| 1145 | * We do that because we can't resume a fault within a TLB |
| 1146 | * miss handler, due to MAS and TLB reservation being clobbered. |
| 1147 | */ |
| 1148 | TLB_MISS_STATS_X(MMSTAT_TLB_MISS_LINEAR) |
| 1149 | TLB_MISS_EPILOG_ERROR |
| 1150 | rfi |
| 1151 | |
| 1152 | tlb_load_linear_fault: |
| 1153 | /* We keep the DEAR and ESR around, this shouldn't have happened */ |
| 1154 | cmpdi cr0,r14,-1 |
| 1155 | beq 1f |
| 1156 | TLB_MISS_EPILOG_ERROR_SPECIAL |
| 1157 | b exc_data_storage_book3e |
| 1158 | 1: TLB_MISS_EPILOG_ERROR_SPECIAL |
| 1159 | b exc_instruction_storage_book3e |
| 1160 | |
| 1161 | |
| 1162 | #ifdef CONFIG_BOOK3E_MMU_TLB_STATS |
| 1163 | .tlb_stat_inc: |
| 1164 | 1: ldarx r8,0,r9 |
| 1165 | addi r8,r8,1 |
| 1166 | stdcx. r8,0,r9 |
| 1167 | bne- 1b |
| 1168 | blr |
| 1169 | #endif |