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gerrit-public.fairphone.software / kernel / msm-4.9 / bc0d0d093b379b0b379c429e3348498287c8a9ca / . / drivers / pinctrl / intel / pinctrl-sunrisepoint.c
blob: 1de9ae5010db285b53c01d7e67dec2bde7ce5233 [file] [log] [blame]
Mika Westerberg7981c0012015-03-30 17:31:49 +0300[diff] [blame]1/*
2 * Intel Sunrisepoint PCH pinctrl/GPIO driver
3 *
4 * Copyright (C) 2015, Intel Corporation
5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Mika Westerberg <mika.westerberg@linux.intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/acpi.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/pm.h>
17#include <linux/pinctrl/pinctrl.h>
18
19#include "pinctrl-intel.h"
20
21#define SPT_PAD_OWN 0x020
22#define SPT_PADCFGLOCK 0x0a0
23#define SPT_HOSTSW_OWN 0x0d0
24#define SPT_GPI_IE 0x120
25
26#define SPT_COMMUNITY(b, s, e) \
27 { \
28 .barno = (b), \
29 .padown_offset = SPT_PAD_OWN, \
30 .padcfglock_offset = SPT_PADCFGLOCK, \
31 .hostown_offset = SPT_HOSTSW_OWN, \
32 .ie_offset = SPT_GPI_IE, \
33 .pin_base = (s), \
34 .npins = ((e) - (s) + 1), \
35 }
36
37/* Sunrisepoint-LP */
38static const struct pinctrl_pin_desc sptlp_pins[] = {
39 /* GPP_A */
40 PINCTRL_PIN(0, "RCINB"),
41 PINCTRL_PIN(1, "LAD_0"),
42 PINCTRL_PIN(2, "LAD_1"),
43 PINCTRL_PIN(3, "LAD_2"),
44 PINCTRL_PIN(4, "LAD_3"),
45 PINCTRL_PIN(5, "LFRAMEB"),
46 PINCTRL_PIN(6, "SERIQ"),
47 PINCTRL_PIN(7, "PIRQAB"),
48 PINCTRL_PIN(8, "CLKRUNB"),
49 PINCTRL_PIN(9, "CLKOUT_LPC_0"),
50 PINCTRL_PIN(10, "CLKOUT_LPC_1"),
51 PINCTRL_PIN(11, "PMEB"),
52 PINCTRL_PIN(12, "BM_BUSYB"),
53 PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"),
54 PINCTRL_PIN(14, "SUS_STATB"),
55 PINCTRL_PIN(15, "SUSACKB"),
56 PINCTRL_PIN(16, "SD_1P8_SEL"),
57 PINCTRL_PIN(17, "SD_PWR_EN_B"),
58 PINCTRL_PIN(18, "ISH_GP_0"),
59 PINCTRL_PIN(19, "ISH_GP_1"),
60 PINCTRL_PIN(20, "ISH_GP_2"),
61 PINCTRL_PIN(21, "ISH_GP_3"),
62 PINCTRL_PIN(22, "ISH_GP_4"),
63 PINCTRL_PIN(23, "ISH_GP_5"),
64 /* GPP_B */
65 PINCTRL_PIN(24, "CORE_VID_0"),
66 PINCTRL_PIN(25, "CORE_VID_1"),
67 PINCTRL_PIN(26, "VRALERTB"),
68 PINCTRL_PIN(27, "CPU_GP_2"),
69 PINCTRL_PIN(28, "CPU_GP_3"),
70 PINCTRL_PIN(29, "SRCCLKREQB_0"),
71 PINCTRL_PIN(30, "SRCCLKREQB_1"),
72 PINCTRL_PIN(31, "SRCCLKREQB_2"),
73 PINCTRL_PIN(32, "SRCCLKREQB_3"),
74 PINCTRL_PIN(33, "SRCCLKREQB_4"),
75 PINCTRL_PIN(34, "SRCCLKREQB_5"),
76 PINCTRL_PIN(35, "EXT_PWR_GATEB"),
77 PINCTRL_PIN(36, "SLP_S0B"),
78 PINCTRL_PIN(37, "PLTRSTB"),
79 PINCTRL_PIN(38, "SPKR"),
80 PINCTRL_PIN(39, "GSPI0_CSB"),
81 PINCTRL_PIN(40, "GSPI0_CLK"),
82 PINCTRL_PIN(41, "GSPI0_MISO"),
83 PINCTRL_PIN(42, "GSPI0_MOSI"),
84 PINCTRL_PIN(43, "GSPI1_CSB"),
85 PINCTRL_PIN(44, "GSPI1_CLK"),
86 PINCTRL_PIN(45, "GSPI1_MISO"),
87 PINCTRL_PIN(46, "GSPI1_MOSI"),
88 PINCTRL_PIN(47, "SML1ALERTB"),
89 /* GPP_C */
90 PINCTRL_PIN(48, "SMBCLK"),
91 PINCTRL_PIN(49, "SMBDATA"),
92 PINCTRL_PIN(50, "SMBALERTB"),
93 PINCTRL_PIN(51, "SML0CLK"),
94 PINCTRL_PIN(52, "SML0DATA"),
95 PINCTRL_PIN(53, "SML0ALERTB"),
96 PINCTRL_PIN(54, "SML1CLK"),
97 PINCTRL_PIN(55, "SML1DATA"),
98 PINCTRL_PIN(56, "UART0_RXD"),
99 PINCTRL_PIN(57, "UART0_TXD"),
100 PINCTRL_PIN(58, "UART0_RTSB"),
101 PINCTRL_PIN(59, "UART0_CTSB"),
102 PINCTRL_PIN(60, "UART1_RXD"),
103 PINCTRL_PIN(61, "UART1_TXD"),
104 PINCTRL_PIN(62, "UART1_RTSB"),
105 PINCTRL_PIN(63, "UART1_CTSB"),
106 PINCTRL_PIN(64, "I2C0_SDA"),
107 PINCTRL_PIN(65, "I2C0_SCL"),
108 PINCTRL_PIN(66, "I2C1_SDA"),
109 PINCTRL_PIN(67, "I2C1_SCL"),
110 PINCTRL_PIN(68, "UART2_RXD"),
111 PINCTRL_PIN(69, "UART2_TXD"),
112 PINCTRL_PIN(70, "UART2_RTSB"),
113 PINCTRL_PIN(71, "UART2_CTSB"),
114 /* GPP_D */
115 PINCTRL_PIN(72, "SPI1_CSB"),
116 PINCTRL_PIN(73, "SPI1_CLK"),
117 PINCTRL_PIN(74, "SPI1_MISO_IO_1"),
118 PINCTRL_PIN(75, "SPI1_MOSI_IO_0"),
119 PINCTRL_PIN(76, "FLASHTRIG"),
120 PINCTRL_PIN(77, "ISH_I2C0_SDA"),
121 PINCTRL_PIN(78, "ISH_I2C0_SCL"),
122 PINCTRL_PIN(79, "ISH_I2C1_SDA"),
123 PINCTRL_PIN(80, "ISH_I2C1_SCL"),
124 PINCTRL_PIN(81, "ISH_SPI_CSB"),
125 PINCTRL_PIN(82, "ISH_SPI_CLK"),
126 PINCTRL_PIN(83, "ISH_SPI_MISO"),
127 PINCTRL_PIN(84, "ISH_SPI_MOSI"),
128 PINCTRL_PIN(85, "ISH_UART0_RXD"),
129 PINCTRL_PIN(86, "ISH_UART0_TXD"),
130 PINCTRL_PIN(87, "ISH_UART0_RTSB"),
131 PINCTRL_PIN(88, "ISH_UART0_CTSB"),
132 PINCTRL_PIN(89, "DMIC_CLK_1"),
133 PINCTRL_PIN(90, "DMIC_DATA_1"),
134 PINCTRL_PIN(91, "DMIC_CLK_0"),
135 PINCTRL_PIN(92, "DMIC_DATA_0"),
136 PINCTRL_PIN(93, "SPI1_IO_2"),
137 PINCTRL_PIN(94, "SPI1_IO_3"),
138 PINCTRL_PIN(95, "SSP_MCLK"),
139 /* GPP_E */
140 PINCTRL_PIN(96, "SATAXPCIE_0"),
141 PINCTRL_PIN(97, "SATAXPCIE_1"),
142 PINCTRL_PIN(98, "SATAXPCIE_2"),
143 PINCTRL_PIN(99, "CPU_GP_0"),
144 PINCTRL_PIN(100, "SATA_DEVSLP_0"),
145 PINCTRL_PIN(101, "SATA_DEVSLP_1"),
146 PINCTRL_PIN(102, "SATA_DEVSLP_2"),
147 PINCTRL_PIN(103, "CPU_GP_1"),
148 PINCTRL_PIN(104, "SATA_LEDB"),
149 PINCTRL_PIN(105, "USB2_OCB_0"),
150 PINCTRL_PIN(106, "USB2_OCB_1"),
151 PINCTRL_PIN(107, "USB2_OCB_2"),
152 PINCTRL_PIN(108, "USB2_OCB_3"),
153 PINCTRL_PIN(109, "DDSP_HPD_0"),
154 PINCTRL_PIN(110, "DDSP_HPD_1"),
155 PINCTRL_PIN(111, "DDSP_HPD_2"),
156 PINCTRL_PIN(112, "DDSP_HPD_3"),
157 PINCTRL_PIN(113, "EDP_HPD"),
158 PINCTRL_PIN(114, "DDPB_CTRLCLK"),
159 PINCTRL_PIN(115, "DDPB_CTRLDATA"),
160 PINCTRL_PIN(116, "DDPC_CTRLCLK"),
161 PINCTRL_PIN(117, "DDPC_CTRLDATA"),
162 PINCTRL_PIN(118, "DDPD_CTRLCLK"),
163 PINCTRL_PIN(119, "DDPD_CTRLDATA"),
164 /* GPP_F */
165 PINCTRL_PIN(120, "SSP2_SCLK"),
166 PINCTRL_PIN(121, "SSP2_SFRM"),
167 PINCTRL_PIN(122, "SSP2_TXD"),
168 PINCTRL_PIN(123, "SSP2_RXD"),
169 PINCTRL_PIN(124, "I2C2_SDA"),
170 PINCTRL_PIN(125, "I2C2_SCL"),
171 PINCTRL_PIN(126, "I2C3_SDA"),
172 PINCTRL_PIN(127, "I2C3_SCL"),
173 PINCTRL_PIN(128, "I2C4_SDA"),
174 PINCTRL_PIN(129, "I2C4_SCL"),
175 PINCTRL_PIN(130, "I2C5_SDA"),
176 PINCTRL_PIN(131, "I2C5_SCL"),
177 PINCTRL_PIN(132, "EMMC_CMD"),
178 PINCTRL_PIN(133, "EMMC_DATA_0"),
179 PINCTRL_PIN(134, "EMMC_DATA_1"),
180 PINCTRL_PIN(135, "EMMC_DATA_2"),
181 PINCTRL_PIN(136, "EMMC_DATA_3"),
182 PINCTRL_PIN(137, "EMMC_DATA_4"),
183 PINCTRL_PIN(138, "EMMC_DATA_5"),
184 PINCTRL_PIN(139, "EMMC_DATA_6"),
185 PINCTRL_PIN(140, "EMMC_DATA_7"),
186 PINCTRL_PIN(141, "EMMC_RCLK"),
187 PINCTRL_PIN(142, "EMMC_CLK"),
188 PINCTRL_PIN(143, "GPP_F_23"),
189 /* GPP_G */
190 PINCTRL_PIN(144, "SD_CMD"),
191 PINCTRL_PIN(145, "SD_DATA_0"),
192 PINCTRL_PIN(146, "SD_DATA_1"),
193 PINCTRL_PIN(147, "SD_DATA_2"),
194 PINCTRL_PIN(148, "SD_DATA_3"),
195 PINCTRL_PIN(149, "SD_CDB"),
196 PINCTRL_PIN(150, "SD_CLK"),
197 PINCTRL_PIN(151, "SD_WP"),
198};
199
200static const unsigned sptlp_spi0_pins[] = { 39, 40, 41, 42 };
201static const unsigned sptlp_spi1_pins[] = { 43, 44, 45, 46 };
202static const unsigned sptlp_uart0_pins[] = { 56, 57, 58, 59 };
203static const unsigned sptlp_uart1_pins[] = { 60, 61, 62, 63 };
204static const unsigned sptlp_uart2_pins[] = { 68, 69, 71, 71 };
205static const unsigned sptlp_i2c0_pins[] = { 64, 65 };
206static const unsigned sptlp_i2c1_pins[] = { 66, 67 };
207static const unsigned sptlp_i2c2_pins[] = { 124, 125 };
208static const unsigned sptlp_i2c3_pins[] = { 126, 127 };
209static const unsigned sptlp_i2c4_pins[] = { 128, 129 };
210static const unsigned sptlp_i2c4b_pins[] = { 85, 86 };
211static const unsigned sptlp_i2c5_pins[] = { 130, 131 };
212static const unsigned sptlp_ssp2_pins[] = { 120, 121, 122, 123 };
213static const unsigned sptlp_emmc_pins[] = {
214 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142,
215};
216static const unsigned sptlp_sd_pins[] = {
217 144, 145, 146, 147, 148, 149, 150, 151,
218};
219
220static const struct intel_pingroup sptlp_groups[] = {
221 PIN_GROUP("spi0_grp", sptlp_spi0_pins, 1),
222 PIN_GROUP("spi1_grp", sptlp_spi1_pins, 1),
223 PIN_GROUP("uart0_grp", sptlp_uart0_pins, 1),
224 PIN_GROUP("uart1_grp", sptlp_uart1_pins, 1),
225 PIN_GROUP("uart2_grp", sptlp_uart2_pins, 1),
226 PIN_GROUP("i2c0_grp", sptlp_i2c0_pins, 1),
227 PIN_GROUP("i2c1_grp", sptlp_i2c1_pins, 1),
228 PIN_GROUP("i2c2_grp", sptlp_i2c2_pins, 1),
229 PIN_GROUP("i2c3_grp", sptlp_i2c3_pins, 1),
230 PIN_GROUP("i2c4_grp", sptlp_i2c4_pins, 1),
231 PIN_GROUP("i2c4b_grp", sptlp_i2c4b_pins, 3),
232 PIN_GROUP("i2c5_grp", sptlp_i2c5_pins, 1),
233 PIN_GROUP("ssp2_grp", sptlp_ssp2_pins, 1),
234 PIN_GROUP("emmc_grp", sptlp_emmc_pins, 1),
235 PIN_GROUP("sd_grp", sptlp_sd_pins, 1),
236};
237
238static const char * const sptlp_spi0_groups[] = { "spi0_grp" };
239static const char * const sptlp_spi1_groups[] = { "spi0_grp" };
240static const char * const sptlp_uart0_groups[] = { "uart0_grp" };
241static const char * const sptlp_uart1_groups[] = { "uart1_grp" };
242static const char * const sptlp_uart2_groups[] = { "uart2_grp" };
243static const char * const sptlp_i2c0_groups[] = { "i2c0_grp" };
244static const char * const sptlp_i2c1_groups[] = { "i2c1_grp" };
245static const char * const sptlp_i2c2_groups[] = { "i2c2_grp" };
246static const char * const sptlp_i2c3_groups[] = { "i2c3_grp" };
247static const char * const sptlp_i2c4_groups[] = { "i2c4_grp", "i2c4b_grp" };
248static const char * const sptlp_i2c5_groups[] = { "i2c5_grp" };
249static const char * const sptlp_ssp2_groups[] = { "ssp2_grp" };
250static const char * const sptlp_emmc_groups[] = { "emmc_grp" };
251static const char * const sptlp_sd_groups[] = { "sd_grp" };
252
253static const struct intel_function sptlp_functions[] = {
254 FUNCTION("spi0", sptlp_spi0_groups),
255 FUNCTION("spi1", sptlp_spi1_groups),
256 FUNCTION("uart0", sptlp_uart0_groups),
257 FUNCTION("uart1", sptlp_uart1_groups),
258 FUNCTION("uart2", sptlp_uart2_groups),
259 FUNCTION("i2c0", sptlp_i2c0_groups),
260 FUNCTION("i2c1", sptlp_i2c1_groups),
261 FUNCTION("i2c2", sptlp_i2c2_groups),
262 FUNCTION("i2c3", sptlp_i2c3_groups),
263 FUNCTION("i2c4", sptlp_i2c4_groups),
264 FUNCTION("i2c5", sptlp_i2c5_groups),
265 FUNCTION("ssp2", sptlp_ssp2_groups),
266 FUNCTION("emmc", sptlp_emmc_groups),
267 FUNCTION("sd", sptlp_sd_groups),
268};
269
270static const struct intel_community sptlp_communities[] = {
271 SPT_COMMUNITY(0, 0, 47),
272 SPT_COMMUNITY(1, 48, 119),
273 SPT_COMMUNITY(2, 120, 151),
274};
275
276static const struct intel_pinctrl_soc_data sptlp_soc_data = {
277 .pins = sptlp_pins,
278 .npins = ARRAY_SIZE(sptlp_pins),
279 .groups = sptlp_groups,
280 .ngroups = ARRAY_SIZE(sptlp_groups),
281 .functions = sptlp_functions,
282 .nfunctions = ARRAY_SIZE(sptlp_functions),
283 .communities = sptlp_communities,
284 .ncommunities = ARRAY_SIZE(sptlp_communities),
285};
286
Mika Westerberg551fa582015-05-07 12:54:59 +0300[diff] [blame]287/* Sunrisepoint-H */
288static const struct pinctrl_pin_desc spth_pins[] = {
289 /* GPP_A */
290 PINCTRL_PIN(0, "RCINB"),
291 PINCTRL_PIN(1, "LAD_0"),
292 PINCTRL_PIN(2, "LAD_1"),
293 PINCTRL_PIN(3, "LAD_2"),
294 PINCTRL_PIN(4, "LAD_3"),
295 PINCTRL_PIN(5, "LFRAMEB"),
296 PINCTRL_PIN(6, "SERIQ"),
297 PINCTRL_PIN(7, "PIRQAB"),
298 PINCTRL_PIN(8, "CLKRUNB"),
299 PINCTRL_PIN(9, "CLKOUT_LPC_0"),
300 PINCTRL_PIN(10, "CLKOUT_LPC_1"),
301 PINCTRL_PIN(11, "PMEB"),
302 PINCTRL_PIN(12, "BM_BUSYB"),
303 PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"),
304 PINCTRL_PIN(14, "SUS_STATB"),
305 PINCTRL_PIN(15, "SUSACKB"),
306 PINCTRL_PIN(16, "CLKOUT_48"),
307 PINCTRL_PIN(17, "ISH_GP_7"),
308 PINCTRL_PIN(18, "ISH_GP_0"),
309 PINCTRL_PIN(19, "ISH_GP_1"),
310 PINCTRL_PIN(20, "ISH_GP_2"),
311 PINCTRL_PIN(21, "ISH_GP_3"),
312 PINCTRL_PIN(22, "ISH_GP_4"),
313 PINCTRL_PIN(23, "ISH_GP_5"),
314 /* GPP_B */
315 PINCTRL_PIN(24, "CORE_VID_0"),
316 PINCTRL_PIN(25, "CORE_VID_1"),
317 PINCTRL_PIN(26, "VRALERTB"),
318 PINCTRL_PIN(27, "CPU_GP_2"),
319 PINCTRL_PIN(28, "CPU_GP_3"),
320 PINCTRL_PIN(29, "SRCCLKREQB_0"),
321 PINCTRL_PIN(30, "SRCCLKREQB_1"),
322 PINCTRL_PIN(31, "SRCCLKREQB_2"),
323 PINCTRL_PIN(32, "SRCCLKREQB_3"),
324 PINCTRL_PIN(33, "SRCCLKREQB_4"),
325 PINCTRL_PIN(34, "SRCCLKREQB_5"),
326 PINCTRL_PIN(35, "EXT_PWR_GATEB"),
327 PINCTRL_PIN(36, "SLP_S0B"),
328 PINCTRL_PIN(37, "PLTRSTB"),
329 PINCTRL_PIN(38, "SPKR"),
330 PINCTRL_PIN(39, "GSPI0_CSB"),
331 PINCTRL_PIN(40, "GSPI0_CLK"),
332 PINCTRL_PIN(41, "GSPI0_MISO"),
333 PINCTRL_PIN(42, "GSPI0_MOSI"),
334 PINCTRL_PIN(43, "GSPI1_CSB"),
335 PINCTRL_PIN(44, "GSPI1_CLK"),
336 PINCTRL_PIN(45, "GSPI1_MISO"),
337 PINCTRL_PIN(46, "GSPI1_MOSI"),
338 PINCTRL_PIN(47, "SML1ALERTB"),
339 /* GPP_C */
340 PINCTRL_PIN(48, "SMBCLK"),
341 PINCTRL_PIN(49, "SMBDATA"),
342 PINCTRL_PIN(50, "SMBALERTB"),
343 PINCTRL_PIN(51, "SML0CLK"),
344 PINCTRL_PIN(52, "SML0DATA"),
345 PINCTRL_PIN(53, "SML0ALERTB"),
346 PINCTRL_PIN(54, "SML1CLK"),
347 PINCTRL_PIN(55, "SML1DATA"),
348 PINCTRL_PIN(56, "UART0_RXD"),
349 PINCTRL_PIN(57, "UART0_TXD"),
350 PINCTRL_PIN(58, "UART0_RTSB"),
351 PINCTRL_PIN(59, "UART0_CTSB"),
352 PINCTRL_PIN(60, "UART1_RXD"),
353 PINCTRL_PIN(61, "UART1_TXD"),
354 PINCTRL_PIN(62, "UART1_RTSB"),
355 PINCTRL_PIN(63, "UART1_CTSB"),
356 PINCTRL_PIN(64, "I2C0_SDA"),
357 PINCTRL_PIN(65, "I2C0_SCL"),
358 PINCTRL_PIN(66, "I2C1_SDA"),
359 PINCTRL_PIN(67, "I2C1_SCL"),
360 PINCTRL_PIN(68, "UART2_RXD"),
361 PINCTRL_PIN(69, "UART2_TXD"),
362 PINCTRL_PIN(70, "UART2_RTSB"),
363 PINCTRL_PIN(71, "UART2_CTSB"),
364 /* GPP_D */
365 PINCTRL_PIN(72, "SPI1_CSB"),
366 PINCTRL_PIN(73, "SPI1_CLK"),
367 PINCTRL_PIN(74, "SPI1_MISO_IO_1"),
368 PINCTRL_PIN(75, "SPI1_MOSI_IO_0"),
369 PINCTRL_PIN(76, "ISH_I2C2_SDA"),
370 PINCTRL_PIN(77, "SSP0_SFRM"),
371 PINCTRL_PIN(78, "SSP0_TXD"),
372 PINCTRL_PIN(79, "SSP0_RXD"),
373 PINCTRL_PIN(80, "SSP0_SCLK"),
374 PINCTRL_PIN(81, "ISH_SPI_CSB"),
375 PINCTRL_PIN(82, "ISH_SPI_CLK"),
376 PINCTRL_PIN(83, "ISH_SPI_MISO"),
377 PINCTRL_PIN(84, "ISH_SPI_MOSI"),
378 PINCTRL_PIN(85, "ISH_UART0_RXD"),
379 PINCTRL_PIN(86, "ISH_UART0_TXD"),
380 PINCTRL_PIN(87, "ISH_UART0_RTSB"),
381 PINCTRL_PIN(88, "ISH_UART0_CTSB"),
382 PINCTRL_PIN(89, "DMIC_CLK_1"),
383 PINCTRL_PIN(90, "DMIC_DATA_1"),
384 PINCTRL_PIN(91, "DMIC_CLK_0"),
385 PINCTRL_PIN(92, "DMIC_DATA_0"),
386 PINCTRL_PIN(93, "SPI1_IO_2"),
387 PINCTRL_PIN(94, "SPI1_IO_3"),
388 PINCTRL_PIN(95, "ISH_I2C2_SCL"),
389 /* GPP_E */
390 PINCTRL_PIN(96, "SATAXPCIE_0"),
391 PINCTRL_PIN(97, "SATAXPCIE_1"),
392 PINCTRL_PIN(98, "SATAXPCIE_2"),
393 PINCTRL_PIN(99, "CPU_GP_0"),
394 PINCTRL_PIN(100, "SATA_DEVSLP_0"),
395 PINCTRL_PIN(101, "SATA_DEVSLP_1"),
396 PINCTRL_PIN(102, "SATA_DEVSLP_2"),
397 PINCTRL_PIN(103, "CPU_GP_1"),
398 PINCTRL_PIN(104, "SATA_LEDB"),
399 PINCTRL_PIN(105, "USB2_OCB_0"),
400 PINCTRL_PIN(106, "USB2_OCB_1"),
401 PINCTRL_PIN(107, "USB2_OCB_2"),
402 PINCTRL_PIN(108, "USB2_OCB_3"),
403 /* GPP_F */
404 PINCTRL_PIN(109, "SATAXPCIE_3"),
405 PINCTRL_PIN(110, "SATAXPCIE_4"),
406 PINCTRL_PIN(111, "SATAXPCIE_5"),
407 PINCTRL_PIN(112, "SATAXPCIE_6"),
408 PINCTRL_PIN(113, "SATAXPCIE_7"),
409 PINCTRL_PIN(114, "SATA_DEVSLP_3"),
410 PINCTRL_PIN(115, "SATA_DEVSLP_4"),
411 PINCTRL_PIN(116, "SATA_DEVSLP_5"),
412 PINCTRL_PIN(117, "SATA_DEVSLP_6"),
413 PINCTRL_PIN(118, "SATA_DEVSLP_7"),
414 PINCTRL_PIN(119, "SATA_SCLOCK"),
415 PINCTRL_PIN(120, "SATA_SLOAD"),
416 PINCTRL_PIN(121, "SATA_SDATAOUT1"),
417 PINCTRL_PIN(122, "SATA_SDATAOUT0"),
418 PINCTRL_PIN(123, "GPP_F_14"),
419 PINCTRL_PIN(124, "USB_OCB_4"),
420 PINCTRL_PIN(125, "USB_OCB_5"),
421 PINCTRL_PIN(126, "USB_OCB_6"),
422 PINCTRL_PIN(127, "USB_OCB_7"),
423 PINCTRL_PIN(128, "L_VDDEN"),
424 PINCTRL_PIN(129, "L_BKLTEN"),
425 PINCTRL_PIN(130, "L_BKLTCTL"),
426 PINCTRL_PIN(131, "GPP_F_22"),
427 PINCTRL_PIN(132, "GPP_F_23"),
428 /* GPP_G */
429 PINCTRL_PIN(133, "FAN_TACH_0"),
430 PINCTRL_PIN(134, "FAN_TACH_1"),
431 PINCTRL_PIN(135, "FAN_TACH_2"),
432 PINCTRL_PIN(136, "FAN_TACH_3"),
433 PINCTRL_PIN(137, "FAN_TACH_4"),
434 PINCTRL_PIN(138, "FAN_TACH_5"),
435 PINCTRL_PIN(139, "FAN_TACH_6"),
436 PINCTRL_PIN(140, "FAN_TACH_7"),
437 PINCTRL_PIN(141, "FAN_PWM_0"),
438 PINCTRL_PIN(142, "FAN_PWM_1"),
439 PINCTRL_PIN(143, "FAN_PWM_2"),
440 PINCTRL_PIN(144, "FAN_PWM_3"),
441 PINCTRL_PIN(145, "GSXDOUT"),
442 PINCTRL_PIN(146, "GSXSLOAD"),
443 PINCTRL_PIN(147, "GSXDIN"),
444 PINCTRL_PIN(148, "GSXRESETB"),
445 PINCTRL_PIN(149, "GSXCLK"),
446 PINCTRL_PIN(150, "ADR_COMPLETE"),
447 PINCTRL_PIN(151, "NMIB"),
448 PINCTRL_PIN(152, "SMIB"),
449 PINCTRL_PIN(153, "GPP_G_20"),
450 PINCTRL_PIN(154, "GPP_G_21"),
451 PINCTRL_PIN(155, "GPP_G_22"),
452 PINCTRL_PIN(156, "GPP_G_23"),
453 /* GPP_H */
454 PINCTRL_PIN(157, "SRCCLKREQB_6"),
455 PINCTRL_PIN(158, "SRCCLKREQB_7"),
456 PINCTRL_PIN(159, "SRCCLKREQB_8"),
457 PINCTRL_PIN(160, "SRCCLKREQB_9"),
458 PINCTRL_PIN(161, "SRCCLKREQB_10"),
459 PINCTRL_PIN(162, "SRCCLKREQB_11"),
460 PINCTRL_PIN(163, "SRCCLKREQB_12"),
461 PINCTRL_PIN(164, "SRCCLKREQB_13"),
462 PINCTRL_PIN(165, "SRCCLKREQB_14"),
463 PINCTRL_PIN(166, "SRCCLKREQB_15"),
464 PINCTRL_PIN(167, "SML2CLK"),
465 PINCTRL_PIN(168, "SML2DATA"),
466 PINCTRL_PIN(169, "SML2ALERTB"),
467 PINCTRL_PIN(170, "SML3CLK"),
468 PINCTRL_PIN(171, "SML3DATA"),
469 PINCTRL_PIN(172, "SML3ALERTB"),
470 PINCTRL_PIN(173, "SML4CLK"),
471 PINCTRL_PIN(174, "SML4DATA"),
472 PINCTRL_PIN(175, "SML4ALERTB"),
473 PINCTRL_PIN(176, "ISH_I2C0_SDA"),
474 PINCTRL_PIN(177, "ISH_I2C0_SCL"),
475 PINCTRL_PIN(178, "ISH_I2C1_SDA"),
476 PINCTRL_PIN(179, "ISH_I2C1_SCL"),
477 PINCTRL_PIN(180, "GPP_H_23"),
478 /* GPP_I */
479 PINCTRL_PIN(181, "DDSP_HDP_0"),
480 PINCTRL_PIN(182, "DDSP_HDP_1"),
481 PINCTRL_PIN(183, "DDSP_HDP_2"),
482 PINCTRL_PIN(184, "DDSP_HDP_3"),
483 PINCTRL_PIN(185, "EDP_HPD"),
484 PINCTRL_PIN(186, "DDPB_CTRLCLK"),
485 PINCTRL_PIN(187, "DDPB_CTRLDATA"),
486 PINCTRL_PIN(188, "DDPC_CTRLCLK"),
487 PINCTRL_PIN(189, "DDPC_CTRLDATA"),
488 PINCTRL_PIN(190, "DDPD_CTRLCLK"),
489 PINCTRL_PIN(191, "DDPD_CTRLDATA"),
490};
491
492static const unsigned spth_spi0_pins[] = { 39, 40, 41, 42 };
493static const unsigned spth_spi1_pins[] = { 43, 44, 45, 46 };
494static const unsigned spth_uart0_pins[] = { 56, 57, 58, 59 };
495static const unsigned spth_uart1_pins[] = { 60, 61, 62, 63 };
496static const unsigned spth_uart2_pins[] = { 68, 69, 71, 71 };
497static const unsigned spth_i2c0_pins[] = { 64, 65 };
498static const unsigned spth_i2c1_pins[] = { 66, 67 };
499static const unsigned spth_i2c2_pins[] = { 76, 95 };
500
501static const struct intel_pingroup spth_groups[] = {
502 PIN_GROUP("spi0_grp", spth_spi0_pins, 1),
503 PIN_GROUP("spi1_grp", spth_spi1_pins, 1),
504 PIN_GROUP("uart0_grp", spth_uart0_pins, 1),
505 PIN_GROUP("uart1_grp", spth_uart1_pins, 1),
506 PIN_GROUP("uart2_grp", spth_uart2_pins, 1),
507 PIN_GROUP("i2c0_grp", spth_i2c0_pins, 1),
508 PIN_GROUP("i2c1_grp", spth_i2c1_pins, 1),
509 PIN_GROUP("i2c2_grp", spth_i2c2_pins, 2),
510};
511
512static const char * const spth_spi0_groups[] = { "spi0_grp" };
513static const char * const spth_spi1_groups[] = { "spi0_grp" };
514static const char * const spth_uart0_groups[] = { "uart0_grp" };
515static const char * const spth_uart1_groups[] = { "uart1_grp" };
516static const char * const spth_uart2_groups[] = { "uart2_grp" };
517static const char * const spth_i2c0_groups[] = { "i2c0_grp" };
518static const char * const spth_i2c1_groups[] = { "i2c1_grp" };
519static const char * const spth_i2c2_groups[] = { "i2c2_grp" };
520
521static const struct intel_function spth_functions[] = {
522 FUNCTION("spi0", spth_spi0_groups),
523 FUNCTION("spi1", spth_spi1_groups),
524 FUNCTION("uart0", spth_uart0_groups),
525 FUNCTION("uart1", spth_uart1_groups),
526 FUNCTION("uart2", spth_uart2_groups),
527 FUNCTION("i2c0", spth_i2c0_groups),
528 FUNCTION("i2c1", spth_i2c1_groups),
529 FUNCTION("i2c2", spth_i2c2_groups),
530};
531
532static const struct intel_community spth_communities[] = {
533 SPT_COMMUNITY(0, 0, 47),
534 SPT_COMMUNITY(1, 48, 180),
535 SPT_COMMUNITY(2, 181, 191),
536};
537
538static const struct intel_pinctrl_soc_data spth_soc_data = {
539 .pins = spth_pins,
540 .npins = ARRAY_SIZE(spth_pins),
541 .groups = spth_groups,
542 .ngroups = ARRAY_SIZE(spth_groups),
543 .functions = spth_functions,
544 .nfunctions = ARRAY_SIZE(spth_functions),
545 .communities = spth_communities,
546 .ncommunities = ARRAY_SIZE(spth_communities),
547};
548
Mika Westerberg7981c0012015-03-30 17:31:49 +0300[diff] [blame]549static const struct acpi_device_id spt_pinctrl_acpi_match[] = {
550 { "INT344B", (kernel_ulong_t)&sptlp_soc_data },
Mika Westerberg551fa582015-05-07 12:54:59 +0300[diff] [blame]551 { "INT345D", (kernel_ulong_t)&spth_soc_data },
Mika Westerberg7981c0012015-03-30 17:31:49 +0300[diff] [blame]552 { }
553};
554MODULE_DEVICE_TABLE(acpi, spt_pinctrl_acpi_match);
555
556static int spt_pinctrl_probe(struct platform_device *pdev)
557{
558 const struct intel_pinctrl_soc_data *soc_data;
559 const struct acpi_device_id *id;
560
561 id = acpi_match_device(spt_pinctrl_acpi_match, &pdev->dev);
562 if (!id || !id->driver_data)
563 return -ENODEV;
564
565 soc_data = (const struct intel_pinctrl_soc_data *)id->driver_data;
566 return intel_pinctrl_probe(pdev, soc_data);
567}
568
569static const struct dev_pm_ops spt_pinctrl_pm_ops = {
570 SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
571 intel_pinctrl_resume)
572};
573
574static struct platform_driver spt_pinctrl_driver = {
575 .probe = spt_pinctrl_probe,
576 .remove = intel_pinctrl_remove,
577 .driver = {
578 .name = "sunrisepoint-pinctrl",
579 .acpi_match_table = spt_pinctrl_acpi_match,
580 .pm = &spt_pinctrl_pm_ops,
581 },
582};
583
584static int __init spt_pinctrl_init(void)
585{
586 return platform_driver_register(&spt_pinctrl_driver);
587}
588subsys_initcall(spt_pinctrl_init);
589
590static void __exit spt_pinctrl_exit(void)
591{
592 platform_driver_unregister(&spt_pinctrl_driver);
593}
594module_exit(spt_pinctrl_exit);
595
596MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
597MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
598MODULE_DESCRIPTION("Intel Sunrisepoint PCH pinctrl/GPIO driver");
599MODULE_LICENSE("GPL v2");