| Sandeep Patil | ddbf565 | 2008-10-21 14:06:23 +0100 | [diff] [blame] | 1 | /* linux/arch/arm/mach-s3c24a0/include/mach/irqs.h |
| 2 | * |
| 3 | * Copyright (c) 2003-2005 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | |
| 12 | #ifndef __ASM_ARCH_24A0_IRQS_H |
| 13 | #define __ASM_ARCH_24A0_IRQS_H __FILE__ |
| 14 | |
| 15 | #define IRQ_EINT0t2 S3C2410_IRQ(0) /* 16 */ |
| 16 | /* for generic entry-macro.S */ |
| 17 | #define IRQ_EINT0 IRQ_EINT0t2 |
| 18 | |
| 19 | #define IRQ_EINT3t6 S3C2410_IRQ(1) |
| 20 | #define IRQ_EINT7t10 S3C2410_IRQ(2) |
| 21 | #define IRQ_EINT11t14 S3C2410_IRQ(3) |
| 22 | #define IRQ_EINT15t18 S3C2410_IRQ(4) /* 20 */ |
| 23 | #define IRQ_TICK S3C2410_IRQ(5) |
| 24 | #define IRQ_DCTQ S3C2410_IRQ(6) |
| 25 | #define IRQ_MC S3C2410_IRQ(7) |
| 26 | #define IRQ_ME S3C2410_IRQ(8) /* 24 */ |
| 27 | #define IRQ_KEYPAD S3C2410_IRQ(9) |
| 28 | #define IRQ_TIMER0 S3C2410_IRQ(10) |
| 29 | #define IRQ_TIMER1 S3C2410_IRQ(11) |
| 30 | #define IRQ_TIMER2 S3C2410_IRQ(12) |
| 31 | #define IRQ_TIMER3_4 S3C2410_IRQ(13) |
| 32 | #define IRQ_OS_TIMER IRQ_TIMER3_4 |
| 33 | #define IRQ_LCD S3C2410_IRQ(14) |
| 34 | #define IRQ_CAM_C S3C2410_IRQ(15) |
| 35 | #define IRQ_WDT_BATFLT S3C2410_IRQ(16) /* 32 */ |
| 36 | #define IRQ_UART0 S3C2410_IRQ(17) |
| 37 | #define IRQ_CAM_P S3C2410_IRQ(18) |
| 38 | #define IRQ_MODEM S3C2410_IRQ(19) |
| 39 | #define IRQ_DMA S3C2410_IRQ(20) |
| 40 | #define IRQ_SDI S3C2410_IRQ(21) |
| 41 | #define IRQ_SPI0 S3C2410_IRQ(22) |
| 42 | #define IRQ_UART1 S3C2410_IRQ(23) |
| 43 | #define IRQ_AC97_NFLASH S3C2410_IRQ(24) /* 40 */ |
| 44 | #define IRQ_USBD S3C2410_IRQ(25) |
| 45 | #define IRQ_USBH S3C2410_IRQ(26) |
| 46 | #define IRQ_IIC S3C2410_IRQ(27) |
| 47 | #define IRQ_IRDA_MSTICK S3C2410_IRQ(28) /* 44 */ |
| 48 | #define IRQ_VLX_SPI1 S3C2410_IRQ(29) |
| 49 | #define IRQ_RTC S3C2410_IRQ(30) /* 46 */ |
| 50 | #define IRQ_ADC_PEN S3C2410_IRQ(31) |
| 51 | |
| 52 | /* interrupts generated from the external interrupts sources */ |
| 53 | #define IRQ_EINT00 S3C2410_IRQ(32) /* 48 */ |
| 54 | #define IRQ_EINT1 S3C2410_IRQ(33) |
| 55 | #define IRQ_EINT2 S3C2410_IRQ(34) |
| 56 | #define IRQ_EINT3 S3C2410_IRQ(35) |
| 57 | #define IRQ_EINT4 S3C2410_IRQ(36) |
| 58 | #define IRQ_EINT5 S3C2410_IRQ(37) |
| 59 | #define IRQ_EINT6 S3C2410_IRQ(38) |
| 60 | #define IRQ_EINT7 S3C2410_IRQ(39) |
| 61 | #define IRQ_EINT8 S3C2410_IRQ(40) |
| 62 | #define IRQ_EINT9 S3C2410_IRQ(41) |
| 63 | #define IRQ_EINT10 S3C2410_IRQ(42) |
| 64 | #define IRQ_EINT11 S3C2410_IRQ(43) |
| 65 | #define IRQ_EINT12 S3C2410_IRQ(44) |
| 66 | #define IRQ_EINT13 S3C2410_IRQ(45) |
| 67 | #define IRQ_EINT14 S3C2410_IRQ(46) |
| 68 | #define IRQ_EINT15 S3C2410_IRQ(47) |
| 69 | #define IRQ_EINT16 S3C2410_IRQ(48) |
| 70 | #define IRQ_EINT17 S3C2410_IRQ(49) |
| 71 | #define IRQ_EINT18 S3C2410_IRQ(50) |
| 72 | |
| Ben Dooks | 56b3442 | 2008-12-12 00:24:12 +0000 | [diff] [blame] | 73 | #define IRQ_EINT_BIT(x) ((x) - IRQ_EINT00) |
| 74 | |
| Sandeep Patil | ddbf565 | 2008-10-21 14:06:23 +0100 | [diff] [blame] | 75 | /* SUB IRQS */ |
| 76 | #define IRQ_S3CUART_RX0 S3C2410_IRQ(51) /* 67 */ |
| 77 | #define IRQ_S3CUART_TX0 S3C2410_IRQ(52) |
| 78 | #define IRQ_S3CUART_ERR0 S3C2410_IRQ(53) |
| 79 | |
| 80 | #define IRQ_S3CUART_RX1 S3C2410_IRQ(54) |
| 81 | #define IRQ_S3CUART_TX1 S3C2410_IRQ(55) |
| 82 | #define IRQ_S3CUART_ERR1 S3C2410_IRQ(56) |
| 83 | |
| 84 | #define IRQ_S3CUART_RX2 (0x0) |
| 85 | #define IRQ_S3CUART_TX2 (0x0) |
| 86 | #define IRQ_S3CUART_ERR2 (0x0) |
| 87 | |
| 88 | |
| 89 | #define IRQ_IRDA S3C2410_IRQ(57) |
| 90 | #define IRQ_MSTICK S3C2410_IRQ(58) |
| 91 | #define IRQ_RESERVED0 S3C2410_IRQ(59) |
| 92 | #define IRQ_RESERVED1 S3C2410_IRQ(60) |
| 93 | #define IRQ_RESERVED2 S3C2410_IRQ(61) |
| 94 | #define IRQ_TIMER3 S3C2410_IRQ(62) |
| 95 | #define IRQ_TIMER4 S3C2410_IRQ(63) |
| 96 | #define IRQ_WDT S3C2410_IRQ(64) |
| 97 | #define IRQ_BATFLT S3C2410_IRQ(65) |
| 98 | #define IRQ_POST S3C2410_IRQ(66) |
| 99 | #define IRQ_DISP_FIFO S3C2410_IRQ(67) |
| 100 | #define IRQ_PENUP S3C2410_IRQ(68) |
| 101 | #define IRQ_PENDN S3C2410_IRQ(69) |
| 102 | #define IRQ_ADC S3C2410_IRQ(70) |
| 103 | #define IRQ_DISP_FRAME S3C2410_IRQ(71) |
| 104 | #define IRQ_NFLASH S3C2410_IRQ(72) |
| 105 | #define IRQ_AC97 S3C2410_IRQ(73) |
| 106 | #define IRQ_SPI1 S3C2410_IRQ(74) |
| 107 | #define IRQ_VLX S3C2410_IRQ(75) |
| 108 | #define IRQ_DMA0 S3C2410_IRQ(76) |
| 109 | #define IRQ_DMA1 S3C2410_IRQ(77) |
| 110 | #define IRQ_DMA2 S3C2410_IRQ(78) |
| 111 | #define IRQ_DMA3 S3C2410_IRQ(79) |
| 112 | |
| 113 | #define IRQ_TC (0x0) |
| 114 | |
| 115 | #define NR_IRQS (IRQ_DMA3+1) |
| 116 | |
| 117 | #endif /* __ASM_ARCH_24A0_IRQS_H */ |