Mark Brown | 5a3af12 | 2014-02-06 12:03:27 +0000 | [diff] [blame] | 1 | PCM512x audio CODECs |
| 2 | |
| 3 | These devices support both I2C and SPI (configured with pin strapping |
| 4 | on the board). |
| 5 | |
| 6 | Required properties: |
| 7 | |
Peter Rosin | ba5295e | 2014-12-09 09:28:09 +0100 | [diff] [blame] | 8 | - compatible : One of "ti,pcm5121", "ti,pcm5122", "ti,pcm5141" or |
| 9 | "ti,pcm5142" |
Mark Brown | 5a3af12 | 2014-02-06 12:03:27 +0000 | [diff] [blame] | 10 | |
| 11 | - reg : the I2C address of the device for I2C, the chip select |
| 12 | number for SPI. |
| 13 | |
| 14 | - AVDD-supply, DVDD-supply, and CPVDD-supply : power supplies for the |
| 15 | device, as covered in bindings/regulator/regulator.txt |
| 16 | |
| 17 | Optional properties: |
| 18 | |
| 19 | - clocks : A clock specifier for the clock connected as SCLK. If this |
Peter Rosin | f086ba9 | 2015-01-28 15:16:10 +0100 | [diff] [blame] | 20 | is absent the device will be configured to clock from BCLK. If pll-in |
| 21 | and pll-out are specified in addition to a clock, the device is |
| 22 | configured to accept clock input on a specified gpio pin. |
Mark Brown | 5a3af12 | 2014-02-06 12:03:27 +0000 | [diff] [blame] | 23 | |
Peter Rosin | f086ba9 | 2015-01-28 15:16:10 +0100 | [diff] [blame] | 24 | - pll-in, pll-out : gpio pins used to connect the pll using <1> |
| 25 | through <6>. The device will be configured for clock input on the |
| 26 | given pll-in pin and PLL output on the given pll-out pin. An |
| 27 | external connection from the pll-out pin to the SCLK pin is assumed. |
| 28 | |
| 29 | Examples: |
Mark Brown | 5a3af12 | 2014-02-06 12:03:27 +0000 | [diff] [blame] | 30 | |
| 31 | pcm5122: pcm5122@4c { |
| 32 | compatible = "ti,pcm5122"; |
| 33 | reg = <0x4c>; |
| 34 | |
| 35 | AVDD-supply = <®_3v3_analog>; |
| 36 | DVDD-supply = <®_1v8>; |
| 37 | CPVDD-supply = <®_3v3>; |
| 38 | }; |
Peter Rosin | f086ba9 | 2015-01-28 15:16:10 +0100 | [diff] [blame] | 39 | |
| 40 | |
| 41 | pcm5142: pcm5142@4c { |
| 42 | compatible = "ti,pcm5142"; |
| 43 | reg = <0x4c>; |
| 44 | |
| 45 | AVDD-supply = <®_3v3_analog>; |
| 46 | DVDD-supply = <®_1v8>; |
| 47 | CPVDD-supply = <®_3v3>; |
| 48 | |
| 49 | clocks = <&sck>; |
| 50 | pll-in = <3>; |
| 51 | pll-out = <6>; |
| 52 | }; |