Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
Ben Skeggs | 70c0f26 | 2012-07-10 10:49:22 +1000 | [diff] [blame] | 25 | #include <subdev/bios.h> |
Martin Peres | a10220b | 2012-11-04 01:01:53 +0100 | [diff] [blame] | 26 | #include <subdev/bus.h> |
Ben Skeggs | e0996ae | 2012-07-10 12:20:17 +1000 | [diff] [blame] | 27 | #include <subdev/gpio.h> |
Ben Skeggs | 4196faa | 2012-07-10 14:36:38 +1000 | [diff] [blame] | 28 | #include <subdev/i2c.h> |
Ben Skeggs | 8aceb7d | 2012-07-10 16:45:24 +1000 | [diff] [blame] | 29 | #include <subdev/clock.h> |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 30 | #include <subdev/devinit.h> |
Ben Skeggs | 7d9115d | 2012-07-11 15:58:56 +1000 | [diff] [blame] | 31 | #include <subdev/mc.h> |
Ben Skeggs | 5a5c743 | 2012-07-11 16:08:25 +1000 | [diff] [blame] | 32 | #include <subdev/timer.h> |
Ben Skeggs | 861d210 | 2012-07-11 19:05:01 +1000 | [diff] [blame] | 33 | #include <subdev/fb.h> |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame] | 34 | #include <subdev/instmem.h> |
| 35 | #include <subdev/vm.h> |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 36 | |
Ben Skeggs | dded35d | 2013-04-25 17:23:43 +1000 | [diff] [blame] | 37 | #include <engine/device.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 38 | #include <engine/dmaobj.h> |
| 39 | #include <engine/fifo.h> |
| 40 | #include <engine/software.h> |
| 41 | #include <engine/graph.h> |
| 42 | #include <engine/mpeg.h> |
| 43 | #include <engine/disp.h> |
| 44 | |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 45 | int |
| 46 | nv30_identify(struct nouveau_device *device) |
| 47 | { |
| 48 | switch (device->chipset) { |
| 49 | case 0x30: |
Ben Skeggs | 2094dd8 | 2012-07-27 08:28:20 +1000 | [diff] [blame] | 50 | device->cname = "NV30"; |
Ben Skeggs | 70c0f26 | 2012-07-10 10:49:22 +1000 | [diff] [blame] | 51 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
Ben Skeggs | d93174e | 2014-05-12 14:18:06 +1000 | [diff] [blame] | 52 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; |
Ben Skeggs | c26fe84 | 2014-05-13 13:59:26 +1000 | [diff] [blame] | 53 | device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; |
Ben Skeggs | 8aceb7d | 2012-07-10 16:45:24 +1000 | [diff] [blame] | 54 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
Ben Skeggs | cf33601 | 2014-01-14 15:55:38 +1000 | [diff] [blame] | 55 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; |
Ben Skeggs | 08f6fbd | 2013-10-11 15:34:08 +1000 | [diff] [blame] | 56 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
Ben Skeggs | 48ae0b3 | 2013-10-24 09:39:05 +1000 | [diff] [blame] | 57 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
Ben Skeggs | 5a5c743 | 2012-07-11 16:08:25 +1000 | [diff] [blame] | 58 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
Ben Skeggs | 1e9fc30 | 2013-10-18 14:18:04 +1000 | [diff] [blame] | 59 | device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; |
Ben Skeggs | 24a4ae8 | 2013-12-23 00:39:47 +1000 | [diff] [blame] | 60 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame] | 61 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
Ben Skeggs | bc98540 | 2014-08-10 04:10:24 +1000 | [diff] [blame^] | 62 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; |
Ben Skeggs | 16c4f22 | 2013-11-05 14:26:58 +1000 | [diff] [blame] | 63 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
Ben Skeggs | c46c3dd | 2013-10-03 07:30:11 +1000 | [diff] [blame] | 64 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 65 | device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass; |
Ben Skeggs | a8f8b48 | 2014-02-20 21:33:34 +1000 | [diff] [blame] | 66 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 67 | break; |
| 68 | case 0x35: |
Ben Skeggs | 2094dd8 | 2012-07-27 08:28:20 +1000 | [diff] [blame] | 69 | device->cname = "NV35"; |
Ben Skeggs | 70c0f26 | 2012-07-10 10:49:22 +1000 | [diff] [blame] | 70 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
Ben Skeggs | d93174e | 2014-05-12 14:18:06 +1000 | [diff] [blame] | 71 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; |
Ben Skeggs | c26fe84 | 2014-05-13 13:59:26 +1000 | [diff] [blame] | 72 | device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; |
Ben Skeggs | 8aceb7d | 2012-07-10 16:45:24 +1000 | [diff] [blame] | 73 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
Ben Skeggs | cf33601 | 2014-01-14 15:55:38 +1000 | [diff] [blame] | 74 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; |
Ben Skeggs | 08f6fbd | 2013-10-11 15:34:08 +1000 | [diff] [blame] | 75 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
Ben Skeggs | 48ae0b3 | 2013-10-24 09:39:05 +1000 | [diff] [blame] | 76 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
Ben Skeggs | 5a5c743 | 2012-07-11 16:08:25 +1000 | [diff] [blame] | 77 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
Ben Skeggs | 1e9fc30 | 2013-10-18 14:18:04 +1000 | [diff] [blame] | 78 | device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass; |
Ben Skeggs | 24a4ae8 | 2013-12-23 00:39:47 +1000 | [diff] [blame] | 79 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame] | 80 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
Ben Skeggs | bc98540 | 2014-08-10 04:10:24 +1000 | [diff] [blame^] | 81 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; |
Ben Skeggs | 16c4f22 | 2013-11-05 14:26:58 +1000 | [diff] [blame] | 82 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
Ben Skeggs | c46c3dd | 2013-10-03 07:30:11 +1000 | [diff] [blame] | 83 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 84 | device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass; |
Ben Skeggs | a8f8b48 | 2014-02-20 21:33:34 +1000 | [diff] [blame] | 85 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 86 | break; |
| 87 | case 0x31: |
Ben Skeggs | 2094dd8 | 2012-07-27 08:28:20 +1000 | [diff] [blame] | 88 | device->cname = "NV31"; |
Ben Skeggs | 70c0f26 | 2012-07-10 10:49:22 +1000 | [diff] [blame] | 89 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
Ben Skeggs | d93174e | 2014-05-12 14:18:06 +1000 | [diff] [blame] | 90 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; |
Ben Skeggs | c26fe84 | 2014-05-13 13:59:26 +1000 | [diff] [blame] | 91 | device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; |
Ben Skeggs | 8aceb7d | 2012-07-10 16:45:24 +1000 | [diff] [blame] | 92 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
Ben Skeggs | cf33601 | 2014-01-14 15:55:38 +1000 | [diff] [blame] | 93 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; |
Ben Skeggs | 08f6fbd | 2013-10-11 15:34:08 +1000 | [diff] [blame] | 94 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
Ben Skeggs | 48ae0b3 | 2013-10-24 09:39:05 +1000 | [diff] [blame] | 95 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
Ben Skeggs | 5a5c743 | 2012-07-11 16:08:25 +1000 | [diff] [blame] | 96 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
Ben Skeggs | 1e9fc30 | 2013-10-18 14:18:04 +1000 | [diff] [blame] | 97 | device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; |
Ben Skeggs | 24a4ae8 | 2013-12-23 00:39:47 +1000 | [diff] [blame] | 98 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame] | 99 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
Ben Skeggs | bc98540 | 2014-08-10 04:10:24 +1000 | [diff] [blame^] | 100 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; |
Ben Skeggs | 16c4f22 | 2013-11-05 14:26:58 +1000 | [diff] [blame] | 101 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
Ben Skeggs | c46c3dd | 2013-10-03 07:30:11 +1000 | [diff] [blame] | 102 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 103 | device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass; |
| 104 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; |
Ben Skeggs | a8f8b48 | 2014-02-20 21:33:34 +1000 | [diff] [blame] | 105 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 106 | break; |
| 107 | case 0x36: |
Ben Skeggs | 2094dd8 | 2012-07-27 08:28:20 +1000 | [diff] [blame] | 108 | device->cname = "NV36"; |
Ben Skeggs | 70c0f26 | 2012-07-10 10:49:22 +1000 | [diff] [blame] | 109 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
Ben Skeggs | d93174e | 2014-05-12 14:18:06 +1000 | [diff] [blame] | 110 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; |
Ben Skeggs | c26fe84 | 2014-05-13 13:59:26 +1000 | [diff] [blame] | 111 | device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; |
Ben Skeggs | 8aceb7d | 2012-07-10 16:45:24 +1000 | [diff] [blame] | 112 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
Ben Skeggs | cf33601 | 2014-01-14 15:55:38 +1000 | [diff] [blame] | 113 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; |
Ben Skeggs | 08f6fbd | 2013-10-11 15:34:08 +1000 | [diff] [blame] | 114 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
Ben Skeggs | 48ae0b3 | 2013-10-24 09:39:05 +1000 | [diff] [blame] | 115 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
Ben Skeggs | 5a5c743 | 2012-07-11 16:08:25 +1000 | [diff] [blame] | 116 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
Ben Skeggs | 1e9fc30 | 2013-10-18 14:18:04 +1000 | [diff] [blame] | 117 | device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass; |
Ben Skeggs | 24a4ae8 | 2013-12-23 00:39:47 +1000 | [diff] [blame] | 118 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame] | 119 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
Ben Skeggs | bc98540 | 2014-08-10 04:10:24 +1000 | [diff] [blame^] | 120 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; |
Ben Skeggs | 16c4f22 | 2013-11-05 14:26:58 +1000 | [diff] [blame] | 121 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
Ben Skeggs | c46c3dd | 2013-10-03 07:30:11 +1000 | [diff] [blame] | 122 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 123 | device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass; |
| 124 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; |
Ben Skeggs | a8f8b48 | 2014-02-20 21:33:34 +1000 | [diff] [blame] | 125 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 126 | break; |
| 127 | case 0x34: |
Ben Skeggs | 2094dd8 | 2012-07-27 08:28:20 +1000 | [diff] [blame] | 128 | device->cname = "NV34"; |
Ben Skeggs | 70c0f26 | 2012-07-10 10:49:22 +1000 | [diff] [blame] | 129 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
Ben Skeggs | d93174e | 2014-05-12 14:18:06 +1000 | [diff] [blame] | 130 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; |
Ben Skeggs | c26fe84 | 2014-05-13 13:59:26 +1000 | [diff] [blame] | 131 | device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; |
Ben Skeggs | 8aceb7d | 2012-07-10 16:45:24 +1000 | [diff] [blame] | 132 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
Ben Skeggs | cf33601 | 2014-01-14 15:55:38 +1000 | [diff] [blame] | 133 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; |
Ben Skeggs | 08f6fbd | 2013-10-11 15:34:08 +1000 | [diff] [blame] | 134 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
Ben Skeggs | 48ae0b3 | 2013-10-24 09:39:05 +1000 | [diff] [blame] | 135 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
Ben Skeggs | 5a5c743 | 2012-07-11 16:08:25 +1000 | [diff] [blame] | 136 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
Ben Skeggs | 1e9fc30 | 2013-10-18 14:18:04 +1000 | [diff] [blame] | 137 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; |
Ben Skeggs | 24a4ae8 | 2013-12-23 00:39:47 +1000 | [diff] [blame] | 138 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame] | 139 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
Ben Skeggs | bc98540 | 2014-08-10 04:10:24 +1000 | [diff] [blame^] | 140 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; |
Ben Skeggs | 16c4f22 | 2013-11-05 14:26:58 +1000 | [diff] [blame] | 141 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
Ben Skeggs | c46c3dd | 2013-10-03 07:30:11 +1000 | [diff] [blame] | 142 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 143 | device->oclass[NVDEV_ENGINE_GR ] = &nv34_graph_oclass; |
| 144 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; |
Ben Skeggs | a8f8b48 | 2014-02-20 21:33:34 +1000 | [diff] [blame] | 145 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 146 | break; |
| 147 | default: |
| 148 | nv_fatal(device, "unknown Rankine chipset\n"); |
| 149 | return -EINVAL; |
| 150 | } |
| 151 | |
| 152 | return 0; |
| 153 | } |