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gerrit-public.fairphone.software / kernel / msm-4.9 / bc98540b7b506689a9bd7bedffb9f60f9c62d945 / . / drivers / gpu / drm / nouveau / core / engine / device / nv50.c
blob: 932f84fae4591c88c46164875afe76785a60476d [file] [log] [blame]
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]25#include <subdev/bios.h>
Martin Peresa10220b2012-11-04 01:01:53 +0100[diff] [blame]26#include <subdev/bus.h>
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]27#include <subdev/gpio.h>
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]28#include <subdev/i2c.h>
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]29#include <subdev/clock.h>
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]30#include <subdev/therm.h>
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]31#include <subdev/mxm.h>
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]32#include <subdev/devinit.h>
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]33#include <subdev/mc.h>
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]34#include <subdev/timer.h>
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]35#include <subdev/fb.h>
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]36#include <subdev/instmem.h>
37#include <subdev/vm.h>
38#include <subdev/bar.h>
Ben Skeggsff4b42c2013-10-15 09:38:12 +1000[diff] [blame]39#include <subdev/pwr.h>
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]40#include <subdev/volt.h>
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]41
Ben Skeggsdded35d2013-04-25 17:23:43 +1000[diff] [blame]42#include <engine/device.h>
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]43#include <engine/dmaobj.h>
44#include <engine/fifo.h>
45#include <engine/software.h>
46#include <engine/graph.h>
47#include <engine/mpeg.h>
48#include <engine/vp.h>
49#include <engine/crypt.h>
50#include <engine/bsp.h>
51#include <engine/ppp.h>
52#include <engine/copy.h>
53#include <engine/disp.h>
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]54#include <engine/perfmon.h>
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]55
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]56int
57nv50_identify(struct nouveau_device *device)
58{
59 switch (device->chipset) {
60 case 0x50:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]61 device->cname = "G80";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]62 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggsd93174e2014-05-12 14:18:06 +1000[diff] [blame]63 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
Ben Skeggsc26fe842014-05-13 13:59:26 +1000[diff] [blame]64 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
Ben Skeggs7c856522013-01-14 08:28:28 +1000[diff] [blame]65 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv50_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]66 device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]67 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggscf336012014-01-14 15:55:38 +1000[diff] [blame]68 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass;
Ben Skeggs08f6fbd2013-10-11 15:34:08 +1000[diff] [blame]69 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
Ben Skeggs48ae0b32013-10-24 09:39:05 +1000[diff] [blame]70 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]71 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame]72 device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]73 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]74 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
75 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]76 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggsbc985402014-08-10 04:10:24 +1000[diff] [blame^]77 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]78 device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]79 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]80 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
81 device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
Ben Skeggsa8f8b482014-02-20 21:33:34 +1000[diff] [blame]82 device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass;
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]83 device->oclass[NVDEV_ENGINE_PERFMON] = nv50_perfmon_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]84 break;
85 case 0x84:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]86 device->cname = "G84";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]87 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggsd93174e2014-05-12 14:18:06 +1000[diff] [blame]88 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
Ben Skeggsc26fe842014-05-13 13:59:26 +1000[diff] [blame]89 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
Ben Skeggs7c856522013-01-14 08:28:28 +1000[diff] [blame]90 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
Martin Peres2f457362013-02-23 16:45:51 +0100[diff] [blame]91 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]92 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ilia Mirkin4019aaa2014-01-14 16:29:06 +1000[diff] [blame]93 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
Ben Skeggs08f6fbd2013-10-11 15:34:08 +1000[diff] [blame]94 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
Ben Skeggs48ae0b32013-10-24 09:39:05 +1000[diff] [blame]95 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]96 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs9ca30372013-10-18 14:44:23 +1000[diff] [blame]97 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]98 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]99 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
100 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]101 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggsbc985402014-08-10 04:10:24 +1000[diff] [blame^]102 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]103 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]104 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]105 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
106 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
107 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
108 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
109 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
Ben Skeggsa8f8b482014-02-20 21:33:34 +1000[diff] [blame]110 device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]111 device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]112 break;
113 case 0x86:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]114 device->cname = "G86";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]115 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggsd93174e2014-05-12 14:18:06 +1000[diff] [blame]116 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
Ben Skeggsc26fe842014-05-13 13:59:26 +1000[diff] [blame]117 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
Ben Skeggs7c856522013-01-14 08:28:28 +1000[diff] [blame]118 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
Martin Peres2f457362013-02-23 16:45:51 +0100[diff] [blame]119 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]120 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ilia Mirkin4019aaa2014-01-14 16:29:06 +1000[diff] [blame]121 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
Ben Skeggs08f6fbd2013-10-11 15:34:08 +1000[diff] [blame]122 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
Ben Skeggs48ae0b32013-10-24 09:39:05 +1000[diff] [blame]123 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]124 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs9ca30372013-10-18 14:44:23 +1000[diff] [blame]125 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]126 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]127 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
128 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]129 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggsbc985402014-08-10 04:10:24 +1000[diff] [blame^]130 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]131 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]132 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]133 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
134 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
135 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
136 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
137 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
Ben Skeggsa8f8b482014-02-20 21:33:34 +1000[diff] [blame]138 device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]139 device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]140 break;
141 case 0x92:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]142 device->cname = "G92";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]143 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggs73568592014-05-12 15:22:42 +1000[diff] [blame]144 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
Ben Skeggsc26fe842014-05-13 13:59:26 +1000[diff] [blame]145 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
Ben Skeggs7c856522013-01-14 08:28:28 +1000[diff] [blame]146 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
Martin Peres2f457362013-02-23 16:45:51 +0100[diff] [blame]147 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]148 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ilia Mirkin4019aaa2014-01-14 16:29:06 +1000[diff] [blame]149 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
Ben Skeggs08f6fbd2013-10-11 15:34:08 +1000[diff] [blame]150 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
Ben Skeggs48ae0b32013-10-24 09:39:05 +1000[diff] [blame]151 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]152 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs9ca30372013-10-18 14:44:23 +1000[diff] [blame]153 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]154 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]155 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
156 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]157 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggsbc985402014-08-10 04:10:24 +1000[diff] [blame^]158 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]159 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]160 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]161 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
162 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
163 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
164 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
165 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
Ben Skeggsa8f8b482014-02-20 21:33:34 +1000[diff] [blame]166 device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]167 device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]168 break;
169 case 0x94:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]170 device->cname = "G94";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]171 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggs73568592014-05-12 15:22:42 +1000[diff] [blame]172 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
Ben Skeggsc26fe842014-05-13 13:59:26 +1000[diff] [blame]173 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
Ben Skeggs7c856522013-01-14 08:28:28 +1000[diff] [blame]174 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
Martin Peres2f457362013-02-23 16:45:51 +0100[diff] [blame]175 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]176 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ilia Mirkin4019aaa2014-01-14 16:29:06 +1000[diff] [blame]177 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
Ben Skeggs9a9d5c62013-10-14 14:58:16 +1000[diff] [blame]178 device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
Ben Skeggs29845062013-10-15 10:49:39 +1000[diff] [blame]179 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]180 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs9ca30372013-10-18 14:44:23 +1000[diff] [blame]181 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]182 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]183 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
184 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]185 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggsbc985402014-08-10 04:10:24 +1000[diff] [blame^]186 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]187 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]188 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]189 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
190 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
191 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
192 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
193 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
Ben Skeggsa8f8b482014-02-20 21:33:34 +1000[diff] [blame]194 device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]195 device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]196 break;
197 case 0x96:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]198 device->cname = "G96";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]199 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggs73568592014-05-12 15:22:42 +1000[diff] [blame]200 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
Ben Skeggsc26fe842014-05-13 13:59:26 +1000[diff] [blame]201 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
Ben Skeggs7c856522013-01-14 08:28:28 +1000[diff] [blame]202 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
Martin Peres2f457362013-02-23 16:45:51 +0100[diff] [blame]203 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]204 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ilia Mirkin4019aaa2014-01-14 16:29:06 +1000[diff] [blame]205 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
Ben Skeggs9a9d5c62013-10-14 14:58:16 +1000[diff] [blame]206 device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
Ben Skeggs29845062013-10-15 10:49:39 +1000[diff] [blame]207 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]208 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs9ca30372013-10-18 14:44:23 +1000[diff] [blame]209 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]210 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]211 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
212 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]213 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggsbc985402014-08-10 04:10:24 +1000[diff] [blame^]214 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]215 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]216 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]217 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
218 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
219 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
220 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
221 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
Ben Skeggsa8f8b482014-02-20 21:33:34 +1000[diff] [blame]222 device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]223 device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]224 break;
225 case 0x98:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]226 device->cname = "G98";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]227 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggs73568592014-05-12 15:22:42 +1000[diff] [blame]228 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
Ben Skeggsc26fe842014-05-13 13:59:26 +1000[diff] [blame]229 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
Ben Skeggs7c856522013-01-14 08:28:28 +1000[diff] [blame]230 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
Martin Peres2f457362013-02-23 16:45:51 +0100[diff] [blame]231 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]232 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ilia Mirkin4019aaa2014-01-14 16:29:06 +1000[diff] [blame]233 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
Ben Skeggs08f6fbd2013-10-11 15:34:08 +1000[diff] [blame]234 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
Ben Skeggs29845062013-10-15 10:49:39 +1000[diff] [blame]235 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]236 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs9ca30372013-10-18 14:44:23 +1000[diff] [blame]237 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]238 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]239 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
240 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]241 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggsbc985402014-08-10 04:10:24 +1000[diff] [blame^]242 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]243 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]244 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]245 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
Ilia Mirkin0d4a1452013-06-27 14:04:20 +1000[diff] [blame]246 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]247 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
Ilia Mirkin0d4a1452013-06-27 14:04:20 +1000[diff] [blame]248 device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]249 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
Ben Skeggsa8f8b482014-02-20 21:33:34 +1000[diff] [blame]250 device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]251 device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]252 break;
253 case 0xa0:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]254 device->cname = "G200";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]255 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggs73568592014-05-12 15:22:42 +1000[diff] [blame]256 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
Ben Skeggsc26fe842014-05-13 13:59:26 +1000[diff] [blame]257 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
Ben Skeggs7c856522013-01-14 08:28:28 +1000[diff] [blame]258 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
Martin Peres2f457362013-02-23 16:45:51 +0100[diff] [blame]259 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]260 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ilia Mirkin4019aaa2014-01-14 16:29:06 +1000[diff] [blame]261 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
Ben Skeggs08f6fbd2013-10-11 15:34:08 +1000[diff] [blame]262 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
Ben Skeggs29845062013-10-15 10:49:39 +1000[diff] [blame]263 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]264 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs9ca30372013-10-18 14:44:23 +1000[diff] [blame]265 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]266 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]267 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
268 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]269 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggsbc985402014-08-10 04:10:24 +1000[diff] [blame^]270 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]271 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]272 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]273 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
274 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
275 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
276 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
277 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
Ben Skeggsa8f8b482014-02-20 21:33:34 +1000[diff] [blame]278 device->oclass[NVDEV_ENGINE_DISP ] = nva0_disp_oclass;
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]279 device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]280 break;
281 case 0xaa:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]282 device->cname = "MCP77/MCP78";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]283 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggs73568592014-05-12 15:22:42 +1000[diff] [blame]284 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
Ben Skeggsc26fe842014-05-13 13:59:26 +1000[diff] [blame]285 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
Roy Splieta7e42012013-11-17 20:09:06 +0100[diff] [blame]286 device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass;
Martin Peres2f457362013-02-23 16:45:51 +0100[diff] [blame]287 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]288 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ilia Mirkin4019aaa2014-01-14 16:29:06 +1000[diff] [blame]289 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
Ben Skeggs08f6fbd2013-10-11 15:34:08 +1000[diff] [blame]290 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
Ben Skeggs29845062013-10-15 10:49:39 +1000[diff] [blame]291 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]292 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs9ca30372013-10-18 14:44:23 +1000[diff] [blame]293 device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]294 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]295 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
296 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]297 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggsbc985402014-08-10 04:10:24 +1000[diff] [blame^]298 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]299 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]300 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]301 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
Ilia Mirkin0d4a1452013-06-27 14:04:20 +1000[diff] [blame]302 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]303 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
Ilia Mirkin0d4a1452013-06-27 14:04:20 +1000[diff] [blame]304 device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]305 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
Ben Skeggsa8f8b482014-02-20 21:33:34 +1000[diff] [blame]306 device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]307 device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]308 break;
309 case 0xac:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]310 device->cname = "MCP79/MCP7A";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]311 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggs73568592014-05-12 15:22:42 +1000[diff] [blame]312 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
Ben Skeggsc26fe842014-05-13 13:59:26 +1000[diff] [blame]313 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
Roy Splieta7e42012013-11-17 20:09:06 +0100[diff] [blame]314 device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass;
Martin Peres2f457362013-02-23 16:45:51 +0100[diff] [blame]315 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]316 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ilia Mirkin4019aaa2014-01-14 16:29:06 +1000[diff] [blame]317 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
Ben Skeggs08f6fbd2013-10-11 15:34:08 +1000[diff] [blame]318 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
Ben Skeggs29845062013-10-15 10:49:39 +1000[diff] [blame]319 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]320 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs9ca30372013-10-18 14:44:23 +1000[diff] [blame]321 device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]322 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]323 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
324 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]325 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggsbc985402014-08-10 04:10:24 +1000[diff] [blame^]326 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]327 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]328 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]329 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
Ilia Mirkin0d4a1452013-06-27 14:04:20 +1000[diff] [blame]330 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]331 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
Ilia Mirkin0d4a1452013-06-27 14:04:20 +1000[diff] [blame]332 device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]333 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
Ben Skeggsa8f8b482014-02-20 21:33:34 +1000[diff] [blame]334 device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]335 device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]336 break;
337 case 0xa3:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]338 device->cname = "GT215";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]339 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggs73568592014-05-12 15:22:42 +1000[diff] [blame]340 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
Ben Skeggsc26fe842014-05-13 13:59:26 +1000[diff] [blame]341 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]342 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
Ben Skeggs7b49bd62012-12-04 12:18:59 +1000[diff] [blame]343 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]344 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggscf336012014-01-14 15:55:38 +1000[diff] [blame]345 device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
Ben Skeggs08f6fbd2013-10-11 15:34:08 +1000[diff] [blame]346 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
Ben Skeggs29845062013-10-15 10:49:39 +1000[diff] [blame]347 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]348 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs9ca30372013-10-18 14:44:23 +1000[diff] [blame]349 device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]350 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]351 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
352 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
Ben Skeggsadec9bc2014-06-12 18:31:32 +1000[diff] [blame]353 device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]354 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggsbc985402014-08-10 04:10:24 +1000[diff] [blame^]355 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]356 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]357 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]358 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
359 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
Ilia Mirkin0d4a1452013-06-27 14:04:20 +1000[diff] [blame]360 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
361 device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]362 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
363 device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
Ben Skeggsa8f8b482014-02-20 21:33:34 +1000[diff] [blame]364 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]365 device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]366 break;
367 case 0xa5:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]368 device->cname = "GT216";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]369 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggs73568592014-05-12 15:22:42 +1000[diff] [blame]370 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
Ben Skeggsc26fe842014-05-13 13:59:26 +1000[diff] [blame]371 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]372 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
Ben Skeggs7b49bd62012-12-04 12:18:59 +1000[diff] [blame]373 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]374 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggscf336012014-01-14 15:55:38 +1000[diff] [blame]375 device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
Ben Skeggs08f6fbd2013-10-11 15:34:08 +1000[diff] [blame]376 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
Ben Skeggs29845062013-10-15 10:49:39 +1000[diff] [blame]377 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]378 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs9ca30372013-10-18 14:44:23 +1000[diff] [blame]379 device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]380 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]381 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
382 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
Ben Skeggsadec9bc2014-06-12 18:31:32 +1000[diff] [blame]383 device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]384 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggsbc985402014-08-10 04:10:24 +1000[diff] [blame^]385 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]386 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]387 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]388 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
Ilia Mirkin0d4a1452013-06-27 14:04:20 +1000[diff] [blame]389 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
390 device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]391 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
392 device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
Ben Skeggsa8f8b482014-02-20 21:33:34 +1000[diff] [blame]393 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]394 device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]395 break;
396 case 0xa8:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]397 device->cname = "GT218";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]398 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggs73568592014-05-12 15:22:42 +1000[diff] [blame]399 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
Ben Skeggsc26fe842014-05-13 13:59:26 +1000[diff] [blame]400 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]401 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
Ben Skeggs7b49bd62012-12-04 12:18:59 +1000[diff] [blame]402 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]403 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggscf336012014-01-14 15:55:38 +1000[diff] [blame]404 device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
Ben Skeggs08f6fbd2013-10-11 15:34:08 +1000[diff] [blame]405 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
Ben Skeggs29845062013-10-15 10:49:39 +1000[diff] [blame]406 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]407 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs9ca30372013-10-18 14:44:23 +1000[diff] [blame]408 device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]409 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]410 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
411 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
Ben Skeggsadec9bc2014-06-12 18:31:32 +1000[diff] [blame]412 device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]413 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggsbc985402014-08-10 04:10:24 +1000[diff] [blame^]414 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]415 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]416 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]417 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
Ilia Mirkin0d4a1452013-06-27 14:04:20 +1000[diff] [blame]418 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
419 device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]420 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
421 device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
Ben Skeggsa8f8b482014-02-20 21:33:34 +1000[diff] [blame]422 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]423 device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]424 break;
425 case 0xaf:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]426 device->cname = "MCP89";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]427 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggs73568592014-05-12 15:22:42 +1000[diff] [blame]428 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
Ben Skeggsc26fe842014-05-13 13:59:26 +1000[diff] [blame]429 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]430 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
Ben Skeggs7b49bd62012-12-04 12:18:59 +1000[diff] [blame]431 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]432 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ilia Mirkin4019aaa2014-01-14 16:29:06 +1000[diff] [blame]433 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvaf_devinit_oclass;
Ben Skeggs08f6fbd2013-10-11 15:34:08 +1000[diff] [blame]434 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
Ben Skeggs29845062013-10-15 10:49:39 +1000[diff] [blame]435 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]436 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs9ca30372013-10-18 14:44:23 +1000[diff] [blame]437 device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]438 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]439 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
440 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
Ben Skeggsadec9bc2014-06-12 18:31:32 +1000[diff] [blame]441 device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]442 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggsbc985402014-08-10 04:10:24 +1000[diff] [blame^]443 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]444 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]445 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]446 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
Ilia Mirkin0d4a1452013-06-27 14:04:20 +1000[diff] [blame]447 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
448 device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]449 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
450 device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
Ben Skeggsa8f8b482014-02-20 21:33:34 +1000[diff] [blame]451 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]452 device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]453 break;
454 default:
455 nv_fatal(device, "unknown Tesla chipset\n");
456 return -EINVAL;
457 }
458
459 return 0;
460}