Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
| 25 | #include <core/gpuobj.h> |
Ben Skeggs | 1971f04 | 2012-08-19 15:58:38 +1000 | [diff] [blame] | 26 | #include <core/class.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 27 | |
| 28 | #include <subdev/fb.h> |
| 29 | #include <subdev/vm/nv04.h> |
| 30 | |
Ben Skeggs | bc98540 | 2014-08-10 04:10:24 +1000 | [diff] [blame^] | 31 | #include "priv.h" |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 32 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 33 | static int |
| 34 | nv04_dmaobj_bind(struct nouveau_dmaeng *dmaeng, |
| 35 | struct nouveau_object *parent, |
| 36 | struct nouveau_dmaobj *dmaobj, |
| 37 | struct nouveau_gpuobj **pgpuobj) |
| 38 | { |
Ben Skeggs | 8a57d27 | 2012-09-26 15:01:39 +1000 | [diff] [blame] | 39 | struct nv04_vmmgr_priv *vmm = nv04_vmmgr(dmaeng); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 40 | struct nouveau_gpuobj *gpuobj; |
| 41 | u32 flags0 = nv_mclass(dmaobj); |
| 42 | u32 flags2 = 0x00000000; |
Ben Skeggs | 8a57d27 | 2012-09-26 15:01:39 +1000 | [diff] [blame] | 43 | u64 offset = dmaobj->start & 0xfffff000; |
| 44 | u64 adjust = dmaobj->start & 0x00000fff; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 45 | u32 length = dmaobj->limit - dmaobj->start; |
| 46 | int ret; |
| 47 | |
Ben Skeggs | 6c1689a | 2012-10-08 12:58:23 +1000 | [diff] [blame] | 48 | if (!nv_iclass(parent, NV_ENGCTX_CLASS)) { |
| 49 | switch (nv_mclass(parent->parent)) { |
| 50 | case NV03_CHANNEL_DMA_CLASS: |
| 51 | case NV10_CHANNEL_DMA_CLASS: |
| 52 | case NV17_CHANNEL_DMA_CLASS: |
| 53 | case NV40_CHANNEL_DMA_CLASS: |
| 54 | break; |
| 55 | default: |
| 56 | return -EINVAL; |
| 57 | } |
| 58 | } |
| 59 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 60 | if (dmaobj->target == NV_MEM_TARGET_VM) { |
Ben Skeggs | 8a57d27 | 2012-09-26 15:01:39 +1000 | [diff] [blame] | 61 | if (nv_object(vmm)->oclass == &nv04_vmmgr_oclass) { |
| 62 | struct nouveau_gpuobj *pgt = vmm->vm->pgt[0].obj[0]; |
| 63 | if (!dmaobj->start) |
| 64 | return nouveau_gpuobj_dup(parent, pgt, pgpuobj); |
| 65 | offset = nv_ro32(pgt, 8 + (offset >> 10)); |
| 66 | offset &= 0xfffff000; |
| 67 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 68 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 69 | dmaobj->target = NV_MEM_TARGET_PCI; |
| 70 | dmaobj->access = NV_MEM_ACCESS_RW; |
| 71 | } |
| 72 | |
| 73 | switch (dmaobj->target) { |
| 74 | case NV_MEM_TARGET_VRAM: |
| 75 | flags0 |= 0x00003000; |
| 76 | break; |
| 77 | case NV_MEM_TARGET_PCI: |
| 78 | flags0 |= 0x00023000; |
| 79 | break; |
| 80 | case NV_MEM_TARGET_PCI_NOSNOOP: |
| 81 | flags0 |= 0x00033000; |
| 82 | break; |
| 83 | default: |
| 84 | return -EINVAL; |
| 85 | } |
| 86 | |
| 87 | switch (dmaobj->access) { |
| 88 | case NV_MEM_ACCESS_RO: |
| 89 | flags0 |= 0x00004000; |
| 90 | break; |
| 91 | case NV_MEM_ACCESS_WO: |
| 92 | flags0 |= 0x00008000; |
| 93 | case NV_MEM_ACCESS_RW: |
| 94 | flags2 |= 0x00000002; |
| 95 | break; |
| 96 | default: |
| 97 | return -EINVAL; |
| 98 | } |
| 99 | |
| 100 | ret = nouveau_gpuobj_new(parent, parent, 16, 16, 0, &gpuobj); |
| 101 | *pgpuobj = gpuobj; |
| 102 | if (ret == 0) { |
| 103 | nv_wo32(*pgpuobj, 0x00, flags0 | (adjust << 20)); |
| 104 | nv_wo32(*pgpuobj, 0x04, length); |
| 105 | nv_wo32(*pgpuobj, 0x08, flags2 | offset); |
| 106 | nv_wo32(*pgpuobj, 0x0c, flags2 | offset); |
| 107 | } |
| 108 | |
| 109 | return ret; |
| 110 | } |
| 111 | |
Ben Skeggs | bc98540 | 2014-08-10 04:10:24 +1000 | [diff] [blame^] | 112 | struct nouveau_oclass * |
| 113 | nv04_dmaeng_oclass = &(struct nvkm_dmaeng_impl) { |
| 114 | .base.handle = NV_ENGINE(DMAOBJ, 0x04), |
| 115 | .base.ofuncs = &(struct nouveau_ofuncs) { |
| 116 | .ctor = _nvkm_dmaeng_ctor, |
| 117 | .dtor = _nvkm_dmaeng_dtor, |
| 118 | .init = _nvkm_dmaeng_init, |
| 119 | .fini = _nvkm_dmaeng_fini, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 120 | }, |
Ben Skeggs | bc98540 | 2014-08-10 04:10:24 +1000 | [diff] [blame^] | 121 | .bind = nv04_dmaobj_bind, |
| 122 | }.base; |